Design Engineer Front End

Job Description

Company Description RV Skills Design Centre, formerly known as RV-VLSI, is a premier VLSI, Embedded Systems, and AI skill development center established in 2006 by the RV group of educational institutions. Managed by industry-experienced professionals, RV Skills offers innovative full-time and part-time programs to enhance the employability of engineering graduates and working professionals. As a trusted partner for industry hiring and training, the center has established a benchmark for skill development programs in India through collaborations with EDA vendors, foundries, and industry experts. Role Description This is a full-time on-site role for a Design Engineer, based in Bengaluru. The Design Engineer will be an experienced and passionate RTL Verification Trainer to design, develop, and deliver training programs focused on RTL (Register Transfer Level) design verification methodologies. The ideal candidate should have a strong background in ASIC design verification, proficiency in industry-standard tools, and a solid understanding of verification techniques such as UVM, System Verilog, and functional coverage. The trainer will be responsible for upskilling fresh graduates, and industry professionals. Key Responsibilities Design and deliver structured RTL verification training modules tailored for varying expertise levels (beginner to advanced). Develop hands-on lab sessions, real-world case studies, and projects to enhance practical understanding. Conduct live instructor-led training sessions. Evaluate training effectiveness through assessments, feedback, and performance monitoring. Stay updated with the latest verification trends, tools, and methodologies, and continuously refresh training materials. Provide mentorship and technical support to trainees during and after the training sessions. Develop certification exams to benchmark trainee competencies. Document training materials, presentations, lab manuals, and FAQs. Required Skills and Qualifications Bachelor’s or Master’s degree in Electronics, Electrical. Experience in RTL verification, preferably in ASIC/FPGA domains or teaching in any institute. Strong expertise in: Verilog and digital circuits SystemVerilog for verification, UVM(optional) RTL simulation tools (e.g., Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa) Previous experience in training, mentoring, or technical leadership is a strong plus. Excellent communication, presentation, and interpersonal skills. Ability to simplify complex concepts and adapt to various learning styles. Please sending your resumes to info@rv-skills.com.