273 Systemverilog Jobs

Company Description RV Skills Design Centre, formerly known as RV-VLSI, is a premier VLSI, Embedded Systems, and AI skill development center established in 2006 by the RV group of educational institutions. Managed by industry-experienced professionals, RV Skills offers innovative full-time and part-time programs to enhance the employability of engineering graduates and working professionals. As a trusted partner for industry hiring and training, the center has established a benchmark for skill development programs in India through collaborations with EDA vendors, foundries, and industry experts. Role Description This is a full-time on-site role for a Design Engineer, based in Bengaluru. The Design Engineer will be an experienced and passionate RTL Verification Trainer to design, develop, and deliver training programs focused on RTL (Register Transfer Level) design verification methodologies. The ideal candidate should have a strong background in ASIC design verification, proficiency in industry-standard tools, and a solid understanding of verification techniques such as UVM, System Verilog, and functional coverage. The trainer will be responsible for upskilling fresh graduates, and industry professionals. Key Responsibilities Design and deliver structured RTL verification training modules tailored for varying expertise levels (beginner to advanced). Develop hands-on lab sessions, real-world case studies, and projects to enhance practical understanding. Conduct live instructor-led training sessions. Evaluate training effectiveness through assessments, feedback, and performance monitoring. Stay updated with the latest verification trends, tools, and methodologies, and continuously refresh training materials. Provide mentorship and technical support to trainees during and after the training sessions. Develop certification exams to benchmark trainee competencies. Document training materials, presentations, lab manuals, and FAQs. Required Skills and Qualifications Bachelor’s or Master’s degree in Electronics, Electrical. Experience in RTL verification, preferably in ASIC/FPGA domains or teaching in any institute. Strong expertise in: Verilog and digital circuits SystemVerilog for verification, UVM(optional) RTL simulation tools (e.g., Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa) Previous experience in training, mentoring, or technical leadership is a strong plus. Excellent communication, presentation, and interpersonal skills. Ability to simplify complex concepts and adapt to various learning styles. Please sending your resumes to info@rv-skills.com.

Role: Senior Design Verification Engineer (PCIe) Role: Bangalore Job Summary: We are looking for a highly experienced and motivated Senior Design Verification Engineer with a deep understanding of the PCIe protocol and hands-on experience in SystemVerilog and UVM. The ideal candidate will lead verification activities for complex PCIe subsystems or SoCs, and contribute to building scalable, reusable verification infrastructure. Key Responsibilities: Develop UVM-based verification environments for PCIe IPs or SoCs . Define and execute comprehensive verification plans for PCIe Gen3/Gen4/Gen5/Gen6 features. Drive testbench development, stimulus generation, score boarding, and coverage closure. Validate protocol compliance including LTSSM, TLP/DLLP, BAR/Address decoding, and interrupt mechanisms. Work closely with RTL, DFT, and system validation teams for debug and feature bring-up. Conduct assertion-based verification and participate in formal verification as needed. Collaborate with cross-functional teams to ensure successful first-silicon quality. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in ECE 8+ years of experience in ASIC/SoC design verification. Proven expertise in System Verilog, UVM, and complex testbench development. Deep knowledge of PCIe protocol (Gen3/Gen4/Gen5/Gen6). Experience in verifying Root Complex (RC) and Endpoint (EP) configurations. Familiarity with AMBA protocols (AXI, AHB) and memory-mapped IO. Proficiency with EDA tools like VCS, Questa, Verdi, Sim Vision. Strong debugging and analytical skills, particularly with PCIe protocol analyzers and simulation waveforms. Scripting proficiency in Python, Perl, TCL, or Shell for automation. Nice to Have: Knowledge of low power (UPF) and DFT concepts. Familiarity with Formal Verification, Portable Stimulus, or Emulation. Exposure to hardware validation, bring-up, or post-silicon debug. Domain experience in datacenter, storage, networking, or automotive industries. Soft Skills: Strong communication and documentation skills Problem-solving mindset and attention to detail Leadership in driving verification tasks and mentoring junior engineers Job Types: Full-time, Permanent Pay: ₹4,000,000.00 - ₹5,000,000.00 per year Benefits: Cell phone reimbursement Health insurance Paid time off Provident Fund Schedule: Day shift Work Location: In person

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Questa Simulation Product It is a core R&D team working on multiple verticals of Simulation. A very energetic and enthusiastic team of motivated individuals. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role ? Job Qualification: An ideal candidate should have skills below: B.Tech or M.Tech in Computer Science & Engineering (CSE), Electrical Engineering (EE), or Electronics & Communication Engineering (ECE) from a reputable engineering institution having 5-7 years of experience. Strong knowledge of C/C++, algorithms, and data structures. Familiarity with compiler concepts and optimizations. Experience with UNIX and/or LINUX platforms is essential. Excellent problem-solving and analytical skills. Self-motivated with the ability to work independently and guide others towards successful project completion. We are not looking for superheroes, just super minds! Having the below skills will be an added advantage: Strong understanding of basic digital electronics concepts. Familiarity with machine learning (ML) and artificial intelligence (AI) algorithms, particularly their implementation in data-driven tasks. Proficiency in hardware description languages such as Verilog, SystemVerilog, and VHDL. Experience with parallel algorithms and job distribution techniques. Exposure to simulation or formal verification methodologies is a plus. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #DVT

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, we’ve got quite a lot to offer. How about you? We blur the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow’s idea. We take what the future promises tomorrow and make it real for our customers today. Join us - where your career meets tomorrow. Looking for Siemens EDA Ambassadors- QuestaSim (Simulation) R&D team (strong AI/ML background) This is your role In this role, you will, craft and develop AI/ML-driven algorithms and solutions to improve simulation tools' performance and capabilities. Contribute to building state-of-the-art engines and components, integrating machine learning techniques into simulation and verification workflows. Contribute to the development and improvement of production-quality components, algorithms, and engines while supporting and improving existing codebases. Solve complex, open-ended problems in collaboration with a senior group of engineers in a fast-paced and multifaceted environment. Apply technical expertise in AI/ML frameworks, data-driven problem solving, and traditional simulation technologies to achieve project milestones. Stay self-motivated, disciplined, and focused while driving innovation within the team. Required Qualifications We are seeking a graduate with Bachelor’s or Master’s degree in Computer Science, Artificial Intelligence, Electrical Engineering, or a related technical field from an accredited institution. We value your experience with conceptualizing, defining, architecting, and implementation of an open-ended problem scope or new insights. Hands-on experience with AI/ML techniques, including supervised and unsupervised learning, neural networks, and reinforcement learning. Strong proficiency in programming languages like C/C++ and Python, along with strong foundations in algorithms and data structures. Knowledge of machine learning and deep learning frameworks. Strong understanding of Compiler Concepts, Optimizations, and parallel computing. Experience working on UNIX and/or LINUX platforms. Excellent problem-solving and analytical skills. Proven track record to work independently, take ownership of tasks, and deliver results A plus! Basic knowledge of Digital Electronics and concepts related to SystemVerilog, Verilog, and VHDL. Exposure to Simulation technologies or Formal-based Verification methodologies is a plus! We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.

ASIC DFx - MTS Silicon Design Engineer New Dehli, India Engineering 66377 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ AECG ASIC DFx - MTS SILICON DESIGN ENGINEER THE ROLE: AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. THE PERSON: As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES: Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications. Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS. Work with multi-functional teams and handling schedules Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Minimum 8 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus. Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Good understanding of RTL quality checks such as SGLINT, SGDFT, CDC, RDC etc Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. is a plus Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with formal model checking for ASICs and FPGAs, SystemVerilog and SystemVerilog Assertions. Experience with formal verification EDA tools. Experience with model checking frameworks such as Murphi or TLA+. Preferred qualifications: Master's or PhD degree in Computer Science, Electrical Engineering, or a related field. Experience working with one or more formal verification tools, such as JasperGold, VC Formal, Questa Formal, 360-DV. Experience with a scripting language like Perl, Tcl or Python. Experience with propositional logic, theorem proving and tools such as Z3. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Partner with hardware architects for formal specifications and verification of system-level properties. Develop highly abstract models of various designs and prove architectural correctness within a model and consistency across models. Plan formal verification strategy, create the properties and constraints for complex digital design blocks. Translate system-level formal specifications into precise constraints for individual logical blocks. Architect and implement reusable formal verification components. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Minimum qualifications: Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. 3 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture. Experience in handling low power schemes, power roll up and power estimations. Experience in Register-Transfer Level (RTL) quality sign-off flows (e.g., CDC, RDC, Lint, Power Intent or LEC). Experience with Perl or Python. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science. Experience with methodologies for low power estimation, timing closure, and synthesis. Experience with computer architecture. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc. Perform Register-Transfer Level (RTL) development (SystemVerilog), RTL integration (Perl), debug functional/performance simulations. Perform RTL quality checks including Lint, CDC, RDC, Synthesis, Unified Power Format (UPF) checks. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X). Job Description Own and deliver on design verification of complex Intellectual Property (IP) or Subsystem or complete full chip (SoC) level features and mixed signal subsystems. Collaborate with design, applications, product and test engineering teams to ensure the implementation meets both architectural and micro-architectural intent for complex IPs and feature areas of subsystem and SoC. Develop test methodologies, strategies, reviews and supervise execution of test plans. Develop verification environments involving directed, formal, constrained random stimulus and coverage driven verification; run and debug simulations to drive quality. Execute test plans for complex design areas or products by leveraging teams, as well as through individual contributions. Set targets for test coverage and strategy to achieve coverage. Ensure quality of test plan execution across broad areas. Apply Agile development methodologies including code reviews, sprint planning, and feature deployment. Innovate to improve verification efficiency through methodologies, processes or tools. Provide technical leadership through coaching, mentorship, modeling and teamwork. Demonstrate ADI core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact and Diversity & Inclusion. Minimum Qualifications Bachelor’s or master’s degree, in Engineering (Electronic Engineering) or equivalent Excellent debugging and analytical skills. 10 – 12 years in ASIC design verification. Additional Qualifications & Experience: Verification Planning tools (ePlanner, vManager) Property Specification Language (PSL), SystemVerilog Assertions (SVA) Proficient with Cadence Suite (Virtuoso IUS) Scripting languages (Shell, TCL, PERL, Python) for bench automation Hands-On UVM at user level, pseudo and constrained random techniques, assertion-based verification techniques with System Verilog. Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by designer. Coding up in C tests on M3 Series Cortex based products. Building and leading small verification teams. Strong interpersonal, teamwork and communication skills are required. Be self-motivated and enthusiastic. Strong level of English speaking and writing. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ AECG ASIC DFx - MTS SILICON DESIGN ENGINEER The Role AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. THE PERSON: As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES: Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications. Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS. Work with multi-functional teams and handling schedules Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Minimum 8 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus. Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Good understanding of RTL quality checks such as SGLINT, SGDFT, CDC, RDC etc Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. is a plus Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

ALTEN Calsoft Labs expertise in VLSI services can transfer your product ideas into cost-effective System on Chip (SoC) designs for Networking, Mobile Multimedia and Consumer Electronics solutions with a faster time to market. Some of the key highlights of our Semiconductor Practice include - Multiple engagements with Tier-1 silicon vendors and fabless semiconductor companies from Spec-to-Netlist Focus on latest verification methodologies - OVM, VMM and UVM Verification & validation experience of complex SOC designs up to 28 nm process technology Expertise in implementing complex ASICs in 130nm, 90nm, 65nm & 40nm Skills:- uvm, systemverilog, rtl, semiconductor, cdc, lint, Verilog and VLSI

NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.” What You’ll Be Doing Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology. Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. You will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks. What We Need To See B.Tech./ M.Tech or equivalent experience 5+ years of relevant experience Experience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog Expertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA) Experience in developing and working in functional coverage based constrained random verification environments Background in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug Ways To Stand Out From The Crowd Excellent knowledge of PCIE protocol - Gen3 and above Good understanding of the system level architecture of PCIE/CXL-based designs Perl, Python or similar scripting and SW programming language experience Good debugging and analytical skills Good interpersonal skills & dream to work as a great teammate With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. JR1998093

SMTS Silicon Design Engineer Bangalore, India Engineering 66762 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Lead Verification Engineer THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. Expertise in Verilog, System Verilog, and Object-Oriented Programming Experience with UVM or similar Verification Methodology Requires strong Computer Architecture knowledge Comfortable in python / perl and editing / maintaining scripts Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out Experience with DRAM controllers, DDR Phys or DRAM Interface Protocols is a plus. Strong communication skills and the ability to work independently as well as in a cross-site team environment ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR5 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SILICON DESIGN ENGINEER 2 (AECG ASIC - SoC verification Engineer) The Role The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 2+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench under supervision from team lead. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification will be a plus Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Minimum qualifications: Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering or equivalent practical experience. 3 years of experience with standard GPU workloads like Manhattan/3DMark. Experience with GPU architecture and AMBA Bus protocols like AHB/AXI/ACE. Preferred qualifications: Master's degree or PhD in Electrical Engineering or Computer Science, or a related field. Experience with performance verification of ASICs and ASIC components. Experience with verification of low power techniques. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Be part of a team to verify complex digital design blocks (e.g., CPU, Graphics Processing Unit (GPU), Image processor) by understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER The Role We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. The Person You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Develop/Maintain tests for functional verification and performance verification at the core level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Create hardware emulation build to verify the IP functional performance Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility Provide technical support to other teams Preferred Experience Good at C/C++ Familiarity with SystemVerilog and modern verification libraries like UVM Experience/Background on Computing/Graphics is a benefit Experience with OpenGL/OpenCL/D3D programming is a benefit Academic Credentials Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Job Summary We are looking for an experienced Senior RTL Design Engineer with a strong background in SoC architecture, logic design, and RTL development. This role is ideal for candidates who are passionate about software-driven digital hardware design and have in-depth knowledge of modern SoC systems, protocols, and low-power design Responsibilities : Design and implement scalable RTL architectures for complex SoC components using Verilog/SystemVerilog. Develop and maintain logic blocks aligned with architectural and functional specifications. Collaborate with design verification and architecture teams to define module interfaces and performance metrics. Implement low-power design techniques using software methodologies such as clock gating, power domain partitioning, etc. Model asynchronous interfaces and multi-clock domain logic for integration into larger SoC platforms. Analyze design performance and optimize RTL for area, power, and logical efficiency. Write clean, reusable, and synthesis-friendly RTL code following best practices and coding standards. Simulate and debug logic design using industry tools and waveform analysis. Integrate IPs and subsystems in a modular and maintainable way using software configuration and scripting Skills & Experience : 5+ years of experience in RTL design, logic development, and micro-architecture. Strong command over Verilog/SystemVerilog and digital design methodologies. Proven experience in designing software-driven SoC architectures with modular, configurable RTL. In-depth knowledge of AMBA protocols - AXI, AHB, APB. Experience in multi-clock domain logic and asynchronous interface design. Proficiency in low-power RTL techniques including power-aware coding and UPF/CPF flows (logic-level). Familiarity with RTL design tools such as Simulation (ModelSim/VCS), Linting, CDC/RDC tools. Scripting skills in TCL, Python, or Shell for automating RTL testbenches, configuration, or IP Qualifications : Bachelors or Masters degree in, Computer Engineering, or related field. Exposure to software-based SoC modeling or transaction-level modeling (TLM). Experience with design abstraction, reusable IP architecture, and configurable RTL components. Knowledge of interfaces such as USB, PCIe, SD/eMMC at RTL level. (ref:hirist.tech)

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Collaborate with design and verification teams to understand digital design specifications and ensure comprehensive verification coverage. Develop and execute verification plans for ASIC/FPGA designs using directed tests and/or SystemVerilog with UVM methodologies. Build and maintain testbenches, verification components, and assertion-based verification structures to validate complex digital designs. Perform simulation, debugging, and coverage analysis to ensure functional correctness and compliance with design requirements. Contribute to the automation of verification flows through scripting (Python, Perl, Bash) to improve productivity and consistency. Work in Unix/Linux environments for development, simulation, and regression testing activities. Document verification strategies, results, and maintain clear communication with cross-functional teams to support project milestones. Actively participate in code reviews and contribute to continuous improvement of verification methodologies and best practices. Mandatory Skills 4+years Strong in digital design. Skills in ASIC / FPGA verification (directed test or System Verilog / UVM) A good knowledge of simulation flow Good basis in scripting Python, Perl, Bash Proficiency in Unix environment.

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Collaborate with design and verification teams to understand digital design specifications and ensure comprehensive verification coverage. Develop and execute verification plans for ASIC/FPGA designs using directed tests and/or SystemVerilog with UVM methodologies. Build and maintain testbenches, verification components, and assertion-based verification structures to validate complex digital designs. Perform simulation, debugging, and coverage analysis to ensure functional correctness and compliance with design requirements. Contribute to the automation of verification flows through scripting (Python, Perl, Bash) to improve productivity and consistency. Work in Unix/Linux environments for development, simulation, and regression testing activities. Document verification strategies, results, and maintain clear communication with cross-functional teams to support project milestones. Actively participate in code reviews and contribute to continuous improvement of verification methodologies and best practices. Skills Must have 1 position: 6+y, 1 position: 4+y Strong in digital design. Skills in ASIC / FPGA verification (directed test or System Verilog / UVM) A good knowledge of simulation flow Good basis in scripting Python, Perl, Bash... Proficiency in Unix environment. Good communication skills Nice to have Bachelor's/Master's in ECE Other Languages English: B2 Upper Intermediate Seniority Regular Hyderabad, IN, India Req. VR-115262 Manual Testing Automotive Industry 20/06/2025 Req. VR-115262

Required Skills and Experience: Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts. Experience in HVL such as System Verilog, UVM/OVM & System C. Experience in HDL such as Verilog. Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia. Familiarity with Power-aware Verification, GLS, Test vector generation is a plus. Exposure to Version managers like Clearcase/Perforce. Scripting language like Perl, Tcl or Python. Analytical and Debugging skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 75630 Responsibilities Collaborate with design engineers to understand design specifications and requirements. Develop and execute verification plans to ensure the functionality and performance of digital designs. Create and maintain testbenches and verification environments using SystemVerilog or similar languages. Write and debug test cases to verify design functionality and identify issues. Perform simulation and analysis to validate design performance and compliance with specifications. Document verification results and provide feedback to the design team.Stay updated with the latest verification methodologies and tools. Required Experience And Skills Desired Experience and Skills

Qualifications and Skills for DV Positions: Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience 7/10+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification 7/ 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in development of UVM based verification environments from scratch Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle7 Experience with verification of ARM/RISC-V based CPU sub-systems or SoCs Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience with revision control systems like Mercurial(Hg), Git or SVN

Who We Are We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies, and improve lives. www.silabs.com About the team The IoT Digital Design team is a state-of-art IC design team focused on producing world class Wireless MCU SoCs. The architecture specification, design, verification, emulation, and implementation of the Wireless MCU SoCs is the responsibility of the IoT Digital team. These SoCs include an embedded CPU system with analog and digital peripherals, advanced security, advanced power management, and best in class radios to support a wide range of wireless IoT applications and standards. We strive to provide best in class technology solutions through innovation in custom RISC-V Cores and AI/ML components. What we’re looking for: Silicon Labs is seeking a Lead Engineer for the Emulation and Prototyping Platform (EPP) team. The position requires a thorough FPGA development and deployment background with focus on automation to efficiently deliver an emulation platform. Technical leadership and Mentorship experience preferred. Skills you’ll need: Deliver emulation platforms to internal groups to enable pre-silicon verification, validation, and software development. Provide hands-on technical leadership and training for staff. Schedule development, task assignment, and tracking to meet project milestones. Robust quality assurance metrics defined, documented, measured, and reported. Collaboration with internal teams and external vendors to define needs and set expectations. Identify and execute strategic initiatives to advance team delivery. Coordinate emulation and prototyping activities with a global engineering team. Communicates technical information and schedules to senior members of the management team. Functional Role: Worked with industry standard emulation and simulation tools. Ability to understand HDL language and understand HW/SW Codesign. Understand CDC, STA and other timing considerations in the context of FPGA. Advanced knowledge of clocking, memory and other FPGA needs. Experience with Lab equipment like Digital Signal Analyzer and Signal Generator. Knowledge of scripting languages like TCL, perl and python. Previous experience with Linux based version control environment (GIT, Perforce, Methodics). Worked with SystemVerilog and UVM testbench. Job Automation skills like Jenkins and Docker. Embedded C programming. PCB knowledge for schematic, layout, signal integrity consideration etc. Chip integration and bring-up experience. SW, Tooling and DevOps knowledge. Education and/or Experience: 6-8 years in Industry Bachelor or master’s degree in electrical and/or Computer Engineering Benefits & Perks: Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability. Show more Show less

Looking for Siemens EDA Ambassadors- QuestaSim (Simulation) R&D team (strong AI/ML background) This is your role In this role, you will, craft and develop AI/ML-driven algorithms and solutions to improve simulation tools' performance and capabilities. Contribute to building state-of-the-art engines and components, integrating machine learning techniques into simulation and verification workflows. Contribute to the development and improvement of production-quality components, algorithms, and engines while supporting and improving existing codebases. Solve complex, open-ended problems in collaboration with a senior group of engineers in a fast-paced and multifaceted environment. Apply technical expertise in AI/ML frameworks, data-driven problem solving, and traditional simulation technologies to achieve project milestones. Stay self-motivated, disciplined, and focused while driving innovation within the team. Required Qualifications We are seeking a graduate with Bachelors or Masters degree in Computer Science, Artificial Intelligence, Electrical Engineering, or a related technical field from an accredited institution. We value your experience with conceptualizing, defining, architecting, and implementation of an open-ended problem scope or new insights. Hands-on experience with AI/ML techniques, including supervised and unsupervised learning, neural networks, and reinforcement learning. Strong proficiency in programming languages like C/C++ and Python, along with strong foundations in algorithms and data structures. Knowledge of machine learning and deep learning frameworks. Strong understanding of Compiler Concepts, Optimizations, and parallel computing. Experience working on UNIX and/or LINUX platforms. Excellent problem-solving and analytical skills. Proven track record to work independently, take ownership of tasks, and deliver results A plus! Basic knowledge of Digital Electronics and concepts related to SystemVerilog, Verilog, and VHDL. Exposure to Simulation technologies or Formal-based Verification methodologies is a plus!

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Job Description We are seeking a highly skilled and experienced Staff Engineer for Functional Modeling & Verification to join our innovative team in Bengaluru, India. As a Staff Engineer, you will play a crucial role in shaping our technical direction, leading complex projects, and mentoring junior engineers. Lead architectural decisions and provide technical guidance to cross-functional teams Collaborate with product managers and other stakeholders to define technical requirements and solutions Conduct code reviews and ensure code quality across projects Mentor and guide junior engineers, fostering their professional growth Identify and resolve complex technical issues across multiple projects Stay current with emerging technologies and industry trends, recommending innovations to improve our tech stack Contribute to the development of engineering best practices and coding standards Participate in system design discussions and technical planning sessions Optimize existing systems for improved performance and scalability Hands-on experience in C++ & System C based Model development/test creation Prior Experience with C based Tests/Test bench development Python coding would be a plus Knowledge on NAND concepts will be an advantage Knowledge on Memory and Digital Design Concepts would be preferable (SRAM/DRAM/ROM/Flash) Circuits/Logic Participate in design / modeling reviews and provide technical guidance to junior engineers. Document all phases of Modeling releases and development for future reference and maintenance. Stay updated with the latest technologies and trends in NAND Flash and Modeling. Languages Expertise C, C++, Python, System C, SystemVerilog/UVM will be a plus Tool Expertise VisualStudio, Git, Bitbucket Hands-on contributions coding C++ & System C models & test creation Debug issues in Firmware environment Validating the developed model using SV/UVM testbench Debug failures and root-cause it by interacting with other teams/groups Etc. Qualifications Qualifications Bachelor's or Master's degree in Computer Science or a related field BE/BTech/ME/MTech in Engineering with Computer Science, ECE or related field MSc/MCA in Computer Science or a related field 13+ years of software engineering experience, with a proven track record of leading complex technical projects Expert-level proficiency in one or more programming languages such as Java, Python, or C++ Strong experience with cloud platforms (e.g., AWS, Azure, GCP) and distributed systems In-depth knowledge of system design, architecture, and performance optimization Proficiency in version control systems, preferably Git Ability to work effectively in a fast-paced, agile environment Strong analytical and detail-oriented approach to software development Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Show more Show less

Sr.Lead Silicon Design Engineer - FPGA Design Hyderabad, India Engineering 66386 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be implemented and verified Build Requirements Spec, Design spec, test plan and test spec documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to implement the new features and write the new feature tests and any required changes to the test environment Debug test failures to determine the root cause; work with other RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Minimum of 15 years of design and development experience, preferably in a customer facing role Minimum of 10 years of experience in FPGA VHDL and/or Verilog design, AMD technology and tools, FPGA verification and test Experienced in analysing customer requirements, effort estimation and committing a schedule for delivery Interaction with Architects, other RTL engineers and SW engineers to define system level requirements and usecases Leading a group of RTL engineers to deliver on customer commitments Experienced with Verilog, System Verilog, and C programming Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Developing UVM based verification frameworks and testbenches, processes and flows Experience in HW testing, including working with test equipment, logic and traffic analyzers, test generators, etc. Experience in designing complex systems involving one or more of the following technologies: PCIe, Ethernet, TCP/IP, Packet processing, USB, etc. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, and shell are preferred. ACADEMIC CREDENTIALS: Top class Bachelors or Master's degree in Electronic Engineering Track record of high academic achievement #LI-PS1 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.