SystemC Hardware Modeling and System Architecture

Job Description

Job Requirements We are seeking a highly skilled SystemC Hardware Modeling and System Architecture Engineers to join our dynamic team. The ideal candidate will have extensive experience in system-level modeling, performance analysis, and architecture design using SystemC/TLM . You will play a crucial role in defining and optimizing next-generation hardware architectures, enabling early software development, and defining hardware-software co-design methodologies. Develop and maintain SystemC IP library for reuse across multiple projects. Ensure modularity, scalability, and maintainability of SystemC IP components. Optimize and standardize SystemC-based IP models for integration into larger SoC platforms. Develop and maintain SystemC-based transaction-level models (TLM) for SoC (System-on-Chip) architectures. Conduct performance analysis, power modeling, and system optimization to guide architecture decisions. Define and implement hardware/software co-simulation environments for early-stage software development. Work closely with RTL design teams to ensure alignment between system models and final hardware implementations. Collaborate with software, firmware, and verification teams to enable pre-silicon verification / validation and bring-up. Develop high-level system models to evaluate trade-offs in memory hierarchy, interconnects, and processing elements. Support the integration of virtual prototypes into larger simulation frameworks. Optimize simulation performance to support large-scale system-level validation. Bachelor’s, or Master’s in Electrical Engineering, Computer Engineering, or a related field . 5+ years of experience in C++ , SystemC/TLM2.0 modeling for hardware architectures. Strong knowledge of computer architecture, SoC design, and hardware-software interaction . Proficiency in C++ programming and SystemC modeling techniques . Experience with performance modeling, cache coherency, and memory subsystem analysis . Familiarity with hardware simulation tools , virtual platforms, and hybrid emulation environments. Hands-on experience with embedded systems, firmware, and device driver development . Strong debugging and profiling skills for hardware/software interaction. Preferred Qualifications: Familiarity with hardware functions, peripherals, Bus Fabrics, RISC-V, and SoC design . Knowledge of RTL design, and high-level synthesis (HLS) . Background in system performance benchmarking and optimization . Proficiency in Python, scripting, and automation for simulation frameworks. Work Experience Required Skills and Experience Bachelor’s, or Master’s in Electrical Engineering, Computer Engineering, or a related field . 1-2 years of experience in C++ , SystemC/TLM2.0 modeling for hardware architectures. Strong knowledge of computer architecture, SoC design, and hardware-software interaction . Proficiency in C++ programming and SystemC modeling techniques . Experience with performance modeling, cache coherency, and memory subsystem analysis . Familiarity with hardware simulation tools , virtual platforms, and hybrid emulation environments. Hands-on experience with embedded systems, firmware, and device driver development . Strong debugging and profiling skills for hardware/software interaction