Posted:1 day ago|
Platform:
On-site
Part Time
Define and implement DFT architecture and strategy for complex SoCs and ASICs
Insert and verify scan chains, MBIST, LBIST, boundary scan (JTAG), and other test structures
Develop and maintain ATPG (Automatic Test Pattern Generation) patterns and flows
Work closely with RTL designers, verification teams, and physical design teams to ensure DFT requirements are met
Debug DFT-related issues during simulation, emulation, and silicon bring-up
Perform timing analysis and constraints development for DFT logic
Drive silicon validation and yield improvement initiatives related to DFT
Document DFT design and verification methodology
Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation
Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.)
Good understanding of RTL design, synthesis, and timing closure
Knowledge of safety-critical or automotive DFT requirements (ISO 26262)
Familiarity with scripting (Perl, Python, Tcl) for automation
Excellent problem-solving and debugging skills
Strong communication and teamwork abilities
Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation
Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.)
Good understanding of RTL design, synthesis, and timing closure
Knowledge of safety-critical or automotive DFT requirements (ISO 26262)
Familiarity with scripting (Perl, Python, Tcl) for automation
Excellent problem-solving and debugging skills
Strong communication and teamwork abilities
Quest Global
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Hyderābād
Experience: Not specified
Salary: Not disclosed
Hyderābād
Experience: Not specified
Salary: Not disclosed
