1623 Tcl Jobs

Alternate Job Titles: ASIC Digital Design, Staff Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and experienced digital design engineer with a deep-rooted curiosity for advancing technology. With a strong foundation in RTL coding, microarchitecture, and high-speed digital IP, you thrive on tackling complex engineering challenges and delivering robust, scalable solutions. You are comfortable navigating the nuances of cutting-edge SERDES IP development and enjoy collaborating with cross-functional teams to deliver industry-leading results. Your proactive nature keeps you ahead of the curve, and your keen problem-solving abilities allow you to identify and resolve issues swiftly. You communicate effectively, ensuring your ideas are heard and understood, and you take pride in mentoring peers and contributing to a culture of continuous learning. You value diversity, demonstrate adaptability in a fast-paced environment, and bring both creativity and discipline to your work. Your technical acumen is matched by your drive to innovate, automate, and optimize design flows, making you an invaluable asset to any team focused on delivering world-class silicon solutions. What You’ll Be Doing: Analyzing and understanding complex IP specifications, clock architectures, and interface requirements for high-speed SERDES IP. Designing, implementing, and optimizing Verilog RTL code to meet stringent performance, area, and power goals. Debugging and verifying advanced digital features to ensure functional correctness and compliance with industry standards Developing and automating design flows and scripts using Perl, Tcl, or Python to enhance productivity and streamline processes. Collaborating with cross-functional teams, including analog, verification, and validation groups, to resolve technical challenges creatively. Participating in design reviews, providing technical leadership, and contributing to best practice methodologies for digital IP development. Staying current with industry trends and integrating innovative techniques into the design and verification process. The Impact You Will Have: Enable the delivery of next-generation high-speed SERDES IP that powers a diverse range of customer products. Drive innovation in digital design methodologies, boosting design efficiency and product quality. Ensure Synopsys DesignWare IP remains at the forefront of performance, reliability, and feature support in the global market. Facilitate seamless integration of IP into customer SoC designs, accelerating time-to-market for industry leaders. Mentor and uplift the technical capabilities of team members, fostering a culture of collaboration and excellence. Contribute to Synopsys' reputation as a trusted partner for silicon-proven, high-performance IP solutions. Support continuous improvement by identifying and implementing process and technology enhancements. What You’ll Need: Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field. 6 to 10 years of hands-on experience in high-speed digital IP design, particularly for SERDES or similar interfaces. Expertise in microarchitecture, RTL coding (Verilog), and debugging complex digital designs. Proficiency with industry-standard EDA tools and design flows for digital implementation and verification. Strong scripting skills in Tcl, Perl, or Python for flow automation and process enhancement. In-depth understanding of timing analysis, clock domain crossing, and interface protocols. Who You Are: Analytical thinker with excellent problem-solving and debugging skills. Proactive, self-motivated, and eager to take initiative in challenging situations. Exceptional communicator who thrives in a collaborative, cross-functional team environment. Committed to continuous learning, embracing new tools, techniques, and industry trends. Adaptable, resilient, and able to manage multiple priorities in a fast-paced setting. Values diversity, inclusion, and a culture of mutual respect. The Team You’ll Be A Part Of: You will join a world-class team of digital and mixed-signal engineers focused on developing high-speed SERDES IP, a cornerstone of the Synopsys DesignWare portfolio. Our team values innovation, collaboration, and technical excellence. We work closely with specialists across analog, verification, validation, and customer support to deliver robust, scalable IP solutions that meet the highest standards of quality and performance. You’ll have the opportunity to collaborate with experts in the field, contribute to groundbreaking projects, and help shape the future of silicon technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an accomplished analog IC design engineer with a proven track record of delivering high-performance, high-speed circuits in advanced technology nodes. With over a decade of hands-on experience, you possess deep technical expertise in transistor-level circuit design, particularly in FinFET and cutting-edge process nodes. You thrive in fast-paced, collaborative environments and enjoy working on challenging projects that push the boundaries of what’s possible in analog and mixed-signal design. Your passion for innovation is matched by a meticulous attention to detail and a strong commitment to quality. You are comfortable navigating complex SerDes architectures, from initial concept through to silicon validation, and you approach problem-solving with creativity and a data-driven mindset. You value teamwork and diversity, and you communicate your ideas clearly to colleagues from a variety of backgrounds, including digital designers, CAD engineers, and customers. What You’ll Be Doing: * Review and interpret SerDes standards to develop innovative transceiver architectures and detailed sub-block specifications. Investigate, propose, and design novel circuit architectures that overcome performance bottlenecks, achieving significant improvements in power, area, and speed. Collaborate with cross-functional teams to streamline design and verification methodologies, ensuring efficiency and design quality. Oversee physical layout processes, minimizing the impact of parasitics, device stress, and process variation for optimal silicon performance. Present and review simulation results within the team and externally at industry panels or customer reviews, articulating complex technical concepts clearly. Document design features, methodologies, and test plans to ensure knowledge transfer and reproducibility. Consult on electrical characterization of SerDes IP, analyze customer silicon data, and propose solutions for post-silicon enhancements. The Impact You Will Have: * Drive innovation in high-speed analog and mixed-signal design, directly contributing to Synopsys’ leadership in SERDES IP. Enable customers to achieve cutting-edge performance, power, and area metrics in their next-generation silicon products. Advance the adoption of the latest FinFET and gate-all-around technologies through robust, reliable analog solutions. Raise the bar for design quality and efficiency by introducing best practices in architecture, verification, and layout. Mentor and inspire a diverse team of engineers, fostering a culture of learning and continuous improvement. Strengthen Synopsys’ reputation by representing the company at industry events and delivering high-impact technical presentations. What You’ll Need: MTech/MS (4+ years) or BTech/BS (5+ years) in Electrical Engineering, Computer Engineering, or related field. Extensive analog IC design experience, especially with FinFET technologies and advanced process nodes. Expertise in transistor-level CMOS design, including successful CMOS tape-outs. Deep understanding of high-speed designs (Multi-Gbps), especially PAM4 SerDes architectures and sub-circuits (TX, RX, equalizers, PLL, DLL, regulators, oscillators, ADC/DAC). Proficiency with analog/digital interaction techniques for circuit optimization, calibration, and adaptation. Familiarity with ESD, custom digital design, design for reliability, layout effects, and signal integrity issues. Hands-on experience with schematic entry, physical layout, design verification tools, and SPICE simulation. Knowledge of scripting languages (TCL, PERL, MATLAB) for simulation post-processing. Excellent communication and documentation skills. Who You Are: An analytical thinker with a passion for solving complex technical challenges. A collaborative team player who values input from diverse perspectives. An effective communicator, able to convey technical details to both experts and non-experts. Detail-oriented, organized, and committed to quality and continuous improvement. Adaptable to changing priorities and eager to learn new technologies. Proactive in mentoring and supporting the professional growth of others. The Team You’ll Be a Part Of: You’ll join a world-class analog and mixed-signal R&D team based in Hyderabad, focused on developing high-speed SERDES IP for the latest process technologies. Our team brings together experts in analog, digital, and CAD, fostering an environment of innovation, knowledge sharing, and technical excellence. We work closely with global teams and customers to deliver industry-leading solutions that shape the future of connectivity. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 7+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Education Requirements Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 9+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. How You Will Contribute: The SVT/PV Engineer will develop test strategies, automation script development, and execute test plans for Ciena’s Optical products, focusing on DCN Comms, Security, NBIs, Platforms testing and NMS. Key Responsibilities: Develop and automate test strategies for Telecom networks. Create and execute test plans using TCL/Python. Identify and automate test scenarios. Debug and resolve defects with design teams. Ensure compliance with industry standards (ITU-T, IETF, IEEE, ANSI). Must Have: Networking (L2/L3 Protocols), Security Protocols (RADIUS, TACACS+, SYSLOG, Certificate Management etc.), NBIs (NETCONF, gRPC, RESTCONF). Test Automation (TCL/Python) Defect Analysis & Debugging Telecom Network Testing Bachelor’s/Master’s in Electronics, Computer Science, or Optical Communications. 2+ years in Telecom System Testing. Experience in test planning, automation, and debugging. Impact Metrics Improved test efficiency & automation coverage Reduction in defect leakage & debugging time Compliance with test quality standards Nice-to-Have Skills: Exposure to Photonics/DWDM. Familiarity with Test Equipment & Performance Benchmarking. #LI-MP2 Not ready to apply? Join our Talent Community to get relevant job alerts straight to your inbox. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

Hi Tech Mahindra is currently hiring RTL Lead Engineer for Bangalore location. Exp:8+yrs Location: Bengaluru NP: 0-30days Here is the detailed JD: KEY RESPONSIBLITIES: Work closely with architecture, RTL, PD and power management teams for coming up with the chip low power intent and UPF. Work with architecture, RTL and PD team for chip level power estimation, analysis and optimization Work closely with CAD team to come up with new flows and methodologies in the power analyisis and low power domains. PREFERRED SKILLSET: 8+ years of professional experience in the industry in low power and power estimation domains. Hands on experience on industry standard tools especially PTPX, Power Artitst, VCLP and CLP. Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker If interested share cv to Preeti.Rajput@TechMahindra.com

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 7+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Education Requirements Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 9+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

The Physical Verification Engineer position requires a minimum of 5 years of experience in the field. You will be based in Bangalore (BLR) and the employment type is full-time. The notice period for this role is immediate to 30 days. To excel in this role, you must possess skills in Physical Verification, TCL, AWK, Python Scripting, have previous experience with ADI Flows, expertise in Power Domain based Designs, and familiarity with tools like Calibre, Innovus, and Voltus. If you find yourself suitable for this role and meet the mentioned criteria, we encourage you to express your interest by sharing your resume to the email address sushma.vunnam@modernchipsolutions.com.,

You will be joining Qualcomm's cutting-edge hardware engineering team to drive the design verification of next-generation SoCs, with a focus on wireless technologies including WLAN (IEEE 802.11). Your role will involve working on IP and subsystem-level verification, collaborating with cross-functional teams to deliver high-performance, low-power silicon solutions. It is essential to have a strong understanding of on-chip buses and bridges to ensure seamless integration and performance across subsystems. Your key responsibilities will include developing and executing verification plans for complex SoC designs and IP blocks, architecting and implementing testbenches using SystemVerilog and UVM/OVM methodologies, performing RTL verification, simulation, and debugging, collaborating with design, architecture, and software teams to ensure functional correctness, contributing to IP design reviews and sign-off processes, supporting post-silicon validation and bring-up activities, analyzing and verifying interconnects, buses (e.g., AMBA AXI/AHB/APB), and bridges for performance and protocol compliance, conducting CPU subsystem verification including coherency, cache behavior, and interrupt handling, performing power-aware verification using UPF/CPF, and validating low-power design intent, as well as executing performance verification to ensure bandwidth, latency, and throughput targets are met. Preferred skills and experience for this role include having 2-15 years of experience in digital design and verification, a deep understanding of bus protocols and bridge logic with hands-on experience in AXI, AHB, and APB, experience with CPU subsystem verification and performance modeling, familiarity with wireless protocols (IEEE 802.11 a/b/g/n/ac/ax/be), proficiency in SystemVerilog, UVM/OVM, Verilog, and scripting languages (Perl, Tcl, Python), experience with power-aware verification methodologies and tools (e.g., UPF, CPF), familiarity with performance verification techniques and metrics, exposure to tools like Clearcase/Perforce and simulation/debug environments, and possessing strong analytical, debugging, and communication skills. To qualify for this position, you must hold a Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Science, or a related field, along with relevant experience in hardware design and verification.,

As an AMS Circuit Design Engineer at ACL Digital in Hyderabad, you will be responsible for designing Analog and SERDES IP circuits. You should hold a B.Tech or M.Tech in Electronics and Electrical Engineering from a reputable institute and have 2 to 8 years of relevant experience in Analog IPs like GPIO, RCOMP, ADC, DAC, LDO, PLL, Thermal Sensor, Voltage Monitor, Process Monitor, and their blocks, as well as SERDES IPs including DLL, PLL, Clocking path Analysis, SERDES System Design and Analysis, Power Delivery Analysis, Transmitter, Receiver, Channel Analysis, and more. In this role, you will need to have knowledge of SERDES protocols such as DDR IO, UCIe, PCIe, HBMIO, HDMI, MIPI, CDPHY, and others. Proficiency in design tools like Cadence Virtuoso, Spectre/HSpice Simulators, High-Speed Simulator APS/XA, and Waveform viewer is essential. Additionally, expertise in .lib generation and scripting languages like PERL, TCL, Python, SKILL will be preferred. Your communication skills should be excellent, and you should be a team player with a problem-solving approach. Reporting blocking issues during the project as needed will also be part of your responsibilities. By joining ACL Digital, you will be at the forefront of digital engineering and transformation, leveraging AI and data-driven solutions from Chip to cloud. Be prepared to navigate the complexities of digital transformation and shape the future with us.,

As an Implementation Engineer at Kinara, a Bay Area-based venture backed company, you will play a crucial role in leading and executing Synthesis and Static Timing Analysis (STA) for complex AI System on Chip (SOC) designs with multi-mode and multi-power domain architecture. Your primary responsibility will be to ensure the quality and reliability of our products by optimizing designs for low power consumption and high performance, while maintaining logically equivalent RTL. You will also be involved in ECO (Engineering Change Order) implementation for both functional and timing closure, as well as working with multi-clock, multi-power domain designs and multi-mode timing constraints. To be successful in this role, you should have a Bachelor's or Master's degree in Electronics, Computer Science Engineering, or a related field, along with a minimum of 5 to 7 years of experience in Implementation flows/Synthesis and STA. Proficiency with tools such as Cadence, Synopsys, and Mentor, as well as experience with Verilog and VHDL, is essential. You should also have expertise in sign-off Static Timing Analysis, Logic equivalency checks, Static Low Power Checks (UPF/CPF/CLP), and Formal verification for RTL 2 gates and gates2gates. Additionally, your role will involve working on tasks such as DFT insertion, simulation, debugging, and collaborating with different functional teams like RTL Design, DFT, and Physical Design. Your deep understanding of physical design concepts and constraints, including floor-planning, placement, congestion, and setup/hold timing closure, will be critical in ensuring the success of our AI solutions. At Kinara, we promote an innovative work culture that encourages collaboration and continuous learning. You will have the opportunity to work alongside technology experts and mentors who will support you in tackling exciting challenges. We value diverse perspectives and shared responsibilities in our work environment, where every contribution is appreciated. If you are passionate about pushing the boundaries of AI technology and eager to make a significant impact in the field of edge AI, we invite you to share your story with us. Join our dynamic team at Kinara and be a part of revolutionizing what people and businesses can achieve with our game-changing AI solutions. We look forward to reviewing your application and welcoming you to our team. Make your mark at Kinara!,

As a Design for Testing (DFT) Engineer at Google, you will play a crucial role in developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your Bachelor's degree in Electrical or Electronics Engineering, along with 3 years of experience in DFT methodologies and proficiency in tools like Tessent, will be instrumental in shaping the next generation of hardware experiences. Your work will involve collaborating with Register-Transfer Level (RTL) and Physical Designer Engineers to optimize the testing process. Your responsibilities will include working on Subsystem level DFT scan and Memory Built-In Self Test (MBIST) architecture, incorporating multiple voltage and power domains. You will also be tasked with writing scripts to automate the DFT flow and developing tests for production in the Automatic Test Equipment (ATE) flow. Additionally, experience with Automatic Test Pattern Generation (ATPG), Low Power designs, Built-In Self Test (BIST), Joint Test Action Group (JTAG), and Internal Joint Test Action Group (IJTAG) tools will be beneficial in executing your role effectively. Your expertise in architecting and developing DFT flows and methodologies, along with strong scripting skills in Python and TCL, will be valuable assets in this role. By joining the Devices & Services team at Google, you will contribute to creating innovative technologies and hardware that enhance user experiences, aligning with Google's mission to organize the world's information and make it universally accessible and useful. If you are passionate about pushing boundaries and delivering unparalleled performance, efficiency, and integration in hardware design, this role offers a rewarding opportunity to shape the future of technology.,

As a Physical Design Engineer at Google, you will be an integral part of a team dedicated to developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your role will involve contributing to the innovation behind products that are beloved by millions worldwide, shaping the next generation of hardware experiences with a focus on performance, efficiency, and integration. In this position, you will collaborate with a diverse group of professionals including architects, verification specialists, power and performance experts, and physical design engineers to specify and deliver high-quality designs for next-generation data center accelerators. Your primary responsibility will be to work on ASICs that are designed to accelerate machine learning computation in data centers. You will be tasked with solving technical challenges using innovative micro-architecture and logical solutions, evaluating design options with considerations for complexity, performance, power efficiency, and area optimization. The Technical Infrastructure team at Google plays a crucial role in ensuring the seamless operation of the architecture that supports all online user activities. From maintaining data centers to developing cutting-edge Google platforms, our team is committed to making Google's diverse product portfolio a reality. We take pride in being the engineers behind our engineers and enjoy the process of deconstructing and reconstructing systems to enhance their performance. Our goal is to keep our networks operational and deliver the best possible user experience. Key Responsibilities: - Take ownership of one or more physical design partitions or the top level of the design. - Drive towards achieving timing closure and optimizing power consumption of the design. - Contribute to the development of design methodologies, libraries, and participate in code reviews. - Define physical design-related rule sets for functional design engineers, ensuring alignment with project objectives. If you are passionate about pushing boundaries and eager to work on cutting-edge projects that have a global impact, this role offers an exciting opportunity to be at the forefront of innovation in silicon design at Google.,

Location: Bangalore (On-Site) Company: The Community League (TCL) Type: Full-Time Experience: 1–3 years in sports management, sales, or sport operations About TCL The Community League (TCL) is a grassroots and amateur sports platform focused on delivering high-quality, community-driven leagues across football, racquet sports, and more. We bring together players, academies, venues, and brands through well-structured formats, consistent content, and a commitment to growing sport at the local level. Role Overview We are looking for a dynamic Sports Management Executive who can contribute to both sales and operations . The ideal candidate should be passionate about sports, organized, and comfortable working on-ground during events while also being confident in handling client communication, lead follow-ups, and team onboarding. You will support the execution of TCL leagues while also playing a role in building our network of teams, academies, and partners. Key Responsibilities 🏟️ Operations Support Assist in the execution of matchdays across all TCL sports formats (football, racquet sports, etc.) Coordinate with venues, referees, vendors, and officials for smooth matchday delivery. Maintain checklists, matchday reports, and operational trackers. Ensure matchday branding and logistics are in place. 🧾 Sales & Customer Onboarding Identify and follow up with leads (teams, academies, and institutions) to onboard them into TCL leagues. Conduct intro calls with potential teams, explain formats, registration process, and benefits. Track outreach and maintain a CRM/log of ongoing communication. 🎯 Team & Registration Coordination Share league details, fixtures, and rules with participating teams. Support with registration tracking, ID checks, and data entry. 🎥 Media Coordination Share schedules, results, and event info with the digital/content team in real-time. Support content collection (basic photography/video coordination) on matchdays. Skills & Qualifications Bachelor's degree in Sports Management, Business, Marketing, or related fields. 1–3 years of experience in sports/event operations or client-facing roles. Excellent communication and organizational skills. Comfortable working on weekends for live events (with compensatory offs). Familiar with basic tools: Excel/Google Sheets, Canva, WhatsApp Broadcast, and email handling. Passion for sports, especially grassroots and community-based initiatives. Preferred Prior experience working with teams, academies, or leagues. Basic understanding of sales funnels, CRM usage, and lead management. On-ground event experience in any sport. What You’ll Get Hands-on experience across sales and event operations in a fast-growing sports platform. Opportunities to grow into specialized roles based on performance and interest. Access to a passionate team and dynamic sporting environment. To Apply Send your CV and a short note about why you want to work in sports to febin@proictus.com Subject Line: Application – Sports Management Executive (TCL) Skills: organizational skills,crm usage,sports management,communication,excel,canva,lead management,operations,google sheets,team management,sales,sport operations

"We're improving the way we live and work by intelligently connecting energy systems, buildings, and industries!! Smart infrastructure from Siemens makes the world a more connected and caring place – where resources are valued, where impact on the world is considered, where sustainable energy is delivered optimally and efficiently. It provides the flexible infrastructure to allow society to evolve and respond to changing conditions. Technology and the ingenuity of people come together to be at one with our environments and to care for our world. We do this from the macro to the micro level, from physical products, components, and systems to connected, cloud-based digital offerings and services. Siemens offers a broad portfolio of grid control and automation; low- and medium-voltage power distribution, switching and control; and building automation, fire safety and security, HVAC control and energy solutions. JOIN US! WE MAKE REAL WHAT MATTERS. THIS IS YOUR ROLE" Experience in Protection relay / distribution automation product validation and troubleshooting of the system concepts. Proficiency with the test case design using Power system simulators such as Omicron/ OCC scripting / TMW TCL scripts/ Python scripts. Basic knowledge and understanding of network communication protocols including Modbus, DNP3, IEC 60870-5-103, IEC61850 etc. Experienced in Product qualification/validation for embedded products and systems. Knowledge with software configuration management tools, defect tracking tools, and peer review. Proficiency in test automation concepts using Control center framework or Selenium/Robot frameworks. Adequate knowledge in understanding voltage disturbances, power system reliability, grounding system, power system tolerances Strong documentation and writing skills. This role is based in Goa, where you’ll get the chance to work with teams impacting entire cities, countries – and the shape of things to come. "WE DON'T NEED SUPERHEROES, JUST SUPER MINDS! WE’VE GOT QUITE A LOT TO OFFER. HOW ABOUT YOU? We’re Siemens. A collection of over 379,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality and we welcome applications that reflect the diversity of the communities we work in across Gender, LGBTQ+, Abilities & Ethnicity. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and imagination, and help us shape tomorrow Find out more about Smart Infrastructure at: https://new.siemens.com/global/en/company/topic-areas/smart-infrastructure.html and about Siemens careers at: www.siemens.com/careers"

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: MTS SILICON DESIGN ENGINEER As a member of the AECG Product Validation and Solutions Team within AMD you will develop and enable the next generation of PCIe technologies to power datacenter, acceleration, AI and communications markets. High speed PCIe connectivity is critical for modern technology and infrastructure that helps improve our lives. THE ROLE: At AMD you will help create leading edge PCIe technologies used in a wide variety of applications. The focus of this role is to design, plan and execute RTL design for new and existing PCIe technology and solutions for programmable silicon at AMD. Key development includes PCIe technologies for PCIe Gen 6, CXL, TDISP, IDE, PCIe in-line DMA and other leading edge products. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. You should also have a desire to expand existing skill sets and take on new challenges. KEY RESPONSIBILITIES: Develop and productize next generation PCIe, CXL and connectivity solutions to power datacenter, acceleration, AI and communications markets Participate in technical role in all phases of the product development cycle from new product exploration, architecture through implementation, prototyping, validation, productization and support including but not limited to architecture, design, and documentation for IPs Develop comprehensive testing plans including Compliance and Interop testing. Critically review and provide feedback on the Design Implementations and Verification plans Pre-Silicon and Post Silicon validation for new PCIe enabled blocks Responsible for IP design, Silicon bring up, Validation and IP release Work in collaboration with the Global teams PREFERRED EXPERIENCE: Strong knowledge in RTL coding, preferably with Verilog and SystemVerilog Proficient in RTL simulation tools (VCS, Modelsim) Knowledge of high-speed interfaces including, PCIe, CXL, NVMe, Ethernet, DDR3/4/5, LPDDR3/4, HBM, AMBA AXI/AHB/APB protocol Experience in using Lab equipment like PCIe Lecroy/Viavi Exerciser/Analyzer Experience in developing system or IP prototypes using FPGAs Strong knowledge of IP/SOC design methodologies Experience with scripting languages including Tcl, Perl, Python, Unix shells and Makefiles Knowledge of C/C++ is an added advantage ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering with 8+Yrs of exp #LI-SR4 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Dear Candidate, Greetings from Ojas Systems!! We have job opening with our client in Chennai for Enovia. Please find below the JD Associate / Lead, Enovia CAD Integration Job Description Summary • Participate in design workshops, involve in design discussions, provide technical inputs and help decision making • Analyze the business requirements and translate into IT requirements • Review user stories and provide IT specific details and address business questions • Execute systems integration test cases and identify issues, if any • Test the data flow and integration with existing PLM BOM/Chg mgmt. modules • Review technical design and code to address design issues / risks • Review the technical solutions with architects and make sure the solution fits to the business and IT needs • Develop IT test cases for the functional features testing • Champion Enovia PLM integration like CAD Integration, SAP Integration, etc. and its interplay with existing module like BOM Mgmt. and Change Mgmt. • Work with Project Manager(s) and business and provide required updates Job Description/Preferred Qualifications 3-5 years of working experience in developing and configuring solutions on Enovia 3DExperience platform Working experience on CAD Integrations with Enovia PLM, major CAD / PDM systems like Creo/ PDMLink, SolidWorks/EPDM, Inventor Vault, Solid Edge, etc. Working experience on Enovia CAD integration technologies like PowerBy, XPDM architectures and related Working experience of 3DExperience Enovia data model (Classic and UPS) Working experience in UPS data model & 3D Visualization and related 3DExperience apps like Product Structure, 3D Visualization, 3D Issue & Markups, 3D Play, etc. Experience in CAD data migrations is a plus Working experience in Web-services based integration architecture Experience in MQL scripts and TCL programming, JPOs, 3D Experience web and widget development Experience - 5-11years Thanks & Regards Meghana

Job Description: Project Executive – Smart Lighting & Data Analytics Location: Ahmedabad Employment Type: Full-time Company: Acon Innovations Website: https://www.aconinnovations.com About Acon Innovations At Acon Innovations, we are redefining the way people experience light. With a core focus on design, innovation, and sustainable technology, we offer customized lighting and automation solutions across commercial, residential, and industrial sectors. Backed by engineering expertise and a deep understanding of space and function, we transform environments with smart, energy-efficient, and aesthetically driven lighting systems. Position Summary Acon Innovations is seeking a technically adept and proactive Project Executive with experience in smart lighting systems, data analysis, and urban IT infrastructure. This individual will be responsible for overseeing lighting design layouts, system analytics, and cross-functional project execution related to smart city and media façade lighting projects. Key Responsibilities · Manage operations and maintenance of large-scale smart street lighting systems (including coordination with O&M teams, AMC, and vendors). · Handle data analytics and system reports from lighting control platforms (e.g., Tata Communications, CCMS, LED Player). · Oversee smart infrastructure projects including ITMS, AFCS, and E-Governance modules. · Work on lighting design layouts using AutoCAD and DiaLUX, and create media façade lighting sequences. · Support pilot projects and deployments in cities like Ahmedabad, Silvassa, Calicut, and Faridabad. · Coordinate with government bodies, consultants, and vendors (e.g., TCL, NEC, PWC, JIO). · Generate daily/monthly analytics reports and system health dashboards for internal and external stakeholders. · Lead documentation, approvals, and feedback integration processes for project delivery. · Collaborate with cross-functional teams to ensure quality, timeliness, and efficiency of smart solutions. Qualifications & Skills · Bachelor’s Degree in Information Technology, Electronics, Electrical Engineering or a related field. · 6months to 2 years of experience in smart city solutions, preferably in lighting, transportation systems, or IoT platforms. · Proficiency in MS Office, AutoCAD, DiaLUX (optional), and data visualization/reporting tools. · Exposure to software for lighting control like LED Player or similar (Optional). · Excellent communication and coordination skills with ability to manage multiple stakeholders. · Strong analytical thinking, problem-solving, and documentation skills. Preferred Experience · Experience working with municipal corporations and large city-wide infrastructure projects. · Familiarity with SCADA, City Wi-Fi, E-Challan, VMS, and SWM systems. · Hands-on with media façade lighting and dynamic content programming. What We Offer · A structured and collaborative work environment. · Opportunity to work with a design-led and innovation-driven company. · Exposure to cutting-edge smart infrastructure projects across India. · Competitive salary package. Ready to be a key part of our project execution team? Send your resume to kapil@aconinnovations.com Subject Line: Application – Project Executive – Smart Lighting

Alternate Job Titles: Senior R&D Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and driven engineering professional with a strong foundation in VLSI concepts, CMOS circuit design, and EDA tools. With2-3 years of hands-on experience in the semiconductor industry, you thrive in dynamic environments where innovation, collaboration, and continuous learning are valued. Your curiosity drives you to explore emerging technologies such as AI/ML, and you have developed proficiency in scripting languages like TCL and Python to solve complex engineering challenges. You have a keen eye for detail and a solid grasp of timing, power, and noise analysis, enabling you to deliver robust and reliable design solutions. Your exposure to industry-standard tools such as VCS, Design Compiler, Primetime, and HSPICE/Primesim has honed your technical expertise, and you are comfortable navigating various stages of the design flow, from synthesis to signoff. As a team player, you communicate effectively, share knowledge openly, and support your peers in achieving shared goals. You value diversity, equity, and inclusion, and are eager to contribute to a culture that fosters creativity and personal growth. If you are ready to challenge yourself, make an impact, and be part of a world-class engineering team, Synopsys is the place for you. What You’ll Be Doing: Developing and maintaining scripts and automation flows using TCL, Python, and Make to streamline EDA tool operations and design processes. Performing advanced timing, power, and noise analysis on CMOS circuits, leveraging your understanding of setup/hold constraints and leakage concepts. Contributing to the characterization of standard cell libraries, including NLDM/CCSN and LVF methodologies, and ensuring accurate modeling for signoff. Collaborating with design, verification, and methodology teams to optimize PPA (Power, Performance, Area) and address STA (Static Timing Analysis) challenges. Utilizing tools such as VCS, Design Compiler, Primetime, and HSPICE/Primesim to support verification, synthesis, and signoff activities. Participating in root cause analysis of timing and power issues, implementing innovative solutions, and documenting best practices for future projects. Staying abreast of the latest trends in AI/ML and exploring their application in EDA tool flows and design optimization. The Impact You Will Have: Accelerate the delivery and quality of Synopsys' IP and design solutions through automation and process innovation. Enhance product reliability by ensuring precise timing and power characterization, directly influencing customer satisfaction. Drive cross-functional collaboration, sharing insights and solutions that elevate team performance and project outcomes. Contribute to the adoption of cutting-edge AI/ML techniques, positioning Synopsys as a leader in intelligent EDA workflows. Reduce design cycle times and resource bottlenecks through effective scripting and workflow optimization. Mentor and support junior engineers, fostering a culture of knowledge sharing and continuous improvement. What You’ll Need: 2-3 years of experience in VLSI design, EDA tool flows, or related semiconductor engineering roles. Proficiency in TCL, Python, and Make for scripting and automation. Strong understanding of CMOS circuit fundamentals, including timing (setup/hold), power (leakage/dynamic), and noise analysis. Experience with cell library characterization methodologies (NLDM/CCSN, LVF) and familiarity with library constructs and syntax. Working knowledge of STA analysis, PPA trends, and basic understanding of PNR (Place & Route). Hands-on experience with EDA tools: VCS, Design Compiler, Primetime, HSPICE/Primesim. Who You Are: Analytical thinker with strong problem-solving skills and a passion for innovation. Effective communicator, able to collaborate across disciplines and share complex ideas clearly. Self-motivated and adaptable, eager to learn new technologies and methods. Detail-oriented with a commitment to delivering high-quality results under tight deadlines. Team player who values diversity, equity, and inclusion in the workplace. The Team You’ll Be A Part Of: You will join a vibrant team of R&D engineers focused on advancing the state of the art in chip characterization, timing, and power analysis. Our team collaborates closely with cross-functional partners in design, verification, and methodology to deliver next-generation semiconductor solutions. We foster a culture of innovation, mentorship, and continuous improvement, ensuring every member has an opportunity to grow and make a meaningful impact. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Position: Associate / Lead – Enovia CAD Integration Job ID: 27376 Location: Chennai, India Domain: Electronics & Electrical Work Shift: Swing Shift (2 PM – 11 PM IST) Job Type: Hybrid (2–3 days in-office per week) Experience: 5 – 8 Years Compensation: ₹14 – ₹21 LPA (Fixed) Max CTC: ₹28 LPA Key Responsibilities Participate in design workshops and technical discussions, providing expert input and guidance. Analyze business requirements and translate them into actionable IT specifications. Review user stories, clarify requirements, and respond to technical/business queries. Execute systems integration test cases and troubleshoot integration issues. Validate data flows and ensure seamless integration with PLM modules such as BOM and Change Management. Review and improve technical designs and code to mitigate risks or design challenges. Collaborate with architects to align technical solutions with business needs. Develop and execute IT test cases for functional and regression testing. Lead efforts in integrating Enovia PLM with CAD systems, ERP (e.g., SAP), and other enterprise modules. Coordinate with project managers and cross-functional teams to provide timely updates. Required Qualifications Bachelor’s degree with a minimum of 5 years of relevant experience, OR Master’s degree with 3+ years of experience, OR Doctorate with 0+ years of experience. 3–5 years of hands-on experience in developing and configuring solutions on the Enovia 3DExperience platform. Strong experience with CAD integrations including X-CAD and XPDM architecture. Deep understanding of the Unified Product Structure (UPS) data model. Proficiency in Enovia development, including JPOs, JSPs, MQL, TCL scripting, and web/widget development. Experience with 3DExperience OOTB applications such as Product Structure, 3DPlay, 3D Visualization, and 3D Issue & Markups. Familiarity with web-services-based integration architecture. Exposure to databases such as Oracle and working knowledge of SQL. Preferred Qualifications Experience in CAD data migration. Knowledge of major CAD/PDM systems such as Creo/Windchill, SolidWorks/EPDM, Inventor Vault, and Solid Edge. Functional experience in Enovia configuration beyond installation/support. Strong communication and documentation skills. Problem-solving mindset with solid analytical abilities. Skills: 3d issue & markups,3dexperience ootb applications,tcl scripting,unified product structure (ups),cad,cad integration,jsps,web-services-based integration architecture,integration,sql,enovia 3dexperience,oracle,product structure,3d,design,x-cad,3dplay,3d visualization,architecture,xpdm,test cases,jpos,mql,web/widget development

As a global technology leader in Electronic Design Automation software, Siemens EDA enables companies worldwide to develop innovative electronic products efficiently. The software tools provided by Siemens EDA support customers in pushing the boundaries of technology and physics to deliver superior products in the realm of chip, board, and system design. Within Siemens EDA, the Aprisa offering encompasses comprehensive functionality for top-level hierarchical design and block-level implementation for intricate digital IC designs. The architecture of Aprisa, with a focus on detail-route-centric and hierarchical database, facilitates swift design closure and ensures optimal quality results within a competitive runtime. This particular role is based in Bangalore, offering opportunities to travel to various locations within India and globally. Flexibility and willingness to adapt to different work environments are essential. In return, you will have the chance to collaborate with teams that have a significant impact on entire cities, countries, and the future landscape. In this position, you will lead a team of engineers dedicated to addressing the latest design challenges in Logic Synthesis. Your responsibilities will include collaborating with Research and Development teams to drive the roadmap for the next generation RTL2GDSII solution. Working closely with the design community, you will tackle critical design problems to achieve desired performance, area, and power targets. Additionally, you will be involved in deploying Synthesis solutions with customers engaged in cutting-edge technologies, including 7nm and beyond. Providing training and technical support to customers utilizing Siemens EDA tools will also be part of your role. The ideal candidate for this position would have a minimum of 10+ years of experience in Logic Synthesis flows, along with proficiency in Verilog, System Verilog, and VHDL. A strong understanding of RTL2GDSII flow, digital design, and implementation fundamentals is essential. Previous experience in IC digital design flows and familiarity with front-end EDAT tools, such as Synthesis, DFT, Formal Verification, and Logic Equivalence Checks, is required. Hands-on experience with commercial synthesis tools like Synopsys-DC/FC and Cadence-Genus is a must, as well as exposure to advanced technology nodes of 7nm and below. Proficiency in scripting languages like TCL, Perl, or Python would be advantageous. The ideal candidate should be a self-motivated team player with a drive for high team performance, possessing strong problem-solving and debugging skills, as well as excellent verbal and written communication abilities. At Siemens, we are a diverse community of over 377,000 individuals shaping the future across more than 200 countries. We are committed to equality and welcome applications that reflect the diversity of the communities we serve. Employment decisions at Siemens are based on qualifications, merit, and business requirements. Join us with your curiosity and creativity as we work together to shape tomorrow.,

Job Title : STA Engineer Experience : 3- 5 Years Location : Noida Immediate Joiners Preferred About the Role : Incise Infotech Limited is expanding its VLSI Design team and is looking for skilled Static Timing Analysis (STA) Engineers to contribute to high-performance chip design projects. This role is ideal for engineers passionate about full-chip timing closure, constraint development, and timing verification in advanced technology nodes. Key Responsibilities Perform Static Timing Analysis at both block and full-chip levels using industry-standard tools such as PrimeTime or Tempus Analyze and debug setup, hold, transition, and other timing violations Work closely with RTL, Synthesis, and Physical Design (PD) teams to drive timing closure Develop, validate, and manage SDC constraints for various design stages Ensure timing sign-off readiness by generating and reviewing timing reports Innovate and automate STA flows for improving efficiency and quality of results Collaborate with design teams to support tape-out schedules and quality metrics Perform PPA (Power, Performance, Area) analysis and support ECO timing closure Support multiple projects by providing STA inputs during design reviews Required Skillsets Hands-on experience in STA tools like PrimeTime, Tempus, etc. Strong understanding of timing concepts, clock domains, and signal integrity Expertise in writing and debugging SDC constraints Solid knowledge of CMOS, VLSI design flows, and timing closure methodologies Proficient in TCL scripting and automation of STA reports and flows Familiarity with synthesis, floorplanning, and physical design interactions Experience with advanced technology nodes (e.g., 7nm, 16nm, 28nm) is a plus Good communication and problem-solving skills Ability to work independently and collaboratively in a fast-paced environment (ref:hirist.tech)

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER As a member of the AECG Product Validation and Solutions Team within AMD you will develop and enable the next generation of PCIe technologies to power datacenter, acceleration, AI and communications markets. High speed PCIe connectivity is critical for modern technology and infrastructure that helps improve our lives. The Role At AMD you will help create leading edge PCIe technologies used in a wide variety of applications. The focus of this role is to design, plan and execute RTL design for new and existing PCIe technology and solutions for programmable silicon at AMD. Key development includes PCIe technologies for PCIe Gen 6, CXL, TDISP, IDE, PCIe in-line DMA and other leading edge products. The Person You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. You should also have a desire to expand existing skill sets and take on new challenges. Key Responsibilities Develop and productize next generation PCIe, CXL and connectivity solutions to power datacenter, acceleration, AI and communications markets Participate in technical role in all phases of the product development cycle from new product exploration, architecture through implementation, prototyping, validation, productization and support including but not limited to architecture, design, and documentation for IPs Develop comprehensive testing plans including Compliance and Interop testing. Critically review and provide feedback on the Design Implementations and Verification plans Pre-Silicon and Post Silicon validation for new PCIe enabled blocks Responsible for IP design, Silicon bring up, Validation and IP release Work in collaboration with the Global teams Preferred Experience Strong knowledge in RTL coding, preferably with Verilog and SystemVerilog Proficient in RTL simulation tools (VCS, Modelsim) Knowledge of high-speed interfaces including, PCIe, CXL, NVMe, Ethernet, DDR3/4/5, LPDDR3/4, HBM, AMBA AXI/AHB/APB protocol Experience in using Lab equipment like PCIe Lecroy/Viavi Exerciser/Analyzer Experience in developing system or IP prototypes using FPGAs Strong knowledge of IP/SOC design methodologies Experience with scripting languages including Tcl, Perl, Python, Unix shells and Makefiles Knowledge of C/C++ is an added advantage ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering with 8+Yrs of exp Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

As a member of our creative and versatile Physical Design team in Bangalore, India, you will play a crucial role in developing next-generation innovative networking chips in advanced process nodes. Your responsibilities will encompass driving the backend process across the entire RTL to GDS Implementation flow. This includes tasks such as hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification, and equivalence checks, all with a primary focus on performance and die size optimization. Your key responsibilities will involve implementing multi-hierarchy designs in 7nm/5nm/3nm TSMC technology, performing partitioning, pin assignment, and design assembly tasks, defining Physical and Timing Sign-Off conditions, collaborating closely with the RTL design team to grasp the design architecture, and leading the development of methodologies to enhance and automate physical design work. Additionally, you will be expected to tackle design and flow issues, propose solutions, and drive their execution effectively. The ideal candidate for this position is an ASIC engineer with over 6 years of relevant work experience across various technologies. You should possess expertise in all facets of ASIC Physical implementation, including Floor planning, Clock and Power distribution, global signal planning, I/O planning, and hard IP integration. Your experience should also cover hierarchical design implementation, Timing closure, physical convergence, Power Integrity Analysis, and working on large designs utilizing cutting-edge sub 16/14/7nm technologies. Familiarity with Design for Yield and Manufacturability, as well as multi Vt strategies, will be beneficial for this role. Hands-on experience with specific tool sets is required, including Cadence Innovus & Synopsys ICC2 for Floor planning and P&R, Synopsys DC/DCG for Synthesis, Synopsys Formality and Cadence LEC for Formal Verification, Primetime-DMSA for Static Timing verification, Apache Redhawk for Power Integrity, and Synopsys ICV, Mentor Calibre for Physical Design Verification. Proficiency in scripting with TCL and Perl is a prerequisite, while knowledge of Python is considered a plus. A Bachelor's or Master's Degree in Electrical or Computer Engineering is a mandatory qualification for this position. At Cisco, where each individual brings a unique set of talents to the table, teamwork is essential to making a difference. The company's commitment to digital transformation, innovation, creativity, and inclusivity is evident in its culture. By fostering an environment that encourages learning, growth, and diversity of thought, Cisco empowers its employees to drive meaningful change and embrace new challenges. Join us at Cisco, where your individuality is celebrated, and your contributions are valued.,