Design Engineer II

Cadence

3 - 6 years

0 Lacs

Pune Maharashtra India

Posted:4 days ago| Platform:

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Skills Required

design cadence integration verification checks engineering flow verilog logic controller documentation synthesis timing constraints analysis development emulation communication

Work Mode

On-site

Job Type

Full Time

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Selected Candidate is responsible for RTL Design & Integration. Need to work closely with Architects and Verification team.Responsible to achieve required design quality by doing Lint and CDC checks and adhering to release checklists.

Skillset/ Requirements

BTech/ MTech in Engineering with 3 to 6 years of actual work experience in RTL Design.
The ideal candidate should have thorough understanding of end-to-end Digital design flow.
Verilog / System-Verilog RTL logic design, debug, and functional verification support.
Understanding of proper handling of multiple asynchronous clock domains and their crossings
Understanding of Lint checks and proper resolution of errors
Working experience on APB and AXI protocols.
Working experience on micro-controller based designs and its associated logic is a Strong plus.
Experience in Digital microarchitecture definition and documentation is a plus
Experience in synthesis timing constraints, static timing analysis and constraint development is a plus
Experience with FPGA and/or emulation platform is a plus.
Exhibit excellent communication skills and be self-motivated and well organized.

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