Standard Cell Layout Engineer

5 years

0 Lacs

Posted:1 month ago| Platform: Linkedin logo

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On-site

Job Type

Full Time

Job Description

We are looking for a skilled Standard Cell Layout Engineer with 3 – 5 Years of experience in standard cell, Analog, mixed-signal, and custom digital block layout design using advanced CMOS technologies . The candidate should have strong hands-on experience with Cadence Virtuoso for schematic and layout editing and be proficient in physical verification (DRC/LVS) using tools like Mentor Calibre Position: Standard Cell Layout Engineer Location: Phoenix Aquila, Hyderabad Joining Timeline: Immediate to 15 Days (strict) Key Responsibilities: Develop and optimize standard cell layouts. Perform physical verification and ensure DRC / LVS clean designs. Collaborate with circuit designers and CAD teams. Solve layout issues related to area, performance, and power. Mandatory Skills: Standard cell layout Cadence Virtuoso (Layout L / XL) Physical verification (Mentor Calibre) Knowledge of Electro-Migration, Latch-UP, Coupling, Crosstalk, IR – Drop, Parasitic Analysis, Matching, Shielding Good to Have: Skill coding / layout automation Experience in advanced nodes (e.g., 28nm and below) Strong problem-solving and communication skills Show more Show less

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