1063 Dft Jobs - Page 4

About The Company : Fischer Measurement Technologies (India) Pvt. Ltd. is an ISO 9001 Certified company and 100% subsidiary of Helmut Fischer Group, Germany. Founded in 1953, Helmut-Fischer is an innovative leader in supplying instruments and solutions for precise material analysis, coating thickness, material testing, micro hardness measurement. Helmut Fischer is active around the globe with 22 Fischer subsidiaries including India and 32 sales offices in all key industrialized countries. Fischer products stand for high quality standards and highest precision. Fischer is also leader in customer service and enjoy high customer loyalty. Fischer is a reliable and competent partner offering appropriate consultation, extensive service and practical-oriented training events. Fischer Measurement Technologies (India) Pvt. Ltd. was incorporated in India in April 2006 with its H.O at Pune and today FISCHER instruments are used successfully in the field of Automotive, Auto-Components, Electroplating, Powder Coating, Electronics, Electrical, Galvanizing, Jewellery, Hallmarking, Research & Development and various other industries. Fischer offers comprehensive range of products using X-ray fluorescence, beta backscatter, magnetic, magnetic induction, eddy current, electrical resistance or coulometric methods . Their highly dedicated team of sales, service and application engineers are available to offer optimum solution and support in line with customer requirements. The high-quality level of Helmut Fischer instruments is driven through the co-operation with demanding partners. Helmut Fischer instruments are used with great success in all the technical fields in industry and research. Fischer India offers its customers the global advantage of its parent company with local expertise. We are the most experienced leader in this field as we have more than 75 years of competency and knowledge built since our inception in 1953. To know more about Fischer products and solutions please visit www.helmut-fischer.com. Position Overview: We are seeking a dynamic and results-oriented Supplier Quality Engineer (SQE) that ensures the quality of products and services from suppliers by evaluating, monitoring, and improving supplier performance through audits, inspections, and collaboration, while also resolving quality issues and ensuring compliance with company and regulatory standards. Key Responsibilities: Conduct incoming inspections of machine parts as per engineering drawings and specifications and Inspection of Raw material forgings, bars, casting and bought out parts as per quality standards. Daily inspection activities, clearance of GRN and ensuring that, these are in line with the schedule; knowledge of SAP / ERP is a must. Review and understand control plans for various machining processes. Utilize a range of measuring instruments such as vernier callipers, micrometres, height gauges, thread gauges, profile projectors, surface roughness testers, and DFT testers to ensure accurate measurements and quality checks. Supplier rework, rejection handling, NCR management, daily report, etc. Apply knowledge of Kaizen, 5S, Poka-yoke, and other continuous improvement methods to ensure efficient and error-free operations. Ensure adherence to Geometric Dimensioning and Tolerancing (GD&T) standards in all inspections. Understand and work with CNC, VMC, conventional machines, grinding processes, and sheet metal works. Quality related problem solving, root cause analysis, etc. Support R&D for new product development quality & prototyping. Support R&D for Automation Project execution (Mechatronics background) Qualifications: Diploma / BE in Mechanical / Mechatronics Engineering. Minimum 2 years as Quality Engineer / Supplier Quality Engineer Preferred candidate profile Knowledge & hands-on experience on below – Reading specifications, technical drawings & documentations Good knowledge about defect analysis & Rejection booking time to time with proper analysis Good Knowledge of ISO 9001-2015, & Lean Manufacturing knowledge of Kaizen, 5S, Poka-yoke, and other continuous improvement methods to ensure efficient and error-free operations. SAP / ERP – Incoming Goods inspection & GRN QAP Documentation What We Offer: Competitive salary and performance-based incentives. Opportunities for professional growth and career advancement. Comprehensive training and development programs. Supportive and collaborative work environment.​ Application Process: Interested candidates are invited to submit their resume along with a cover letter detailing their relevant experience and why they are a good fit for this role.​ Apply Now: Please send in your resumes with covering letters on email id - hr@fischerindia.com Note: This document is an outline of the primary tasks assigned and is subject to revision by the company based on the needs and requirements of the job.

Alternate Job Titles: Senior Digital Design Engineer ASIC Design Engineer High-Speed SerDes Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced ASIC Digital Design Engineer with a strong background in digital design for high-speed serial interfaces. You have a deep understanding of USB, PCIe, Ethernet, Display, and HDMI protocol standards, and you thrive in a collaborative environment. Your expertise in Verilog RTL design, microarchitecture, and timing constraints development makes you a valuable asset to any team. You are adept at using tools like Spyglass for CDC/RDC/Lint and have excellent debugging skills. Your ability to propose and implement design updates based on various requirements, coupled with your experience in test coverage and physical design timing closure, sets you apart as a leader in your field. With a passion for innovation and a keen eye for detail, you are ready to take on new challenges and contribute to the success of Synopsys. What You’ll Be Doing: Driving and working on digital design for high-speed serial interface PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Proposing micro-architecture of design/design updates based on customer requirements, analog requirements, system performance improvements, Link layer interface changes, or overall robustness of design. Implementing RTL in Verilog and running Spyglass CDC/RDC/Lint. Collaborating with verification teams to test desired functionality and corner cases. Developing timing constraints, DFT insertion, and test coverage, and closing timing with physical design teams. Well versed in Micro-Architecture and Block Ownership, Design from scratch. The Impact You Will Have: Enhancing the performance and reliability of high-speed serial interface PHY IPs. Contributing to the development of cutting-edge technologies that power modern electronics. Driving innovation in digital design and influencing the future of semiconductor technology. Collaborating with cross-functional teams to deliver robust and high-quality designs. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous improvement and excellence. Supporting customers by providing high-performance and reliable IP solutions that meet their needs. What You’ll Need: 5-8 years of relevant experience in digital design for ASICs. Strong knowledge of Verilog RTL design and microarchitecture. Experience with timing constraints development and synthesis flow. Proficiency in using Spyglass or similar tools for Lint/CDC/RDC. Proficiency in scripting and automation using TCL, PERL, or Python. Excellent debugging skills and attention to detail. Who You Are: A collaborative team player with strong communication skills. A problem solver with a proactive approach to challenges. A detail-oriented professional with a passion for innovation. A self-motivated individual who thrives in a fast-paced environment. An adaptable engineer who can handle multiple tasks and priorities. The Team You’ll Be A Part Of: You will be part of the High-Speed SerDes Digital Design Team, a group of talented engineers dedicated to developing high-performance serial link PHY IPs. The team focuses on innovation, quality, and collaboration to deliver industry-leading solutions. Together, you will work on challenging projects that push the boundaries of technology and make a significant impact on the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Description: Hardware Engineer (PCB Design) Position: Hardware Engineer (PCB Design) Location: Employment Type: Full-Time Role Overview: We are seeking a skilled Hardware Engineer (PCB Design) to design, develop, and test high-performance circuit boards for embedded systems and electronic products. The ideal candidate should have expertise in schematic design, PCB layout, component selection, and signal integrity analysis. Key Responsibilities: Design and develop multi-layer PCB layouts using tools like Altium Designer, KiCad, or Cadence Allegro. Create and optimize schematics for electronic circuits. Perform signal integrity, power integrity, and thermal analysis for PCB designs. Select appropriate electronic components based on performance and cost criteria. Collaborate with firmware, mechanical, and production teams to ensure seamless integration. Conduct design validation, prototyping, and testing of PCB assemblies. Work with fabrication and assembly vendors to ensure DFM (Design for Manufacturing) and DFT (Design for Testing) compliance. Debug and troubleshoot hardware issues using oscilloscopes, logic analyzers, and other test equipment. Qualifications & Skills: Bachelors or Masters degree in Electrical/Electronics Engineering or a related field. 2+ years of experience in PCB design for embedded systems or industrial applications. Proficiency in ECAD tools such as Altium Designer, OrCAD, or Eagle. Strong understanding of high-speed PCB design, EMI/EMC compliance, and power distribution networks. Experience with analog, digital, and mixed-signal circuit design. Knowledge of IPC standards and PCB fabrication processes. Experience in working with communication protocols (SPI, I2C, UART, CAN, etc.). Strong problem-solving skills and ability to work in a collaborative environment. Preferred Skills: Experience with RF PCB design and impedance matching. Knowledge of IoT, wireless communication modules, or power electronics. Familiarity with automated testing and scripting for hardware validation.

About Marut Drones Marut Drones is India's leading Industrial Drone Manufacturer based in Hyderabad. Known for our powerful and innovative drones, we have developed popular models like Agricopter for precision agriculture, Hepicopter for long-range deliveries, Seed copter for afforestation, and Marut ZAP for mosquito eradication and disease prediction. Marut Drones has been recognized with numerous prestigious awards for its innovation and contributions to various sectors. These accolades include the FICCI Award for Sustainable Agriculture , the Telangana State Industries Award 2022 for Best Startup , the NASSCOM Emerging Technology Award for Drones and AI , and the South India Business Award . These awards highlight the company's commitment to excellence, sustainability, and its transformative impact across industries. Role Overview The VP - R&D will lead the end-to-end product R&D and Engineering functions at Marut Drones, with a core focus on ensuring reliable, robust, and scalable hardware and integrated systems. This leader will own the full technology roadmap across hardware, embedded systems, and supporting software layers, driving innovations that translate into world-class, field-validated drone systems. Key Responsibilities Leadership & Strategy: Lead the R&D/Engineering team to innovate and design products that align with the company’s vision for the UAV/UGV industry. Develop and execute the R&D roadmap, ensuring the timely delivery of projects in line with company objectives. System Architecture Leadership: Lead system-level architecture decisions across avionics, propulsion, flight control, power systems, and software stacks. Ensure platform modularity and scalability for future variants, payloads, and mission profiles. Architect robust battery systems — including smart BMS integration, power distribution, and thermal management — ensuring performance across diverse flight profiles. Drive innovations in energy efficiency, fast charging, and redundant power backup systems for critical operations. Product Reliability & Field Validation: Drive design-for-reliability (DFR), environmental testing, and field validation frameworks. Implement hardware-in-the-loop (HIL) testing and performance monitoring under real-world conditions. Champion robust component selection, mechanical durability, and EMI/EMC compliance. Build feedback loops from field failures into design improvements. Establish quality gates and failure analysis processes for drone and payload systems. Define validation protocols for battery safety, cycle life, thermal stability, and fail-safe behavior under different environmental and payload conditions. Lead decisions on battery chemistry, cell quality, BMS tuning, and charging infrastructure for enhanced mission reliability. Reliability Engineering & Design Validation: Build reliability engineering functions: HALT, HASS, MTBF analysis, FMEA, fault injection, and environmental validation. Define lifetime targets for components and systems and lead accelerated life testing. Implement a “design for serviceability” mindset, minimizing field repair complexity. Technology & Innovation Pipeline: Define and maintain a 2–3 year technology roadmap for sensors, navigation, autonomy, and AI/ML-driven analytics. Create IP and innovation culture — patents, trade secrets, new technologies (e.g., swarming, edge AI, autonomy in GPS-denied environments). Manufacturability &Production Handoff: Collaborate closely with Production and QA for DGM( Design for Manufacturability) DFA and DFT practices. Ensure engineering owns the BOM cost vs. reliability trade off. Team Management & Development: Manage, mentor, and grow a high-performing engineering team by fostering a culture of collaboration and innovation. Set clear performance goals for team members and provide regular feedback on progress and development. Project Management: Ensure timely delivery of R&D projects within scope, budget, and quality standards. Utilize agile methodologies and project management tools to oversee multiple projects concurrently. Handle the coordination of resources, prioritization, and risk management across all ongoing R&D projects. Regulatory & Safety Ownership: Lead the interface with DGCA, MoD, global standards like ASTM, FCC/CE, MIL-STD, and EASA-type certifications. Champion internal compliance frameworks for functional safety, RF emissions, flight logs, and telemetry retention. This role will be pivotal in driving technological advancements at Marut Drones, ensuring that our products remain at the cutting edge. The Head of R&D/Engineering will have a strong blend 1leadership, technical expertise, and strategic thinking to shape the future of agricultural drones. Requirements Proven track record in delivering hardware products with >95% field uptime. Deep understanding of rugged electronics design, thermal & power management, and real-time systems. Exposure to IEC/ISO/DO standards for product safety, environmental compliance, and flight certifications. Exposure to materials, fabrication and moulding processes. Experience in battery pack design, BMS integration, and flight endurance optimization. Exposure to safety standards like UN38.3, IEC 62133, and BIS certification for Li-ion systems. Industry exposure to UAV or automotive is preferred

PCB Designer – Hardware Design & Layout Engineer Job Description: We are seeking a detail-oriented and experienced PCB Designer to join our hardware engineering team. The ideal candidate will be responsible for designing high-quality, reliable, and manufacturable printed circuit boards (PCBs) for our electronic products, including Android-based devices and embedded systems. Key Responsibilities: Design multi-layer PCBs from schematic to final layout using industry-standard tools (Altium, KiCad, Eagle, etc.). Collaborate with hardware engineers to translate electrical schematics into optimized PCB layouts. Ensure signal integrity, EMI/EMC compliance, and adherence to DFM/DFT guidelines. Generate manufacturing files (Gerber, BOM, Pick & Place) and coordinate with fabrication and assembly vendors. Review and revise PCB designs based on testing feedback and electrical performance. Preferred Skills & Experience: 2+ years of experience in PCB design. Proficiency in PCB design software (Altium Designer, KiCad, Eagle, or similar). Experience with high-speed routing, impedance control, and multilayer board design. Understanding of electronic components, schematics, and embedded hardware design. Knowledge of industry standards (IPC, RoHS) and best practices in board layout. Nice to Have: Experience with Android device hardware, power optimization, or RF modules. Basic knowledge of firmware/hardware interaction and debugging tools. Job Type: Full-time Pay: ₹20,000.00 - ₹25,000.00 per month Schedule: Day shift Work Location: In person

Requisition ID: 99871-0 CAD Engineer 2 Duties of Position: (Include specific duties and responsibilities)  Requires a broad knowledge of PCB Layout Engineering practices, manufacturing process and IPC standards  Should be responsible to adhere the DFM/DFA and DFT process and preparing the files for PCB Fabrication and Assembly  Execute the High speed Design boards and support team members to develop skill sets for Sanmina Design specifications.  Should interact with SI and PI team.  Design consideration for EMI/EMC, thermal and Mechanical performance enhancement  Design the complex and multi-Layer PCB Board using Cadence Allegro Tool.  Technical expertise to handle project independently  Design consideration for EMI/EMC, thermal and Mechanical performance enhancement  Excellent Team player who interact with other Team Members and Supervisors  Experience In Skill Development, Design Automation Are Preferred  Experience in Library database management is preferred.  Experience In EDA Tool Automation Is Preferred. Qualifications Required: (Education, experience, skills, etc. Please be specific)  BE/B.Tech in Electronics, Electronics and Communication , Electrical and Electronics Engineering  Minimum of 5 years of experience in PCB Layout development experience in computer, Server, Storage PCBAs or related fields.  Technical expertise in High Speed Digital , Analog and Power Supply designs  Experience in board layout for x86 based Computing, Server and Storage Application domain.  Experience in Intel designs especially Sandy bridge and Server platform designs.  Familiarity in High End Processor based Mother Board Design, DDRx memory interfaces, Ethernet interfaces  Familiarity with Signal Integrity concepts and its implementation  Strong knowledge in EDA Tool (Cadence Allegro). Knowledge in other EDA tools like Mentor Graphics and Altium is added advantage.  Expertise in DFx concepts and its implementation. Familiarity with Valor/CAM350 or DFM/DFA tool is preferred  The Candidate should have experience in successful participation in development projects from design to production.  Should be proficient with office productivity tools including Microsoft Office.  Candidate should have basic knowledge of project management methods, and strong verbal and written communication skills.  Solid understanding of manufacturing pcb assembly flows.  Experience In EDA Tool Automation Is Preferred.  Must be detail oriented and have a proven ability to organize, analyze, set priorities, and multi task in a fast paced environment  Must be self-disciplined, highly productive and work effectively in team. Apply Back to results

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ AECG ASIC DFx - SENIOR SILICON DESIGN ENGINEER The Role AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. The Person You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS Work with multi-functional teams and handling schedules The successful candidate may also be responsible of: Debugging and verifying block-/chip-level DFT/DFX features Porting or creating the DFT/DFX verification environment Block/Chip test plan creation and development Stimulus writing and debug, and regression clean-up Generating high quality manufacturing test patterns for stuck-at, transition fault models and using on-chip test compression techniques Stimulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Provide technical support to other teams Preferred Experience Minimum 5 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus. Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Strong problem-solving skills. Team player with strong communication skills. Academic Credentials Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

The ideal candidate for this role should possess a Bachelor's or Master's degree or equivalent practical experience along with a minimum of 5 years of experience in Design for Testability/Design for Debugging (DFT/DFD) flows and methodologies. They should have a proven track record in developing DFT specifications and DFT architecture, fault modeling, test standards, and industry DFT/DFD/Automatic Test Pattern Generation (ATPG) tools with Application-Specific Integrated Circuit (ASIC) DFT, synthesis, simulation, and verification flow. Preferred qualifications for this position include experience with DFT for a subsystem with multiple physical partitions, Internal JTAG (IJTAG) ICL, Procedural Description Language (PDL) terminology, ICL extraction, Instrument Connectivity Language (ICL) modeling with Siemens Tessent Tool, Spyglass-DFT, DFT Scan constraints, and evaluating DFT Static Timing Analysis (STA) paths. Knowledge of coding languages like Perl or Python, as well as familiarity with DFT techniques like SSN and HighBandwidth IJTAG, are also desirable. As a part of the team responsible for developing custom silicon solutions for Google's direct-to-consumer products, you will play a crucial role in shaping the future of hardware experiences. Your contributions will drive innovation in products that are loved by millions worldwide, delivering unparalleled performance, efficiency, and integration. Google's mission to organize the world's information and make it universally accessible and useful guides our work, combining the best of Google AI, Software, and Hardware to create radically helpful experiences. In this role, you will collaborate with Design for testing (DFT) engineers, Register-Transfer Level (RTL), Physical Designer Engineers, System on a chip (SoC) DFT, and Product Engineering team. Your responsibilities will include working on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) Architecture with multiple voltage, power domains, writing scripts to automate the DFT flow, developing tests for Production in the Automatic Test Equipment (ATE) flow, and collaborating with the DFT team to deliver two or more Subsystems in a SoC.,

You will be responsible for executing customer projects independently with minimum supervision, guiding team members technically in various fields of VLSI Frontend Backend or Analog design. As an individual contributor, you will take ownership of tasks/modules such as RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, Signoff, etc., leading the team to achieve results. Your responsibilities will include completing assigned tasks successfully and on-time within the defined domain(s), anticipating, diagnosing, and resolving problems, coordinating with cross-functional teams as necessary, delivering on-time quality work approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost accepted by UST Manager and Client. Additionally, you will be expected to write papers, file patents, and devise new design approaches. Your performance will be measured based on the quality of deliverables, timely delivery, reduction in cycle time and cost, number of papers published, number of patents filed, and number of trainings presented to the team. You will be expected to ensure zero bugs in the design/circuit design, deliver clean design/modules for ease of integration, meet functional specifications/design guidelines without deviation, and document tasks and work performed. Furthermore, you will be responsible for meeting project timelines, facilitating other team members" progress by delivering intermediate tasks on time, and seeking help and support in case of any delays. Your role will also involve active participation in team work, supporting team members as needed, anticipating when support may be required, and being able to explain project tasks and support delivery to junior team members. Your creativity and innovation will be showcased through tasks such as automating processes to save design cycle time, participating in technical discussions, training forums, white paper or patent filings, and contributing to technical discussions. Your skill set should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, Makefile, Spice, and familiarity with EDA Tools like Cadence, Synopsys, Mentor tool sets, and various simulators. You should have strong technical knowledge in IP Spec Architecture Design, Micro Architecture, Bus Protocols, Physical Design, Circuit Design, Analog Layout, Synthesis, DFT, Floorplan, Clocks, P&R, STA, Extraction, Physical Verification, Soft/Hard/Mixed Signal IP Design, and Processor Hardening. Additionally, you should possess communication skills, analytical reasoning, problem-solving skills, and the ability to interact effectively with team members and clients. Your knowledge and experience should reflect leadership and execution of projects in areas such as RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and understanding of design flow and methodologies. Independent ownership of circuit blocks, clear communication, diligent documentation, and being a good team player are essential attributes for this role. Overall, your role will involve circuit design and verification of Analog modules in TSMC FinFet technologies, developing circuit architecture, optimizing designs, verifying functionality, performance, and power, as well as guiding layout engineers. Strong problem-solving skills, results orientation, attention to detail, and effective communication will be key to your success in this position.,

Job Summary Java development Lead with hands-on coding and solution designing skills for Functions DFT. Candidate should be able to code and lead and formulate the deliveries for DFT Functions Domain. The candidate should develop Applications and enable Development teams with cookie cutter reusable patterns / components for development with end-to-end ownership / life cycle. Candidate should also be able to lead and guide community group contributing for reusable component/library. Key Responsibilities Have a strong sense of responsibility and ownership and contributes heavily to technical evaluations, decisions, software design & development activities. Contributes to building prototypes or proof of concepts and translates them to production grade applications or reusable components. Keeping track of industry developments, conducting R&D to incorporate best in class practices and methodologies and sharing the same with team and stakeholders. Leading the end-to-end delivery with adherence to timelines & agile practices. Participate in code reviews, assist & mentor team on technical aspects. Key Expertise Expertise in programming language – Java Expertise in web application development using one or more frameworks such as Spring boot, Quarkus, node.js, go lang. Proficient in designing and developing applications using microservices, cloud native architecture & REST API. Expertise in API design and is proficient in applying various design patterns. Experience on ES6, HTML5, React, Redux, JavaScript MVC patterns / frameworks and CSS pre-processers and strategies for scalable CSS, Babel and Webpack. Strong expertise in one or more databases – RDBMS & NoSQL. Strong coding, debugging, profiling, testing and documentation skills. Proficient in version control – GitHub / bitbucket and code reviews. Strong in one or more container ecosystem – Kubernetes, EKS, AKS. Experience in one or more messaging, streaming systems – Kafka, RabbitMQ. Strong in one or more cloud computing platforms – AWS, GCP, Azure. Experience in creating high level architecture & design diagrams. Strong knowledge in CI/CD - ADO Excellent knowledge of Scrum methodology and related processes. Excellent communication and leadership skills. Other Responsibilities Regulatory & Business Conduct Display exemplary conduct and live by the Group’s Values and Code of Conduct. Take personal responsibility for embedding the highest standards of ethics, including regulatory and business conduct, across Standard Chartered Bank. This includes understanding and ensuring compliance with, in letter and spirit, all applicable laws, regulations, guidelines and the Group Code of Conduct. Effectively and collaboratively identify, escalate, mitigate and resolve risk, conduct and compliance matters. [Fill in for regulated roles] Lead the [country / business unit / function/[team] to achieve the outcomes set out in the Bank’s Conduct Principles: [Fair Outcomes for Clients; Effective Financial Markets; Financial Crime Compliance; The Right Environment.] Key stakeholders Enterprise Architects Technology Delivery teams Business Product owners Skills And Experience Java Web application development using one or more frameworks such as Spring boot, Quarkus, node.js, go lang Knowledge on ES6, HTML5, Lit, React, Redux, JavaScript MVC patterns / frameworks and CSS pre-processers and strategies for scalable CSS, Babel and Webpack Experience in one or more container ecosystem – Kubernetes, Openshift, EKS, AKS One or more container ecosystem – Kubernetes, Openshift, EKS, AKS Communication Skills High level architecture & design diagrams Qualifications Bachelor’s in computer science, software engineering or related technical field. 8+ years of relevant work experience. Experience in one or more following: designing distributed systems, designing scalable enterprise applications, application security, full stack development (is a plus). Certification on Java, Architecture, Cyber Security, Cloud will be an added advantage About Standard Chartered We're an international bank, nimble enough to act, big enough for impact. For more than 170 years, we've worked to make a positive difference for our clients, communities, and each other. We question the status quo, love a challenge and enjoy finding new opportunities to grow and do better than before. If you're looking for a career with purpose and you want to work for a bank making a difference, we want to hear from you. You can count on us to celebrate your unique talents and we can't wait to see the talents you can bring us. Our purpose, to drive commerce and prosperity through our unique diversity, together with our brand promise, to be here for good are achieved by how we each live our valued behaviours. When you work with us, you'll see how we value difference and advocate inclusion. Together We Do the right thing and are assertive, challenge one another, and live with integrity, while putting the client at the heart of what we do Never settle, continuously striving to improve and innovate, keeping things simple and learning from doing well, and not so well Are better together, we can be ourselves, be inclusive, see more good in others, and work collectively to build for the long term What We Offer In line with our Fair Pay Charter, we offer a competitive salary and benefits to support your mental, physical, financial and social wellbeing. Core bank funding for retirement savings, medical and life insurance, with flexible and voluntary benefits available in some locations. Time-off including annual leave, parental/maternity (20 weeks), sabbatical (12 months maximum) and volunteering leave (3 days), along with minimum global standards for annual and public holiday, which is combined to 30 days minimum. Flexible working options based around home and office locations, with flexible working patterns. Proactive wellbeing support through Unmind, a market-leading digital wellbeing platform, development courses for resilience and other human skills, global Employee Assistance Programme, sick leave, mental health first-aiders and all sorts of self-help toolkits A continuous learning culture to support your growth, with opportunities to reskill and upskill and access to physical, virtual and digital learning. Being part of an inclusive and values driven organisation, one that embraces and celebrates our unique diversity, across our teams, business functions and geographies - everyone feels respected and can realise their full potential. Recruitment Assessments Some of our roles use assessments to help us understand how suitable you are for the role you've applied to. If you are invited to take an assessment, this is great news. It means your application has progressed to an important stage of our recruitment process. Visit our careers website www.sc.com/careers

SE NIOR SILICON DESIGN ENGINEER 1. Must have SoC implementation knowledge with deep level expertise in at least one domain. Have responsibility for processes of significant technical importance and for results in SoC implementation and/OR related areas. Solve complex, novel and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation. Influences technical decisions that have a significant impact on final product. Requires limited supervision and is evaluated according to project performance. Coaches and mentors less experienced staff; influences others as a technical leader. very good communication and presentation skills Proficiency in scripting Required Skills: SoC implementation expertise. Multi million gates integration. Low power implementation, Constraints validation, Formal verification Floorplanning, Power planning. Clock Tree Synthesis (CTS). Awareness of Synthesis, SCAN and DFT implementation Static Timing analysis (STA). Analysis: IR, EM, Noise. Physical Verification #LI-PK2

Solid Experience in DFT Architecture. The candidate should have experience with ATPG, JTAG, BSCAN, BIST and MBIST flows. Experience on Hierarchical DFT techniques using Pattern Retargeting in Tessent flow Strong knowledge of the Tessent Shell environment and Tessent tools The desired candidate must have specific emphasis on the following tools Test Kompress / Fastscan ATPG, MBIST, Boundary scan. Hands on experience in simulating scan patterns and debugging pattern mismatches during verification process Experience in helping to debug failing scan patterns on the ATE is highly desirable. Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification.(Mentor, Cadence, Synopsys) Must be able to simulate and debug MBIST testbenches. Ability to come up with a detailed test plan based on the Arch specs Should be knowledgeable in all SOC functions such as Digital design, STA, Synthesis, PnR, DV and ATE test. The candidate should have prior experience in managing and developing teams Required Qualification B.E / B.Tech / M.E / M.Tech in Electrical / Electronic Engineering.experience-10-16 years Preferred experience of handling 10+ team members. Good understanding and exposure to SoC design and architecture Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects Comfortable with VCS / Verdi and excellent debugging skills Logical in thinking and ability to gel well within a team and be a proactive member of the team. Good communication and leadership skills Excellent team player High Integrity Job Type Full Time Job Location Hubballi

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. At Amazon, DFT (Design-for-Testability) is a multi-faceted job that involves architecture definition, logic design, verification, test patterns generation, chip bring-up and more. As a DFT Engineer, you will impact and see the device through its entire lifecycle, from definition stage to high volume production. You will be working in close collaboration with multiple VLSI engineering groups including design, verification, backend, test, reliability and more. As part of the chip design group, you will: Contribute to the design and verification of DFT logic and components Help to drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon Review sign-off level timing closure using static timing analysis of DFT modes Perform wafer probe testing, ATE testing, silicon bring-up, diagnosis and support for physical failure analysis Take high volume chips to production with high coverage ATE test program BS degree in Computer Engineering/Electrical Engineering 5+ years in semiconductor companies as a DFT lead/manager Chip design experience in Verilog and System Verilog Chip verification experience, UVM methodology Scan insertion tools and methodologies MBIST and BISR, BIHR insertion tools and methodologies EFUSE controllers and related structures Top level DFT architecture definition experience Gate-level simulations Static timing analysis, DFT related timing closure Scripting (Perl/Tcl) MS degree in Computer Engineering/Electrical Engineering or related field Excellent communication skills. Should be able to well communicate and establish relations with internal customers , Manufacturing, and equipment vendors Energetic, self-motivated Pro-active, oriented on execution Attentive to details and quality Team player, with the ability to work in a rapidly evolving/changing environment Ability to work well with overseas partners

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior SoC Integration Design Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have Fun. Make history. In this role, as a Senior Physical Design Engineer, you will be part of the team developing SoCs to be deployed in a range of Amazon devices. You will integrate industry standard and custom hardware IP and subsystems into SoCs to accelerate applications in machine learning, computer vision and robotics. You will work closely with System Architects, SoC architects, IP developers and SoC RTL design teams to develop SoCs that meets the power, performance and area goals for Amazon devices. You will help define the processes, methods and tools for physical design and implementation of large complex SoCs. Develop chip level and subsystem level netlists integrating IPs and new design. Own all aspects of physical design implementation through synthesis, formal verification, floor planning, bus / pin planning, power domain implementation, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off. Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure at the block and Sub System level. . Work closely with third party design and fabrication services to deliver quality first pass silicon that meets all performance, power and area goals. Contribute to developing physical design methodologies. . Signoff flows including STA, formal verification, EM/IR, reliability and Physical Verification. Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. Teams BS + 10yrs or MS + 7yrs in EE/CS 10+ years of experience in all aspects of physical design implementation multiple tape-outs in FINFET technologies such as 5nm/7nm, 14/16nm. Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) to block design for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO Scripting experience with Tcl, Perl or Python and ability to drive physical design flow automation. Must have good communication and analytical skills. Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO Thorough knowledge of device physics, custom/semi-custom implementation techniques. Experience solving physical design challenges across various technologies such as CPU, DDR, PCIe, fabrics etc. Experience in extraction of design parameters, QOR metrics, and analyzing trends. Experience with DFT DFM flows. Experience leading top level of SoC and all integration issues between IPs and partitions, drive package requirements, resets/clocks and power detection at SoC level Ability to provide mentorship, guidance to junior engineers and be a very effective team player.

SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and timing closure support. Familiarity with Verilog and RTL simulation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

TECHNICAL LEAD – DFT SmartSoC is looking for a smart and enterprising leader with expert knowledge in DFT to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking. You will be responsible for leading and managing a team, client communication, and project execution. Job Responsibilities- Lead an internal DFT team, executing projects for an offshore client Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 7+ years of experience in DFT, mainly Scan Architecture, ATPG & MBIST Experience in planning scan chains, running scan insertion flow Experience in latest Cadence tool set Genus & Modus Experience in ATPG for Stuck@, TFT, IDDQ & Path delay faults with tough coverage targets Experience in MBIST architecture, generation and implementation Experience in AECQ100 requirement standard is a big plus Experience in working with a multi-site team is a big plus Experience in working on critical time-bound projects is a big plus Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

1-3 years of experience in RTL DFT Verification (DFx). Good Understanding of JTAG IEEE-1149.1 and IJTAG IEEE P1687 standard. Understanding of using ICL and PDL files for verification and knows to create a testbench. Experience in JTAG RTL verification within any UVM. Able to debug simulation fails effectively utilizing debug tools like Synopsis Verdi. Basics of system Verilog, Basics of UVM, and preferably System Verilog assertions Scripting knowledge of TCL/Perl. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Candidates need to have good experience in Tessant tools Candidates need to have good experience in ATPG pattern generation and simulation(both timing and no timing) Candidates need to have good experience in Scan insertion Experience should be more than 6+ years Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly experienced Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong foundation in SystemVerilog (SV) and Universal Verification Methodology (UVM). In addition to standard verification skills, this role requires expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST (Memory Built-In Self-Test), SCAN, PG (Pattern Generator), and PM (Pattern Memory). Key Responsibilities: IP and SOC Verification Perform comprehensive IP and SOC verification to ensure the reliability and functionality of integrated circuits. SystemVerilog (SV) and UVM Proficiency Demonstrate a strong understanding of SystemVerilog and Universal Verification Methodology for efficient verification processes. CDP, GDP, DFT DV Expertise Possess expertise in Compressed Data Pattern (CDP) and Generic Data Pattern (GDP) methodologies. Proficiency in Design for Test in Design Verification (DFT DV) techniques, including JTAG, MBIST, SCAN, PG, and PM. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong knowledge of SystemVerilog (SV) and Universal Verification Methodology (UVM). Expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST, SCAN, PG, and PM. If you are a talented Design Verification Engineer with a deep understanding of IP and SOC verification, as well as specialized expertise in CDP, GDP, and DFT DV methodologies, we encourage you to apply. Join our dynamic team and contribute to the advancement of cutting-edge technology. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech) Excellent communication skills, both verbal and written Experience: Minimum of 7 years of experience in the field Proficiency in DVT pattern experience Experience with ATE and functional vectors generation Understanding of Stimgen flow Prior experience with AMD is preferred Skills: Strong debugging skills Experience with MBIST, JTAG, and Phy-loopback NoteCandidates are encouraged to provide a detailed resume showcasing their relevant experience and skills. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Number of Open Positions: 7 Experience: 4 to 7+ years Location: Bangalore : We are seeking highly skilled and motivated DFT-DV Engineers to join our dynamic team in Bangalore. As a DFT-DV Engineer, you will play a pivotal role in ensuring the quality and reliability of our digital designs through Design for Test (DFT) and Design Verification (DV) methodologies. The ideal candidates should possess a minimum of 4 to 7+ years of experience in the field, with a strong background in DFT DV flow, JTAG, MBIST, SCAN, PG, PHY-LP, and BSCAN. Key Responsibilities: DFT Implementation: Collaborate with design and verification teams to define and implement DFT strategies and methodologies that enable efficient testing of complex digital designs. Scan and ATPG: Develop and maintain scan insertion, Automatic Test Pattern Generation (ATPG), and compression methodologies to achieve high test coverage. Memory BIST: Implement and verify Memory Built-In Self-Test (MBIST) solutions for embedded memories in the design. JTAG and Boundary Scan: Develop JTAG and Boundary Scan solutions to facilitate efficient testing and debugging of digital designs. Power Management: Work on Power Gating (PG) techniques to optimize power consumption during testing. PHY-LP Integration: Collaborate with PHY teams to ensure seamless integration of low-power features into the design. BSCAN Integration: Implement Boundary Scan (BSCAN) infrastructure to enhance testability and debug capabilities. Verification: Verify DFT features and ensure their correctness through simulation and formal verification. Documentation: Prepare detailed documentation, including DFT specifications, test plans, and reports. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or related field. 4 to 7+ years of experience in DFT-DV engineering. Strong expertise in DFT methodologies, including scan, ATPG, MBIST, JTAG, BSCAN, and PG. Proficiency in industry-standard EDA tools for DFT implementation. Experience with low-power design and PHY-LP integration is a plus. Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills. If you are a proactive and results-oriented engineer with a passion for ensuring the quality and reliability of digital designs, we encourage you to apply. Join us in our mission to develop cutting-edge technology and make a significant impact in the semiconductor industry. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech) Excellent communication skills, both verbal and written Experience: 5-8 years of experience in RTL Design with exposure to synthesis OR 8+ years of experience in RTL Design Strong understanding of digital basics Proficiency in RTL coding (Verilog), IP design, and RTL integration Hands-on experience with LINT, CDC, and RDC Experience in writing UPFs and CLP/VCLP checks Familiarity with synthesis flow and validating design constraints Specific domain knowledge in ARM protocols, PCIe, Ethernet, RISC V, DDR, etc. Strong scripting knowledge Responsibilities: Understand the overall ASIC flow and effectively collaborate with multiple teams such as DV, DFT, Synthesis/Implementation, and PD teams Ability to take on the role of a Technical Manager while maintaining hands-on contributions NoteInterested candidates should provide a detailed resume highlighting relevant experience and skills. Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaHyderabad

Job Description Manage multiple new products through their full product lifecycle, Product Compliance to Sustainment of production released parts Generate Characterization, Qualification, Bench-to-ATE Correlation and Test Limit plans for new products based on REA guidelines and JEDEC standards Drive measurements/data collection and statistical analysis for Characterization, Qualification, Correlation, Production Test Limit setting, and any other specialized testing for datasheet parameters Cost reduction via yield improvement and test time reduction from safe launch study at both NPI and MP stage. Excursion management (Low yield and RMAs) and MRB lot disposition. Work with DE/TE team to design and implement production test solutions. Continually look for opportunities to improve the NPI process. Focus areas include streamlining Test, Qualification and Characterization plans and strategies, reducing documentation overhead, and leveraging NPI efficiencies such as Qualification by Similarity (QBS) Be a mentor to junior Product Engineering team members to accelerate their technical and career growth Contribute technical expertise to business critical projects as required to advance MID (Memory Interface Division) business objectives Qualifications Preferred with 10+ years experience from Product Engineer, Quality Engineer, Test Engineer, Validation Engineer and FA Engineer in fabless. Deep knowledge of Digital / Analog Product Characterization Technique. Hands-on experience to work on Characterization Plan, PVT test, Report. Strong statistical data analysis background for NPI/MP products. Hands-on experience from PDF (TIBCO Spotfire, Exensio), JMP, Galaxy Examinator,VB, etc. Strong working knowledge of Product / Package Qualification Process. Hands-on experience from HTOL / ESD / LU / HTS / TC / ELFR / UHAST / Endurance / Retention, etc. Experienced in ATE testing on V93K (PS1600 /PS9G/PSSL) ATE testers in CP/FT test. Hands-on experience from ATE test debug analysis with Test program , STDF, datalog, etc. Experienced in Bench testing of Electrical Characteristics, Tx/Rx Jitter, Eye Diagram for Memory Interface Products (RCD, DB, TS, SPD, etc) Familiar with Digital / Analog Product DFT / DFM method. JEDECT Spec and Product Datasheet. Deep knowledge of CMOS Process in HKMG / FINFET process. Ability to manage complex projects in parallel and on schedule . Preferred with Project Management experience. Solid organizational skills with attention to detail for risk management Good communication / reporting skills Self-motivated to work independently and in a team environment with project teams from different regions / timezones High energy, driven-to-succeed personality in fast pace environment Experience working with databases and creating regular reports Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Mandatory Skills: Strong understanding of DFX concepts : DFT, DFM, DFA, DFR, etc. Experience in semiconductor, electronic hardware, or embedded product development Proficiency in DFT/DFM tools and methodologies Familiarity with manufacturing processes , assembly line constraints, and test strategies Knowledge of FMEA, FTA, reliability analysis, and root cause problem solving Working knowledge of EDA tools (for VLSI roles) or CAD/PCB tools (for hardware roles) Scripting or data analysis (Python, MATLAB, Excel) Job Type: Full-time Pay: ₹359,487.15 - ₹1,548,892.09 per year Work Location: In person

Job Summary We are seeking a detail-oriented and innovative Electronics Hardware Engineer to design, develop, and test cutting-edge electronic systems and products. The ideal candidate will be responsible for schematic design, PCB layout, prototyping, testing, and hardware validation across the full product development lifecycle. You will work closely with cross-functional teams including software, mechanical, and manufacturing engineers. Key Responsibilities Design and develop analog and digital circuits based on project requirements. Create schematics and PCB layouts using tools such as Altium Designer, KiCAD, Eagle, or OrCAD. Select and source appropriate electronic components based on performance, cost, and availability. Build and test prototypes , and iterate based on performance and reliability testing. Conduct circuit simulations and signal integrity analysis. Work with firmware/software teams to ensure proper hardware-software integration. Perform DFT (Design for Test) and DFM (Design for Manufacturing) analysis. Collaborate with production teams to bring designs to mass production. Document hardware specifications, test procedures, and design decisions. Troubleshoot hardware failures and support debugging in lab and field environments. Stay current with emerging technologies and regulatory standards (e.g., CE, FCC, RoHS, EMC/EMI). Qualifications Required: Bachelor’s or Master’s degree in Electronics Engineering , Electrical Engineering , or related field. Strong understanding of analog/digital electronics , microcontrollers , power supplies , and communication interfaces (I2C, SPI, UART, CAN, etc.). Experience in schematic capture and multi-layer PCB design . Hands-on experience with oscilloscopes, multimeters , and lab testing tools . Familiarity with circuit simulation tools (e.g., LTSpice, PSpice). Proficiency in hardware debugging and root cause analysis. Preferred: Experience with embedded systems , RF design , or IoT hardware . Knowledge of compliance testing (EMC/EMI, safety standards). Exposure to automated test frameworks or hardware validation scripting . Soft Skills Strong analytical and problem-solving abilities Excellent communication and teamwork skills Ability to manage multiple projects and meet deadlines Passion for technology and continuous learning Job Type: Full-time Pay: From ₹8,000.00 per month Ability to commute/relocate: Madurai, Tamil Nadu: Reliably commute or planning to relocate before starting work (Preferred) Education: Bachelor's (Required)