We are seeking a seasoned SoC Architect with expertise or significant interest in System Architecture. You have had significant success driving architecture, product roadmaps and product requirements. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead architecture teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: Define product features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements Knowledge sharing and other contributions to Platform & System Architecture As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs Support Post-Si teams for Product Performance, Power and functional issues debug/resolution PREFERRED EXPERIENCE: Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels Excellent communication, management, and presentation skills. Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies ACADEMIC CREDENTIALS: bachelors or masters degree in related discipline preferred

Identify , recruit & develop new channel partners to meet business goals . Liaison between AMD and its partners, ensuring seamless communication and alignment on business objectives. Engage in Joint Business Planning with OEMs and Channel Partners to increase AMD SoW Conduct weekly meetings with partners sales team to review performance against quarterly goals . Identify opportunities and develop action plan for future. Build and deploy customer engagement plan which includes direct customer engagement and working with channel partners. Identify potential SMB customers & drive AMD adoption to meet or exceed our SMB growth targets. Position and sell AMD technology in new customers and new market segments. Understand products, customer needs, competitors, industry issues, and trends, then continually refine the message, positioning, product demos, and sales tools to meet business objective . Build and manage the sales pipeline . Train & enable partners sales & presales on AMD products & solutions . Execute AMD Partner Programs ,aligning it with overall business goals. Education / Experience requirement : Bachelor s or master s degree . MBA desired 10 to 12 yrs of IT hardware Sales experience

The team works on cutting edge research opportunities helping AMD business to flourish against competition. The team takes up research problems/challenges by the Business Units and help them resolve those issues in the AMD products. The engineer is expected to be highly innovative, motivated to solve real engineering problems with doing independent research. The areas may include CPU design/optimizations, Deep Learning optimizations for CPU/GPUs/AIEs, and related areas. The candidate is expected to have deep understanding of systems (both architectures, OS/Compilers) and domain knowledge such as Deep Learning. We are looking for a Member of Technical Staff with experience in research in the above areas and ability to deliver innovative solutions in systems/architecture and domain specific software. THE PERSON: You are a self-starter with passion for driving large-scale technical projects, consistent record of solving highly sophisticated problems along with solid technical background. You possess excellent interpersonal, verbal, and written communication skills, as we'll as excellent organizational and time management skills. You are used to working independently, yet as part of a team where teamwork is of utmost importance. KEY RESPONSIBILITIES: Understand the challenges in current design/optimization opportunities in the software. Work with Business units to articulate the problem. Coming out with a plan for solving this for next couple of years Driving the research to solve the problem and possibly publishing the work in competitive journals. Reporting the progress and presenting this to execs PREFERRED EXPERIENCE: PhD/MTech in CSE from a reputed institute with exceptional grades Good knowledge of C++, proven ability to read and understand Java and Python code Working knowledge of scripting languages such as shell scripts and Perl is an added advantage. Excellent research and analytical skills Excellent organizational and time management skills Excellent interpersonal, verbal, and written communication skills Deep understanding of CPU designs and Deep Learning stack ACADEMIC CREDENTIALS: PhD/masters in Computer Science & Engineering Degree or equivalent 10+ years of software development experience Understanding of IP licensing principles and open-source compliance

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

Collaborates in developing new or modified, high-density, printed circuit boards. Work with Design Engineer and Simulation Engineer in making sure PCB layout adheres to SI/PI requirements. Work on the Layout design for highspeed interfaces like PCIe Gen5/6, Multi-Gigabit serial buses, DDR5/LPDDR5/DIMM and other circuits. Work on the characterization/evaluation and production boards. Create or modify footprints as per guideline and maintain library database. Should work with Fabrication and Assembly house for DFX queries. Should follow process, guidelines, and checklists to produce error free design. Should be able to meet the schedule. Job Description : 12 + years of layout design experience in High-Speed Digital Design, Analog, and RF boards. Excellent experience in routing of interfaces like PCIe Gen5/6, Multi-Gigabit serial buses, DDR5/LPDDR5/DIMM, Flash, SPI, I2C and High current switching power supplies Excellent hands-on knowledge of Cadence Allegro PCB design, constraint manager. Excellent knowledge of IPC standards, HDI, back drilling, stack up selection. Excellent experience in design with DFM/DFT/DFA constraints. Hands on experience on CAM350 gerber review tool. Hands on experience on footprint creation and library database maintenance. Good understanding of mechanical 3D model design practice. Ability to work independently with minimal supervision and ability to handle multiple tasks. Ability to work cross-functional along with strong interpersonal and communication skills.

The candidate will get to work on the Verification of complex PLLs that are delivered to various AMD SoCs. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience in collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. K EY RESPONSIBLITIES : Verification of IP features : Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations. Create methodology-based (UVM) verification testbenches and components from scratch for various IP features. Quality deliverables through regressions Verification coverage: code-coverage, functional coverage, assertions, to achieve 100% verification completeness Reviews, and feedback to design/architecture teams. P REFERRED EXPERIENCE : Years of experience 13+ Required. Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions (SVA) Expertise in code and functional coverage. Excellent Problem solving and debugging skills. Excellent Communication skills. Strong digital design knowledge. Exposure to UPF based low power RTL verification. Prior experience in leading a team is desirable. Prior experience in PLL verification and Mixed signal verification methodology is highly desirable. Exposure to digital-analog co-simulations (cosims) is desirable. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

We are looking for an adaptive, self-motivative EMIR engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The EMIR team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Good understanding of IR/Power-Domain-Network signoff at SOC & block level Experience in RHSC tool Good at scripting python/perl/tcl Must have knowledge of Physical Implementation (Synthesis and Place&Route) Effective communication ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering with 5+Yrs of exp.

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are meticulous about Power, Performance and Area while driving schedule and managing cost. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

We are looking for a Fellow-level Engineer to join our team to develop world-class DFT architecture for EPYC Server products. In this role you will be engaged with the SoC Architects, Micro Architects, PD Engineers, Product Engineers, etc, to define and implement the DFT Architecture, guide/technically lead the DFT Team to ensure right pre-si verification is done for the DFT logic, and the highest level of Scan coverage is achieved to hit the product goals. You will also be responsible for driving innovation to continuously improve the execution and also drive TTR (Test Time Reduction) THE PERSON: You will possess very strong DFT knowledge and bring broad experience in with a strong, self-motivated work ethic and leadership qualities. KEY RESPONSIBILITIES: Work closely with the SoC Architecture and uArch teams to define the DFT architecture. Be the Tech Lead driving DFT RTL implementation, DFT functional and Scan capture timing closure, Scan/ATPG implementation to hit the product coverage goals, interactions with the Product Engineering team to ensure on-time and FirstTimeRight pattern delivery and silicon bring-up Drive the required pre-silicon reviews for RTL, DFT DV and ATPG to ensure clean silicon bring-up Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to comprehend and validate all the usage models Work with the post-silicon team on debug support and to help root-cause any failures Be upto date with the industry trends and bring-in the latest to the AMD products Work with DFT Tool Vendors and drive improvements based on our requirements REQUIREMENTS: 15+ years of in-depth DFT experience having driven multiple Tapeouts and silicon bring-ups across different process nodes. Good understanding and exposure to SoC design and architecture Very good understanding of verif and timing concepts having handled DFT timing closure Exposure to all DFT concepts such as JTAG, SCAN, MBIST, BScan, etc Comfortable with VCS/Verdi and Mentor TK. Logical in thinking and ability to gel we'll within a team Good stakeholder management Ability to quickly adapt to changes and handle pressure Good communication and leadership skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer engineering/Electrical Engineering

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

Identify , recruit & develop new channel partners to meet business goals . Liaison between AMD and its partners, ensuring seamless communication and alignment on business objectives. Engage in Joint Business Planning with OEMs and Channel Partners to increase AMD SoW Conduct weekly meetings with partners sales team to review performance against quarterly goals . Identify opportunities and develop action plan for future. Build and deploy customer engagement plan which includes direct customer engagement and working with channel partners. Identify potential SMB customers & drive AMD adoption to meet or exceed our SMB growth targets. Position and sell AMD technology in new customers and new market segments. Understand products, customer needs, competitors, industry issues, and trends, then continually refine the message, positioning, product demos, and sales tools to meet business objective . Build and manage the sales pipeline . Train & enable partners sales & presales on AMD products & solutions . Execute AMD Partner Programs ,aligning it with overall business goals. Education / Experience requirement : Bachelor s or master s degree . MBA desired 10 to 12 yrs of IT hardware Sales experience

You have a passion and proven track record of emulation domain. You are a team player who has excellent communication skills and experience collaborating in a corporate environment with other architects & engineers located in different sites/time-zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. P REFERRED EXPERIENCE : Technical - 14+ years of experience in Pre & post silicon IP or SOC Validation Working knowledge of the HSIO protocols PCIE, ethernet , ORAN/eCPRI and legacy IO - I2C/I3C, UART, GPIO, SPI Extensive experience with engineering lab equipment, oscilloscopes, protocol analyzers, signal generators, etc. Hand on experience with one or more types of emulators (Palladium, Protium, Zebu ) Hands-on experience and well versed in one or more of the scripting languages like C, tcl and Python. Extensive experience with debug techniques and methodologies. ARM Coresight knowledge is a plus. Ability to develop and execute test cases in both pre and post Si environments In-depth knowledge of PC architectures and system technologies. Attention to detail and the ability to analyze data quickly is a must. Ability to flex responsibilities over the development lifecycle. Knowledge on the system drivers, firmware and software is a plus. Solid grasp of concepts of HW/SW interface Firsthand experience with silicon bringup, complex system debug, or bare-metal programming. Strong programming skills (assembly, C, Perl/Python) Experience in a full development cycle from pre-silicon to silicon bringup Experience with SOC fabrics, memory controllers, and SOC peripherals Leadership Drive end-to-end project delivery, ensuring quality and performance. Lead and mentor a team of developers/engineers, fostering technical excellence and collaboration. Collaborate with cross-functional teams including design, verification, firmware and project management. Excellence in technical communication with peers and non-technical cohorts Qualifications Bachelor s degree or higher in EE, CE, or CS Very strong problem solving, debug and analysis, and automation skills

AMD is looking for a talented, self-driven and motivated engineer to technically lead AIG s Simulation Modeling projects working on AMD s XDNA (AI Engine) architecture and the Vitis AI family of software tools. The XDNA is an industry leading architecture in terms of performance per watt and is used in AMD s client and embedded devices as the primary engine for Machine Learning workloads. It is the hardware engine behind Windows Co-pilot on AMD devices. The team provides a fast-paced environment offering each of its members immense opportunity to interact with a wide variety of people including from other organizations like hardware designers, marketing, support, and even direct customer interaction, and truly learn and grow their skills and capabilities. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated technical issues to resolution. They should have demonstrated ability to identify technical problems, explore and propose viable options, and apply technical solutions. They should be able to excel in a global team environment with strong verbal and written communication skills. . KEY RESPONSIBILITIES: Vitis AI is AMD s primary SDK that enables users to compile and run their ML models on the XDNA architecture. As a senior member of this high-performance team, the selected candidate will have responsibility to model the XDNA architecture in terms of functionality, accuracy and simulation speed. Candidate will work with compiler, runtime/driver teams to bring up latest AI models like CNNs, Transformers, StableDiffiusion, NLPs etc. on the XDNA simulator. This is a crucial part of AMD s shift-left strategy for the successful bring up of new devices and day 0 enablement of models. Candidates would develop a deeper understanding of the various ML models, and how they are executed, identify performance bottlenecks and enable faster development. PREFERRED EXPERIENCE: Minimum 10 years of relevant work experience. Strong background in C++ based development and debug, dealing with multi-threaded infrastructure and performance optimization Experience in creating cycle accurate modeling of IPs in C++ or SystemC / TLM. Understanding of SoCs, and bringing up of software stack from driver to application on simulation model. Understanding hardware metrics like latency/throughput on any sub-system, and what changes impact those metrics. Experience in software development environment on both Linux and Windows is required. Experience in technologies like Virtual Platforms, SystemC/QEMU models, Emulation platforms, Hw/Sw co-design, and Performance analysis is desired. Familiarity with hardware languages like VHDL, Verilog and System Verilog for simulation using tools like Modelsim, VCS, Questa Sim is highly desired. ACADEMIC CREDENTIALS: Bachelor s or M asters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

Drive and lead execution with SOC teams for Design. Drive efficiency on execution of SOC for integration as well as various quality checks like lint, CDC, RDC, Synthesis, CLP, LEC, constraints quality checks. Drive quality and timely delivery to various teams like DV, DFT, Emulation & PD. Work with architecture team on high level arch and uArch definition. Work with IP team for IP requirement, deliverables and negotiations. Drive SOC from concept to productization. Work with customer requirements on product definition, feature, bounding box analysis and drive optimal solution. Work with business and design team on optimal development cost solution considering in die size, power, performance optimization. Work with program management team for SOC planning, schedule, resource demand/supply, critical path analysis, dev cost and execution. Work with SOC (Design, DFT, DV, PD), System and SW team to deliver next generation high performance SOC designs. Work with post-Si team to drive Si bring up and ramp to productization. Drive improvisation on methodologies in SOC design. Get technical alignment with experts across geographies. Develop plans and track progress to maintain aggressive development timelines. Has understanding on SOC and IP development milestones and drive execution to meet them. THE PERSON: Strong understanding of SOC design methodology & related flows. (Design integration including UPF, Lint, CDC, RDC, CLP, LEC). Also on various handoffs (DV, PD, DFT & Emulation) Leader with strong self-driving ability and winning attitude. Be able to drive technical alignment with experts across geographies to improve design methodologies. Strong interpersonal and stakeholders management skills. Strong problem-solving skills. Strong commitment to own/drive SOC development using well-defined metrics. Work with PM team on execution planning, to track quality metrics, milestone convergence, to assess risk, and ensure plan is on track. Detail-oriented candidate who can work seamlessly with larger SOC design team across geographies on driving the solutions. Technical Leader with strong self-driving ability and winning attitude. Should have excellent communication written, oral and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. KEY RESPONSIBILITIES: Driving SOC design execution across from concept to tape-out and productization. Contribute to Bounding box analysis, Design, DFT, Verification, Test-plan, Power Reduction, Timing Convergence & Floorplan, Tape-outs, System engineering and SW deliverables. Running regular execution meetings, scrums, standing meetings and resolving bottlenecks. Project planning, schedule, deliverables, risk/ mitigations. Presenting status update to senior executives. Good understanding of sign-off flows like Lint, CDC, RDC, Formal Equivalence, Low Power Checks, timing convergence (both tile-level and FCT), and full chip integration flows. Drive and improvise various design hand-offs to DV, DFT, PD and Emulation teams. Understanding design requirements, timelines and various milestones of a project and tracking project convergence status accordingly covering all aspects of the design cycle. Drive methodology development ideas/forums. Collaborate with CAD and EDA vendors to further strengthen AMD and S3 design methodology. Strong interpersonal skills to work across teams in different geographies. Provide technical direction, guidance, and Support to the engineering team. PREFERRED EXPERIENCE: Experience of successfully leading multiple SOC execution from spec to tape-out and productization. Expertise in SOC integration and implementation - IP Integration, SOC fabrics, Voltage / Clock domain crossings, DFT, Power intent design, RTL Quality checks, Clock, Reset, Fuses, Synthesis, Timing Analysis, Design Partitioning, PPA optimization, PnR, Timing analysis, Floorplan convergence, Physical design implementation and signoff. Experience in ASIC execution, customer engagement, deliverables and execution flow. Work with a team of Architects, Hardware and Software engineers to define the High-Level Architecture. Strong hands-on experience in different SOC design activities, Verification aspects, Test plan review, Debug/triage, bottleneck resolution etc. Strong Problem Solving and Debugging Skills Comfortable with design/implementation tools and flows like VCS, SOC Connectivity, Spyglass Lint/CDC/RDC, VCLP, Synthesis DC/FC, ICC, and Physical design implementation/signoff tools, STA and constraints analysis tools. Expertise in SOC architecture, System bus and IO protocol understanding (e.g. AXI, PCIe, Memory, uProcessor, etc.) Good understanding of System integration, multi-die methodology, packaging, yield, and system solution. Experience in working with SW team for BIOS, FW, Driver, SW stack, QA and SW release is a plus. Expertise in managing execution team, project planning, IP delivery timelines, deliverables and quality checks, Resource planning, critical path analysis, risks, and mitigation plan. Good understanding of Power, Performance and Area (PPA) optimization techniques. Good experience with Perl/TCL/Shell/Python scripting, and Verilog/VHDL RTL design. Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: ~5+ years of strong experience in leading end to end SOC design and ASIC execution. BE/B.Tech/ME/MTECH/MS or equivalent ECE/EEE with 12+ yrs. of experience

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification and performance verification at the core level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Create hardware emulation build to verify the IP functional performance Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility Provide technical support to other teams PREFERRED EXPERIENCE: Good at C/C++ Familiarity with SystemVerilog and modern verification libraries like UVM Experience/Background on Computing/Graphics is a benefit Experience with OpenGL/OpenCL/D3D programming is a benefit ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 4years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 10+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills Continuously drive methodology improvements to improve efficiency Mentor junior engineers to build a high performing team PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

As a SoC validation enigneer you will play a critical role in ensuring our custom silicon products meet AMD s quality standards and achieve production quality, working hands on you will be responsible for enabling the pre-silicon and post-silicon validation verification of next generation SoCs on multiple platforms. You will develop and execute test plans, design test environments and help build emulation and prototype models while working closely with architects, RTL designers, SoC and software development teams. THE PERSON: You have a passion and proven track record of emulation domain. You are a team player who has excellent communication skills and experience collaborating in a corporate environment with other architects & engineers located in different sites/time-zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Technical role requirements - 8+ years of experience in Pre & post silicon IP or SOC Validation Working knowledge of the HSIO protocols PCIE, ethernet , ORAN/eCPRI and legacy IO - I2C/I3C, UART, GPIO, SPI Extensive experience with engineering lab equipment, oscilloscopes, protocol analyzers, signal generators, etc. Hand on experience with one or more types of emulators (Palladium, Protium, Zebu ) Hands-on experience and well versed in one or more of the scripting languages like C, tcl and Python. Extensive experience with debug techniques and methodologies. ARM Coresight knowledge is a plus. Ability to develop and execute test cases in both pre and post Si environments In-depth knowledge of PC architectures and system technologies. Attention to detail and the ability to analyze data quickly is a must. Ability to flex responsibilities over the development lifecycle. Knowledge on the system drivers, firmware and software is a plus. Solid grasp of concepts of HW/SW interface Firsthand experience with silicon bringup, complex system debug, or bare-metal programming. Strong programming skills (assembly, C, Perl/Python) Key job responsibilities As an SoC Validation Engineer, you will be responsible for enabling the pre-silicon and post-silicon validation verification of next generation SoCs on multiple platforms such as emulation, prototyping and early silicon. You will develop and execute test plans, design test environments and help build emulation and prototype models while working closely with architects, RTL designers, SoC and software development teams. Basic Qualifications Bachelor s degree or higher in EE, CE, or CS Very strong problem solving, debug and analysis, and automation skills Experience with verification and validation of complex SOCs Preferred Qualifications Experience in a full development cycle from pre-silicon to silicon bringup MS or PhD in Computer Science, Electrical Engineering or related field Experience with SOC fabrics, memory controllers, and SOC peripherals Excellence in technical communication with peers and non-technical cohorts

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 4years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

Identify , recruit & develop new channel partners to meet business goals . Liaison between AMD and its partners, ensuring seamless communication and alignment on business objectives. Engage in Joint Business Planning with OEMs and Channel Partners to increase AMD SoW Conduct weekly meetings with partners sales team to review performance against quarterly goals . Identify opportunities and develop action plan for future. Build and deploy customer engagement plan which includes direct customer engagement and working with channel partners. Identify potential SMB customers & drive AMD adoption to meet or exceed our SMB growth targets. Position and sell AMD technology in new customers and new market segments. Understand products, customer needs, competitors, industry issues, and trends, then continually refine the message, positioning, product demos, and sales tools to meet business objective . Build and manage the sales pipeline . Train & enable partners sales & presales on AMD products & solutions . Execute AMD Partner Programs ,aligning it with overall business goals. Education / Experience requirement : Bachelor s or master s degree . MBA desired 10 to 12 yrs of IT hardware Sales experience