1063 Dft Jobs - Page 2

SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience ( eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc .) Experience with Mentor testkompress and/or Synopsys Tetramax /DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

SILICON DESIGN ENGINEER 2 THE ROLE: The focus of this role is to execute the front end implementation of sub-blocks or IP. This involves ownership of synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. KEY RESPONSIBILITIES: Responsible for front end implementation of IPs which includes synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure Collaborate with designer and PNR teams to achieve closure. Execute as per schedule. Complete quality delivery for synthesis and timing closure. Debug and resolve technical issues PREFERRED EXPERIENCE: Experienced in synthesis and timing closure Good to have experience in LEC, CLP Have handled blocks with complex designs, high frequency clocks and complex clocking complete understanding of timing constraints, low power aspects and concepts of DFT Have debug experience to solve issues. scripting and automation ACADEMIC CREDENTIALS: Bachelors with 2 years of experience or Masters degree with 1 years of experience in Electrical Engineering #LI-RP1

Where ASIC Physical Design, Sr Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12343 Remote Eligible No Date Posted 23/07/2025 Alternate Job Titles: ASIC Physical Design Engineer Place & Route Engineer Sr. Physical Design Specialist We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and detail-oriented engineer with a strong background in ASIC physical design and a keen interest in advancing semiconductor technology. You thrive in collaborative, fast-paced environments and are motivated by technical challenges that push the boundaries of what s possible in chip design. With your foundational education in electronics or electrical engineering, you have honed a solid understanding of CMOS and submicron ASIC flows, working on advanced technology nodes such as 28nm, 16nm, 14nm, 10nm, and 7nm. You possess hands-on experience with industry-leading EDA tools, including Synopsys ICC-II/FC, Design Compiler, PrimeTime, and Cadence Innovus, and are adept at developing, optimizing, and verifying robust ASIC design flows. Your curiosity drives you to stay on top of the latest methodologies, and your analytical mindset ensures you can solve complex problems with innovative solutions. You are comfortable taking ownership of tasks, whether it s developing flows, performing timing analysis, or releasing production views for IP. You communicate clearly, collaborate effectively, and are committed to delivering high-quality results with attention to every detail. You believe in continuous improvement, proactively seeking ways to optimize power, performance, and area (PPA) while maintaining the highest standards of quality. Most importantly, you are excited about making an impact in a global team that values diversity, learning, and technological excellence. What You ll Be Doing: Developing and optimizing ASIC design flows to build and verify standard cell libraries, ensuring the best possible Power, Performance, and Area (PPA) with uncompromised quality. Creating and maintaining Place & Route (P&R) methodologies using industry-standard tools such as Synopsys ICC-II/FC and Cadence Innovus. Releasing P&R production views for IP, ensuring readiness for downstream design and integration teams Conducting thorough physical verification (DRC/LVS), timing analysis (STA), and addressing design closure challenges across advanced technology nodes. Collaborating with cross-functional teams to integrate design flows, improve automation, and resolve technical issues throughout the ASIC lifecycle. Implementing and validating low-power design concepts using UPF/CPF formats, and ensuring robust power analysis and planning. Generating and managing technology files, library views (Milkyway, NDM), and deliverables such as LEF, DEF, GDS for standard cell libraries. The Impact You Will Have: Enable the creation of high-performance, energy-efficient silicon chips that power next-generation applications and devices. Drive improvements in PPA and overall design quality, directly influencing customer satisfaction and product competitiveness. Ensure timely and robust release of IP production views, accelerating time-to-market for Synopsys customers. Advance the state-of-the-art in physical design methodologies, contributing to Synopsys leadership in the semiconductor industry. Collaborate cross-functionally to share best practices and foster a culture of continuous improvement and innovation. Support the successful deployment of Synopsys tools and flows in real-world customer projects, reinforcing our reputation for technical excellence. What You ll Need: Bachelor s or Master s degree in Electronics or Electrical Engineering (or equivalent) from a reputed university. 1-2 years experience in ASIC design, with hands-on exposure to advanced process nodes (28nm, 16nm, 14nm, 10nm, 7nm) and multiple foundries. Strong understanding of CMOS, ASIC flow in submicron nodes, and expertise in Place & Route, physical verification (DRC/LVS), and timing analysis (STA). Proficiency with Synopsys (ICC-II/FC, Design Compiler, PrimeTime) and Cadence (Innovus, RC/Genus) EDA tools. Experience with all stages of the ASIC design flow, including Synthesis, DFT, timing analysis, floor planning, power planning, CTS, ECO flow, STA, and power analysis. Good grasp of low power design concepts, UPF/CPF formats, and standard cell library view generation processes (Milkyway, NDM). Who You Are: Analytical thinker with strong problem-solving skills and meticulous attention to detail. Effective communicator, able to articulate complex technical concepts to diverse audiences. Collaborative team player who thrives in a multicultural and multidisciplinary environment. Self-motivated, adaptable, and eager to learn new technologies and methodologies. Proactive in identifying areas for improvement and driving innovative solutions. The Team You ll Be A Part Of: You ll join a dynamic, inclusive team of physical design and ASIC implementation experts dedicated to developing world-class design flows and methodologies. Our team collaborates closely with IP development, CAD, and validation groups, sharing knowledge and driving best practices across the organization. We value open communication, continuous learning, and a passion for technical excellence, and we are committed to supporting each other s growth and success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Candidate must have completed 03-06 months of training in VLSI. Candidate must have knowledge about: VLSI - Design Verification VLSI - Physical Design VLSI - Hardware VLSI - Analog Circuit Analog (Memory Design/Layout) VLSI - DFT RTL

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy. Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&R IP blocks for Scan, MBIST and other test interfaces. Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing. Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet. Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs. Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations. Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types. Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues. Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs. Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting. Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow. Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory. Knowledge of LogicBIST with Test point insertion, X-blocking. Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements. Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug. Ability to perform volume diagnostics on the parts to isolate and improve the patterns. Requirements Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. OR masters degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design for Test. Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows. Prior experience working on IP level and SOC level DFT projects. Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc. Worked in full chip design or complex IP delivery in the area of DFT. Experience in post silicon debug, diagnosis and yield enhancements is a plus.

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR. Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently. Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence. Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs. Support and Development of advanced physical design methodologies and flows for complex semiconductor designs. Requirements Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. 4+ years of experience in physical design of ASICs Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure. Extensive experience with timing closure techniques, power optimization. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues. Experience in handling Partitions and blocks for size estimation, pin assignment, CTS. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration. Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power. Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF. Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks. Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues. Experience with formal verification for RTL to Netlist and Netlist to Netlist. Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.

Talent Acquisition Specialist – Semiconductor Hiring | Hyderabad | 0 – 6 Months Experience Education: MBA (HR or related) with Bachelor's in Electronics or related field About the Role: We are seeking a smart, energetic, and highly motivated Talent Acquisition Specialist to join our Semiconductor hiring team. This is an exciting opportunity for fresh graduates or early-career professionals who are passionate about recruitment and want to be part of building the next generation of semiconductor talent. The ideal candidate should have a strong interest in technology hiring, excellent communication skills, and a willingness to learn and grow in a fast-paced environment. Key Responsibilities: Support end-to-end recruitment for niche semiconductor roles (ASIC, SoC, RTL, DFT, AMS, etc.) Screen resumes and evaluate candidates based on job requirements and technical fit Conduct initial HR discussions and schedule interviews with technical panels Work closely with internal stakeholders to understand job descriptions and role expectations Build candidate pipelines through sourcing tools (LinkedIn, Naukri, etc.) Maintain and update applicant tracking systems and recruitment dashboards Assist in campus engagement and outreach programs where required Coordinate with onboarding and documentation teams for smooth candidate joining Requirements: MBA in Human Resources (preferred) with a Bachelor's degree in Electronics, ECE, or a related stream 0 to 6 months of experience in recruitment or internship experience in TA (preferred but not mandatory) Strong communication and interpersonal skills Interest or basic understanding of semiconductor industry roles is a plus Self-driven, organized, and eager to learn Proficiency in MS Office tools (Excel, Word, PPT) Why Join Us? Opportunity to work in a growing Semiconductor talent team Exposure to niche technical hiring Learn from experienced mentors and stakeholders Fast-track career development and learning programs If you're passionate about people and technology, and ready to kick-start your career in Talent Acquisition, we’d love to hear from you!

Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact Work with the team on Verilog RTL and scripted flow implementation of the specified Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design. Work with the team on Verilog testbench implementation of the specified verification tests for DFT features and use case. Work with the team on automation scripts intended for robustness of implementation quality and improvement of efficiency. Minimum Qualifications: Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 2 to 4 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Preferred Qualifications: VLSI circuit physical behaviors in silicon (electrical migration, temperature/voltage variation effects). Basic timing concepts, including setup and hold, metastability. Some EDA tools usage experience Strong verbal communication skills and ability to thrive in a dynamic environment Scripting/coding language: Tcl, Python, Perl, or c/c++. Why Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re "old" (36 years strong) and only about hardware, but we’re also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you can’t put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it). Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us!

The Common Hardware Group (CHG) at Cisco is responsible for delivering silicon, optics, and hardware platforms for core Switching, Routing, and Wireless products. As a part of this team, you will contribute to designing networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations globally. Cisco Silicon One is a groundbreaking silicon architecture that allows customers to utilize top-of-the-line silicon in various network environments. Join us in shaping innovative solutions by working on the design, development, and testing of complex ASICs. In this role, you will collaborate with the team on Verilog RTL and scripted flow implementation of Hardware Design-for-Test (DFT) features to support ATE, in-system test, debug, and diagnostics requirements. You will also be involved in Verilog testbench implementation for verification tests and automation scripts to enhance implementation quality and efficiency. **Minimum Qualifications:** - Bachelor's or Master's Degree in Electrical or Computer Engineering with a minimum of 2 years of experience. - Proficiency in DFT, test, and silicon engineering trends. - Familiarity with JTAG protocols, Scan and BIST architectures, ATPG, and EDA tools. - Verification skills in System Verilog Logic Equivalency checking and Test-timing validation. **Preferred Qualifications:** - Understanding of VLSI circuit physical behaviors in silicon. - Knowledge of timing concepts and EDA tools usage. - Strong verbal communication skills and adaptability in a dynamic environment. - Proficiency in scripting/coding languages such as Tcl, Python, Perl, or C/C++. Cisco is committed to embracing diversity, fostering innovation, and driving digital transformation. With a focus on inclusive teamwork and a culture of creativity, we encourage individuality and support continuous learning and growth. At Cisco, we value accountability, boldness, and diversity of thought. Join us in our journey to create a future where technology drives positive change and equality for all.,

The Common Hardware Group (CHG) at Cisco is responsible for delivering silicon, optics, and hardware platforms for the core Switching, Routing, and Wireless products. We design networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations worldwide. Cisco Silicon One is a unique silicon architecture that allows customers to utilize top-of-the-line silicon in TOR switches, web-scale data centers, and across various networks with a unified routing and switching portfolio. Join our team and contribute to shaping Cisco's innovative solutions by participating in the design, development, and testing of cutting-edge ASICs. As a member of our team, you will be involved in the Verilog RTL and scripted flow implementation of Hardware Design-for-Test (DFT) features supporting ATE, in-system test, debug, and diagnostics requirements. Additionally, you will collaborate on Verilog testbench implementation for verification tests related to DFT features and use cases. Your role will also include contributing to automation scripts aimed at enhancing implementation quality and efficiency. **Minimum Qualifications:** - Bachelor's or Master's Degree in Electrical or Computer Engineering with a minimum of 2 years of experience - Knowledge of the latest trends in DFT, test, and silicon engineering - Proficiency in JTAG protocols, Scan and BIST architectures, including memory BIST and boundary scan - Familiarity with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime - Verification skills encompass System Verilog Logic Equivalency checking and validating the Test-timing of designs **Preferred Qualifications:** - Understanding of VLSI circuit physical behaviors in silicon, including electrical migration and temperature/voltage effects - Knowledge of basic timing concepts like setup and hold, metastability - Experience with EDA tools - Strong verbal communication skills and ability to excel in a dynamic environment - Proficiency in scripting/coding languages like Tcl, Python, Perl, or C/C++ Cisco is a diverse and inclusive environment where individuality is celebrated, and collaborative teamwork drives meaningful change for an inclusive future. Embracing digital transformation, we assist our customers in implementing digital changes in their businesses, showcasing our expertise as both a hardware and software company. Our innovative network solutions adapt, predict, learn, and protect, setting us apart as a company that defies traditional categorization. At Cisco, we value accountability, boldness, and diversity of thought. We foster a culture of innovation, creativity, and learning from failures, all while promoting equality for all individuals. Our inclusive environment encourages employees to be themselves, whether it's through unique personal styles or a passion for technology and positive change. Join us at Cisco, where your individuality and dedication to excellence are celebrated.,

Skills: Strong technical foundation and proven hands-on experience in PCB design using industry-standard software. Deep understanding of various sensor technologies, Sensor building , signal conditioning, and their practical application in embedded systems or IoT devices. Proficiency in circuit simulation tools. Ability to guide students in conceptualizing, designing, fabricating (conceptually), and testing complete electronic hardware projects incorporating sensors and custom PCBs. Must be able to confidently explain and simplify complex electronics and hardware concepts for diverse age groups and academic levels. Excellent communication skills in English and Hindi (both verbal and written). Strong planning and time management abilities. Strong public speaking and presentation skills. Comfortable handling large groups and tailoring delivery methods to suit different institutions. Excellent stakeholder management handling clients, academic institutions, and internal teams Willingness to take up training responsibilities as required. Role & responsibilities Lead Training Sessions: Deliver engaging and practical trainings covering PCB Design, Sensor Designing & Integration , Hardware Prototyping & Testing across colleges, schools, and premier institutions . Mentorship & Team Training: Train, guide, and mentor junior trainers from PHN Technology, ensuring content and delivery consistency in PCB design and sensor systems. Content Development: Develop and continuously update training materials, live projects, case studies, and hands-on labs that demonstrate practical applications of PCB design and sensor technologies. Travel Readiness: Willingness and ability to travel extensively across India for conducting workshops and sessions as per schedule. Preferred candidate profile We are looking for a highly skilled professional with deep expertise in PCB design, diverse sensor technologies and sensor designing . The ideal candidate should have a minimum of 5+ years of relevant experience in teaching, corporate training, or industry roles. A strong command over communication (both verbal and written) in English and Hindi is essential, along with the ability to clearly explain and simplify complex concepts to learners across diverse age groups and academic levels. Candidates should possess excellent public speaking and presentation skills , and be comfortable delivering sessions to large groups while tailoring the content as per institutional needs.

Candidate will be responsible for building/maintaining highlyconfigurable and reusable IO Subsystems (Note: An IO Subsystem is alogic IP that processes the IO Pads/IO Ring information and requiredlogic to allow multiple on-chip peripherals to share the same IOs in aconfigurable manner) Job Description In your new role you will: Candidate will be responsible for building/maintaining highly configurable and reusable IO Subsystems (Note: An IO Subsystem is a logic IP that processes the IO Pads/IO Ring information and required logic to allow multiple on-chip peripherals to share the same IOs in a configurable manner) Candidate will be responsible for RTL design for integration of IO pads into SoC, building the required multiplexing logic and necessary power control signals integration. Strong fundamentals in DFT/Fault-grading and/or hands on experience. Sound & Practical Written and Verbal Communication Skills. Your Profile You are best equipped for this task if you have: Must have worked in ASIC Design flow, with ASIC experience of upto 5years. Must be strong in scripting using Perl/Python Must be familiar with RTL design for for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Experience: 3 6 Years Location: Pune Joining: Immediate Work Location / Mode of Work Hinjewadi / Work from office Key Responsibilities: Design and layout of multi layer PCBs for EV powertrain modules (inverters, BMS, DC DC converters, OBC, motor controllers) Collaborate with hardware/thermal engineers and cross-functional teams to optimize layout Create schematics, footprints, BOMs; ensure DFM/DFT and high-speed design compatibility Coordinate with PCB manufacturers for prototyping and compliance Ensure designs follow IPC standards and EMI/EMC considerations Required Skills: Proficiency in PCB design tools (Altium, OrCAD, Allegro, etc.) Experience in power electronics, signal integrity, thermal constraints Familiarity with EMI/EMC compliance and automotive design practices Xpetize is a technology solutions company, supporting customers in IoT, application and engineering services, data services, cybersecurity, cloud and social services. We are headquartered in Trivandrum with offices in Bengaluru, Pune, USA and Japan. We work tirelessly to help our customers across the globe since 2011 and relentlessly trying to grow our expertise across geographies. Our flagship Industry 4.0 product XPETICS, is a fully managed IIoT platform that lets customers securely connect and process IoT data at scale. We have a flexible and open work culture, lots of fun, flexi work hours, up skilling programs, medical insurance for family and parents and ensuring work life balance.e

BE/B.Tech in Electronics, Electrical, Telecommunication, or Instrumentation Key Competencies Required: Electronics control module and electrification product design Analog and sensor interface circuits Microcontroller / microprocessor-based designs Switch-mode and linear power supply design (Buck, Boost converters) EMI/EMC compliance and multilayer PCB design Familiarity with UART, I2C, SPI, RS485, CAN, Ethernet Simulation tools: Pspice, LTSPICE Design tools: Capture, Altium Board debugging tools: Logic analyzers, DSO Signal integrity tools: Hyperlynx, Cadence SI Role Expectations: Requirement analysis Schematic design & development Prototyping & testing Design documentation Lifecycle understanding (DFM/DFT, certifications)

Apply to this job We are looking for a highly skilled and experienced DFT Engineer to become part of our team. Our DFT Engineers will build efficient System on Chip (SoC) and IP for data center applications. This role offers the opportunity to work with industry-standard Siemens/Synopsys DFT EDA tools and IEEE standards (1149, 1500, 1687) while contributing to cutting-edge technology. This role includes developing and applying DFT strategies for complex mixed-signal integrated circuits (ICs), ensuring fault coverage and testability. ASIC Implementation, DFT Engineer Responsibilities Develop and implement DFT strategies for mixed-signal ICs, considering factors such as fault coverage, test time, and in-system test Ensure compliance with IEEE standards (1149, 1687) for DFT methodologies and test patterns Conduct fault simulation and coverage analysis to assess the effectiveness of DFT strategies and identify areas for improvement Generate high-quality test patterns using automated test pattern generation (ATPG) tools Verify the correctness of DFT implementation through simulation and hardware testing Collaborate with design/implementation teams to ensure that DFT requirements are met throughout the process Minimum Qualifications Bachelors degree in Electrical Engineering or Computer Engineering 6+ years of experience in DFT for mixed-signal ICs Understanding of DFT concepts, including scan insertion, BIST, and boundary scan In-depth knowledge of DFT EDA tools (Siemens/Synopsys) Familiarity with IEEE standards 1149, 1500, and 1687 Experience with fault simulation and coverage analysis tools Problem-solving and analytical skills Strong communication skills Experience of consistently working under your own initiative, seeking feedback and input where appropriate Proficiently use Siemens/Synopsys EDA tools for DFT-related tasks, including MBIST, scan insertion, and test pattern generation Preferred Qualifications Masters degree in Electrical Engineering or Computer Engineering 10+ years of experience in DFT strategies implementation and development for mixed signal ICs Experience with mixed-signal DFT methodologies Knowledge of scripting languages (e.g., Perl, Python) for automation Experience with hardware testing and debugging About Meta . Equal Employment Opportunity . Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form .

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Basic qualifications: Strong academic and technical background in electrical engineering. A Bachelor s degree in EE / Computer is required, and a Master s degree is preferred. 7 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! Required experience : Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less. Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level. Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production. Experience with Cadence and/or Synopsys physical design tools/flows. Familiarity and working knowledge of System Verilog/Verilog. Experience with DFT tools and techniques. Experience in working with IP vendors for both RTL and hard-mac blocks. Good scripting skills in python or Perl Preferred : Good knowledge of design for test (DFT), stuck-at and transition scan test insertion. Familiarity with DFT test coverage and debug. Familiarity with ECO methodologies and tools. Your base salary will be determined based on your experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Demonstrates ability to do PCB Layout designs of Multilayer boards up to 16 layers for Digital, Analog, PS and RF. Demonstrates proficiency on Mentor Graphics ECAD tools like Dxd , Expedition and Valor. Knowledge of PCB Layout design concepts for High speed, PS and RF layouts. Basic concepts of SI, PI and EMC Concepts to design robust layouts is expected. Knowledge about IPC-2221, IPC-610 standards and Class -C Drawing standards. Experience in writing Perl, VB/Python Scripting for Mentor tools is added advantage. Demonstrates basic knowledge of DFx ( fabrication , assembly and DFT) for PCB and PCBA. In Addition: Must be a Team player. Demonstrates proficiency in oral, written communications. Problem solving, innovation/creativity by proposing alternate solutions are expected. Qualification: B. E/B. TECH Electronics/Electrical Experience : 3 to 7 Years Demonstrates ability to do PCB Layout designs of Multilayer boards up to 16 layers for Digital, Analog, PS and RF. Demonstrates proficiency on Mentor Graphics ECAD tools like Dxd , Expedition and Valor. Knowledge of PCB Layout design concepts for High speed, PS and RF layouts. Basic concepts of SI, PI and EMC Concepts to design robust layouts is expected. Knowledge about IPC-2221, IPC-610 standards and Class -C Drawing standards. Experience in writing Perl, VB/Python Scripting for Mentor tools is added advantage. Demonstrates basic knowledge of DFx ( fabrication , assembly and DFT) for PCB and PCBA. In Addition: Must be a Team player. Demonstrates proficiency in oral, written communications. Problem solving, innovation/creativity by proposing alternate solutions are expected. Qualification: B. E/B. TECH Electronics/Electrical Experience : 3 to 7 Years

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI the next era of computing. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can address, and that matter to the world. This is our life s work, to amplify human creativity and intelligence. As an engineer of our Software Quality Assurance (QA) team, you will orchestrate the process of Software Quality for our CAD tools and flows. We develop and support flows for all of NVIDIAs semiconductor products. In addition, the CAD group also develops in-house tools in the area of Design for Test (DFT) using C++, Python, and TCL. You will work on infrastructure and software used to test our complex semiconductor devices. Below are some of the CAD teams activities. We are a diverse team, looking for someone who is not afraid of a challenge. If this is you, come join us today. What you will be doing: Providing hardware, software, and lab support for testing and validation processes. Architecting highly automated and customizable Software Quality processes for design flows using software engineering with modular design and object-oriented techniques. Crafting feature test plans, identifying, and writing test cases based on user requirements, and providing automation of testing. Maintaining regression testing frameworks and developing test reporting mechanisms Performing code reviews, static analysis, and dynamic testing. Continuously delivering high-quality, bug-free Software Applications. Working closely with our diverse team members on flows to provide DFT and methodologies for industry-leading chip designs. Supporting the development of tools using C++/Python/TCL. Working cross-functionally with DFT Methodology, Implementation, and design teams with important DFT tools support. What we need to see: A BS or MS in Electrical Engineering, Computer Science, or Computer Engineering with at least 4+ years of relevant work experience in Software QA role. Knowledge of different software testing techniques, code reviews, code coverage, unit and flow testing, use case testing, random, white, and black box testing. Experience with test management tools such as TestRail or Zephyr. Familiarity with CI/CD tools like Jenkins and GitLab. Strong GenAI, LLM, AI Code Generation skills desirable. Good software design, algorithms, programming and scripting skills in Python, Tcl, or C++ desired. Experience with defect tracking tools such as JIRA. Experience in providing lab software and hardware Ways to stand out from the crowd: Knowledge or experience with DFT is a plus. Knowledge of BDD processes is desirable. Verilog and ASIC design principles, including knowledge of logic cells is a plus. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If youre creative and autonomous, we want to hear from you! #LI-Hybrid

We are seeking a highly experienced Senior Physical Design Engineer with 8+ years of experience in block-level and full-chip physical implementation. The candidate should be proficient in physical design flows and methodologies for advanced technology nodes. Key Responsibilities: Drive physical implementation from RTL to GDSII (floorplanning, placement, CTS, routing) Perform timing analysis, congestion analysis, and physical verification (DRC/LVS) Optimize for performance, power, and area (PPA) Collaborate closely with RTL, STA, DFT, and package teams Own signoff checks (IR drop, EM, Antenna, Crosstalk, etc.) Support tape-out and silicon validation activities Requirements: 8+ years of experience in physical design implementation and signoff Strong hands-on experience with tools like ICC2, Innovus, Primetime, RedHawk, Calibre Solid understanding of timing closure, IR/EM analysis, and power optimization Experience with advanced nodes (7nm, 5nm, etc.) is a plus Good scripting skills (TCL, Perl, Python) for automation Strong communication and teamwork skills

Design and development of processor L2 , L3, Non cacheable units and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. . Required education Master's Degree Preferred education High School Diploma/GED Required technical and professional expertise 8 to 15 years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design,

Key Responsibilities: Interpret schematics, layouts, BOMs, and datasheets to understand components, their packaging, and PCB requirements. Create and maintain schematic symbols and footprints per: o ANSI Y32.2 / IEEE 315 (US schematic symbols) o IEC 60617 (European standards) o IPC-7351 (land pattern and footprint creation) Design high-quality multi-layer PCBs using Cadence Allegro, Altium Designer, PADS supporting: o Auto-routing o Team collaboration o High-speed/serial signal handling Optimize designs for DFM, DFT, DFA, with emphasis on cost, reliability, and layer reduction. Perform stack-up selection, impedance control, and use constraint managers effectively. Apply EMI/EMC-compliant layout practices and design techniques. Collaborate with mechanical and hardware teams on thermal, mechanical, and signal considerations. Understand PCB materials, fabrication processes, soldering standards, and assembly techniques. Generate fabrication outputs including Gerbers, ODB++, drill files, BOMs, Pick & Place, and mechanical drawings. Conduct thorough reviews for design quality, manufacturability, and compliance to standards. - Required Skills B.Tech in electronics engineering with 5+ years of hands-on PCB layout experience including symbol/footprint creation. Strong understanding of DFM/DFT/DFA, PCB stack-up, HDI, back drilling, and high-volume production optimization. Proficiency with EDA tools: Cadence Allegro, Altium Designer, PADS. Knowledge in EMI/EMC standards and design practices. Familiar with different component manufacturers, packages, specifications, and selection criteria. Strong ability to read datasheets, interpret component specs, and assess mounting/thermal requirements. knowledge of IPC standards: IPC-2221, IPC-7351, IPC-610, etc. Familiar with assembly guidelines, soldering standards, PCB materials, and manufacturing processes. Experience working under AS9100 quality standards and procedure

Job description: Job Description Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client ͏ Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project ͏ Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc)2. Self-development Skill test for next level clearance on Trend Nxt ͏ ͏ Mandatory Skills: VLSI Design For Testability - DFT . Experience: 1-3 Years . Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

Mission principale : Industrialisation des Moyens de Test Mission 1 : Assurer l’industrialisation des nouvelles solutions de test Rédiger les cahiers des charges selon les spécifications awardés (Temps de test, budget, délai de livraison, Capabilité et R&R) Garantir le bon déroulement des différentes phases du projet dans les parties relatives au Test Développer les moyens de test (Hardware et Software) Contribuer dans les échanges techniques avec le client dans les sujets relatifs au test en collaboration avec le chef de projet. Assurer la réception, validation et qualification des moyens de test Elaborer les couvertures de test Mission 2 : Chiffrer les nouvelles solutions de test Faire l’analyse DFT et assurer une bonne testabilité du produit en collaboration avec l’équipe projet et le client Participer aux choix techniques pour les nouvelles stratégies de test Chiffrer les moyens de test et les potentielles évolutions. Mission 3 : Assurer une productivité et efficience en continu des moyens de test Proposer et concrétiser en continu des pistes d’optimisation des solutions de test Optimiser les temps de test. Améliorer en continu la couverture et la fiabilité des testeurs. Assurer une veille technologique par rapport aux stratégies et moyens de test et de contrôle automatisés. Mission 4 : Assurer un entretien optimal et une efficience de fonctionnement des moyens de test sous sa responsabilité Supporter et former les techniciens Support Test Garantir le fonctionnement des moyens de test selon les spécifications définies depuis le lancement du projet Participer à la validation des interventions préventives sur les moyens de test Participer à la maintenance corrective des testeurs Niveau et spécialité requis : Ingénieur en électronique, électromécanique, mécatronique ou informatique industrielle Expérience professionnelle: 5 ans dans un milieu industriel dans le domaine du test des cartes électroniques.

Expertise / Skills: Footprint creation Layout, high-speed layout,multi-layer board design Orcad (must) Allegro (must) Job Description: Guide and provide technical support to juniors for Project development. Experience in High-speed design and Analog design routing. Experience with PCB Layout design up to 4 layers is preferred. Conduct hardware design in DFM, DFA, and DFT format Should be open to working in a challenging environment with minimal supervision Design and Develop Multilayer PCB Basic knowledge of IPC Standards PCB Design as per the EMI / EMC standards Strong Skills for Library development, footprint creation, and Layout in software like Orcad (must), Altium, Allegro (must), Eagle, Mentor Graphics, etc Demonstrate robust design principles in the execution Continuously upgrade skills and knowledge of self Signal Integrity and Power Integrity. Knowledge of protocols including RS232, RS485, SPI, USB, CAN, ZigBee, Experience in Power supply- SMPS design, DC/DC converter, LDOs

Role: PCB Design & Development: Design and develop RF/Microwave and mixed-signal PCBs for high-frequency applications, including phased arrays and wireless communication systems. Implement repeated circuit designs to ensure consistency and reliability in large-scale deployments. Tool Utilization & Analysis: Utilize Altium Designer to create schematics, layouts, and manufacturing documentation. Perform signal integrity, power integrity, and electromagnetic compatibility (EMC) analyses to optimize PCB performance. Cross-Functional Collaboration: Collaborate with RF, hardware, and software teams to integrate PCB designs into larger system architectures. Work with vendors and fabrication houses to ensure designs meet DFM (Design for Manufacturability) and DFT (Design for Testability) requirements. Required Qualifications Bachelors degree in Electronics and communication . Strong experience in RF and mixed-signal PCB design, including impedance control and high-frequency layout techniques. Proficiency with Altium Designer (or similar PCB design tools). Knowledge of phased array design, including beamforming and antenna integration. Experience with repeated circuit design methodologies for high-volume production. Understanding of RF circuit design principles (e.g., transmission lines, filters, amplifiers, matching networks). Familiarity with simulation tools for RF and PCB analysis (e.g., HFSS, ADS, CST, or similar). Preferred Qualifications Experience with multi-layer PCB stack-ups and mixed-signal isolation techniques. Knowledge of RF packaging, shielding, and thermal management. Previous experience with antenna design and RF front-end modules. Familiarity with manufacturing and assembly processes for RF PCBs. Core Competencies Effective written and verbal communication skills. Ability to explain complex technical concepts to non-technical stakeholders. Strong teamwork and collaboration skills. Ability to work independently and manage multiple projects simultaneously. Excellent organizational skills, attention to detail, and a systems-thinking approach. Willingness to assist teammates with larger engineering tasks and assume technical responsibility when required. Role & responsibilities Preferred candidate profile