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Smart Soc Solutions
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Design Verification Engineer Ã¢â‚¬â€œ Position 3

Design Verification Engineer Ã¢â‚¬â€œ Position 3

Smart Soc Solutions

5 - 10 years

6 - 10 Lacs

Bengaluru

Posted:2 days ago| Platform:

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Skills Required

soc verification design verification system verilog software testing dft jtag c++ circuit soc scanning electrical engineering vhdl rtl design axi fpga rtl coding ahb perl asic sv ip ovm rtl uvm cdp verilog asic design gdp mbist vlsi pcie

Work Mode

Work from Office

Job Type

Full Time

Job Description

Experience: 5 to 12 years
Location: Bangalore
:
We are seeking a highly experienced Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong foundation in SystemVerilog (SV) and Universal Verification Methodology (UVM). In addition to standard verification skills, this role requires expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST (Memory Built-In Self-Test), SCAN, PG (Pattern Generator), and PM (Pattern Memory). Key Responsibilities:

IP and SOC Verification

Perform comprehensive IP and SOC verification to ensure the reliability and functionality of integrated circuits.

SystemVerilog (SV) and UVM Proficiency

Demonstrate a strong understanding of SystemVerilog and Universal Verification Methodology for efficient verification processes.

CDP, GDP, DFT DV Expertise

Possess expertise in Compressed Data Pattern (CDP) and Generic Data Pattern (GDP) methodologies.

Proficiency in Design for Test in Design Verification (DFT DV) techniques, including JTAG, MBIST, SCAN, PG, and PM.

Qualifications:

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

5 to 12 years of relevant industry experience in IP and SOC verification.

Strong knowledge of SystemVerilog (SV) and Universal Verification Methodology (UVM).

Expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST, SCAN, PG, and PM.

If you are a talented Design Verification Engineer with a deep understanding of IP and SOC verification, as well as specialized expertise in CDP, GDP, and DFT DV methodologies, we encourage you to apply. Join our dynamic team and contribute to the advancement of cutting-edge technology. Job Category VLSI (Silicon engineering)
Job Type Full Time
Job Location IndiaBangalore

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Design Verification Engineer Ã¢â‚¬â€œ Position 3