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Smart Soc Solutions
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SR. DFT ENGINEER

SR. DFT ENGINEER

Smart Soc Solutions

3 - 8 years

6 - 10 Lacs

Noida Hyderabad Bengaluru

Posted:1 week ago| Platform:

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Skills Required

atpg mentoring cadence verilog dft jtag c++ soc scanning simulation bist digital design vhdl rtl design fpga drc linux rtl coding debugging perl system verilog tcl synthesis asic sta python c scan insertion rtl uvm silicon mbist vlsi

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Work from Office

Job Type

Full Time

Job Description

SR. DFT ENGINEERSmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience-

3 – 10year’s experience in DFT

Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan.

DFT logic integration and verification.

Experience in debugging low coverage and DRC fixes

Gate Level ATPG simulation with and without timing.

Pattern generation, verification, and delivery to ATE team.

Post silicon debug and support on failing patterns.

Good experience with tools from Mentor/Synopsis/Cadence.

LBIST experience is plus.

DFT mode STA and timing closure support.

Familiarity with Verilog and RTL simulation

Job Category VLSI (Silicon engineering)
Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

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SR. DFT ENGINEER