1063 Dft Jobs - Page 5

We are seeking a skilled PCB Design Engineer with 4 to 7 years of hands-on experience in Cadence Allegro tools. The selected candidate will be responsible for end-to-end PCB design, from schematic translation to manufacturing support. Key Responsibilities: Design complex multilayer PCBs using Cadence Allegro and related tools. Collaborate with electrical engineers to convert schematics into optimized PCB layouts. Define board stack-ups, impedance control, and layout constraints. Perform signal integrity (SI), power integrity (PI), and DFA/DFT/DFM analysis. Generate and review fabrication and assembly documentation (Gerber files, BOMs, pick & place files, assembly drawings). Create and maintain PCB design libraries. Ensure compliance with regulatory standards (e.g., IPC, RoHS, UL). Required Skills and Qualifications: Proficiency in PCB CAD tools, especially Cadence Allegro. Strong understanding of high-speed design principles and layout best practices. Familiarity with EMI/EMC considerations and thermal management. Experience with HDI, mixed-signal, and RF PCB designs. Knowledge of IPC standards (e.g., IPC-2221, IPC-7351). Strong attention to detail and analytical skills. Experience with DFx (Design for Excellence) methodologies.

Job Summary: The Quality Engineer is responsible for ensuring that all FRP equipment and components meet quality standards and customer specifications. The role involves quality planning, inspection, testing, documentation, and supporting continuous improvement initiatives in the manufacturing process. Key Responsibilities: Inspect incoming raw materials (resins, glass fiber, etc.) and ensure conformance to specifications. Monitor in-process and final inspections for FRP tanks, scrubbers, pipelines, and related equipment. Conduct dimensional checks, visual inspections, hardness tests, lamination thickness measurements, and leak tests. Review and interpret technical drawings, standards (ASTM, ASME, IS), and customer requirements. Prepare and maintain QA/QC documents like inspection reports, material test certificates, and compliance records. Identify root causes of quality issues and implement corrective and preventive actions (CAPA). Assist in preparing Quality Assurance Plans (QAP), Inspection Test Plans (ITP), and Standard Operating Procedures (SOPs). Interface with third-party inspectors and customers during stage and final inspections. Support internal and external audits (ISO 9001:2015 or similar). Promote and ensure safety and cleanliness in quality control areas. Qualifications & Skills: Education: Diploma / B.E. / B.Tech in Mechanical / Chemical / Production Engineering Experience: 2–5 years of QA/QC experience in FRP equipment or chemical processing industry Technical Knowledge: Good understanding of FRP/GRP fabrication standards and testing methods Familiarity with IS/ASTM/DIN standards applicable to FRP and process equipment Hands-on experience with measuring instruments like Vernier, Micrometer, DFT gauge, etc. Software: MS Office, AutoCAD (basic), ERP systems Key Skills: Strong attention to detail and analytical skills Good documentation and communication ability Knowledge of quality tools like 5 Why, Root Cause Analysis, Fishbone Diagram, etc. Job Type: Full-time Pay: ₹10,693.75 - ₹37,697.78 per month Work Location: In person

Location: Hybrid Job Type: Full-Time Posted Date: 6/30/2025 About The Role Job Overview: We are seeking a Senior Physical Design Engineer with strong expertise in Netlist-to-GDSII implementation and experience working on advanced submicron technology nodes. The role demands in-depth knowledge of industry-standard EDA tools and a solid grasp of timing closure and physical verification processes. Key Responsibilities:  Drive full Netlist-to-GDSII flow: floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off.  Perform Static Timing Analysis (STA) and ensure timing closure across all design corners.  Execute power integrity and physical verification checks (LVS, DRC).  Collaborate closely with cross-functional teams (RTL, STA, packaging, and DFT).  Handle complex designs on 28nm and below technology nodes. Must-Have Skills  Strong hands-on experience with: o Synopsys/Cadence tools: Innovus, ICC2, Primetime, PT-PX, Calibre o Physical Design Methodologies: Floorplanning, Placement, CTS, Routing, STA  Proficiency in: o Timing constraints and closure o Tcl/Tk/Perl scripting o Submicron nodes (28nm and below) Good to Have  Familiarity with Fusion Compiler  Broader understanding of signal and power integrity  Experience in workflow automation and tool scripting If you are interested in this role, please mail your resume to hemanth@neualto.com or spoorthy@neualto.com.

Strong understanding of DFX concepts: DFT, DFM, DFA, DFR Experience in semiconductor, electronic hardware, or embedded product development Proficiency in DFT/DFM tools and methodologies FMEA, FTA, reliability analysis, and root cause problem solving

Company: Eteros Technologies India Private Limited Eteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad • Our world-wide customers are amongst The Who's who in the semiconductor industry. Eteros works not only with some of the top 20 semiconductor startups in the world but boasts of customers who are among the most respected publicly traded semiconductor companies. • Eteros engineers work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5G domains. Eteros engineers work with some of the brightest, innovative and successful engineers and leaders around the world. A one-of-a-kind opportunity where young Eteros engineers showcase their ability and experience world-wide from day 1 while learning from some of the world's most well-respected companies. • We are not your traditional design services company offering staff augmentation. Eteros engineers are treated as an integral part of the customer team and routinely are responsible for turnkey, end-to-end ownership and delivery, whether it is Implementation, Digital and Mixed Signal Verification, DFT or Analog Design and Layout. Eteros and our engineers work closely with our customers to define and set methodologies and design flows. • Eteros invests in our engineers. Our engineers are continuously learning, on and off the job. They are able to grow the breadth and depth of knowledge. We believe in preparing our employees for the fast-track in career development as well as longevity ----------------------------------------------------------------------------- Job Title/Role: DFT - Senior Engineer/Lead Location : Bangalore/Hyderabad/Ahmedabad Experience Level : 4+ Years Industry : Semiconductors Employment Type : Full-time Job Functions : Engineering ----------------------------------------------------------------------------- Summary Minimum 4 yrs+ experience in DFT implementation Must have worked on Scan Insertion, MBiST, ATPG, Simulations Must have experience with Synopsys DFT tools & Flows Experience in DFT timing closure preferred Experience in multi-die HBM/Memory testing with Synopsys tools preferred Work hands-on on critical tasks of DFT implementation Own the DFT implementation flows, methodologies and execution of SoCs Experience Experience in all phases of the DFT pre and post-Si for large SoCs Implement DFT of SoC/Full-chip-level and/or high-speed cores/blocks Experience in high-speed, low-power, mixed-signal SoC’s is a plus Preferably worked on 5nm/7nm/12nm/14nm/16nm nodes at the major foundries Experience in developing DFT architecture, Test-plan, implementation methodologies Experience in scan insertion, memory-BIST, JTAG/IJTAG, CTL, IEEE 1149.1/1500 wrappers, BSCAN, Compression, ATPG, Simulations, post-Si testing/debug Experience in manual test-point insertion, improve coverage targets, high-compression Experience in hierarchical ATPG, OCC/OPCG, power-aware scan/ATPG methodologies Experience in test-mode constraints generation and test-mode timing closure Experience in patter generation for foundry, post-Si support/debug Thorough understanding of digital design, timing analysis, and physical design process EDA Tools: Cadence (Encounter-Test, Modus-DFT, Tempus, Conformal), Mentor (Tessent tool suite), Synopsys (DFTC, Tetramax, TestMax-DFT, SMS, PTSI) Requirements • BTech/MTech/PhD with in Electrical or Computer engineering • 4-8years of hands-on experience with DFT and test flow with commercial EDA tools for large and complex SOCs • Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST • Experience with Cadence & Synopsys DFT tools is required. • Strong programming skills in Perl/TCL/C++ and shell scripting is required • Must be able to solve complex problems and independently drive tasks to completion in a timely manner. • Be able to work under limited supervision and take complete accountability. • Excellent written and verbal communication skills What's in it for you • Work on leading edge technologies • An opportunity for career development and growth • Competitive compensation • Medical Benefits and more

Key Responsibilities: Design and develop custom memory circuits such as: SRAM (register file, cache), ROM, eDRAM, MRAM, RRAM, or embedded Flash. Work across the entire memory development cycle: from specification, circuit design, pre/post-layout simulations, to silicon validation. Design key components including bitcells, sense amplifiers, wordline/bitline drivers, precharge, write drivers, and redundancy logic. Optimize memory circuits for power, performance, area (PPA), yield, and reliability. Collaborate with layout engineers to ensure quality layout and adherence to design constraints. Perform exhaustive corner simulations (PVT, Monte Carlo, mismatch, IR drop, etc.). Interface with technology, verification, DFT, product engineering, and test teams to support silicon bring-up and yield improvement. Contribute to design methodology improvements and automation. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in Electronics or Electrical Engineering. 3–10 years of hands-on experience in memory circuit design (SRAM, ROM, or other embedded memories). Strong knowledge of CMOS circuit design, device physics, and transistor-level analysis. Proficiency with EDA tools such as Cadence Virtuoso, Spectre, HSPICE, FastSPICE, and Calibre. Experience with advanced technology nodes (preferably 16nm and below, including FinFET). Solid understanding of yield, variation, IR drop, and reliability considerations in memory design. Familiarity with scripting languages (e.g., Python, Perl, TCL) for automation.

Key Responsibilities: Define and implement DFT architecture for SoCs and IPs. Develop and integrate scan chains, ATPG, MBIST, LBIST, and boundary scan (JTAG). Work with RTL designers to insert DFT logic and resolve DRC violations. Generate and validate test patterns using tools such as TetraMAX , FastScan , DFT Advisor , etc. Analyze and improve fault coverage and test time reduction. Support silicon bring-up and post-silicon validation of test features. Debug and resolve DFT-related issues during synthesis, simulation, and verification. Collaborate with physical design and verification teams to ensure DFT compliance throughout the flow. Required Skills: 3–10 years of hands-on experience in DFT implementation. Strong knowledge of scan insertion, ATPG, MBIST, LBIST, and boundary scan. Experience with DFT tools: Synopsys DFT Compiler , TetraMAX , Mentor Tessent , FastScan , DFTMAX , etc. Proficient in scripting (TCL, Perl, Python, Shell) for automation. Familiar with RTL coding (Verilog/SystemVerilog) and synthesis flow. Good understanding of timing constraints, STA, and low-power design considerations in DFT. Experience in handling gate-level simulations and testbench development.

Key Responsibilities: Drive block-level and/or full-chip physical design from RTL to GDSII. Floorplanning, placement, clock tree synthesis (CTS), and routing. Work on static timing analysis (STA) and timing closure. Run and debug physical verification (LVS/DRC/ERC) and power integrity checks (IR Drop/EM). Collaborate with RTL, DFT, synthesis, verification, and packaging teams. Ownership of PPA (Power, Performance, Area) targets and meeting timing goals. Participate in multiple tape-outs and manage block-level signoff closure. Automate and optimize flows using Tcl, Perl, Python, or shell scripting. Keep up-to-date with the latest EDA tools and technology trends. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related field. 4–10 years of experience in physical design with successful tape-outs. Strong expertise in Synopsys/Cadence tools (ICC2, Fusion Compiler, Innovus, PrimeTime, etc.). Deep understanding of digital design concepts, timing, and power trade-offs. Hands-on experience in advanced technology nodes (16nm and below preferred). Experience with scripting languages (Tcl, Python, Perl, Shell). Familiarity with ECO flows, DFT insertion, and low-power design techniques (UPF/CPF). Knowledge of signal and power integrity issues (IR/EM) is a plus.

Key Responsibilities: Develop and execute verification test plans based on design specifications. Create constrained-random and directed testbenches using SystemVerilog/UVM. Develop functional coverage models and drive coverage closure. Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues. Perform block-level and/or SoC-level verification. Integrate and verify 3rd-party IPs and custom IPs in subsystem and full-chip environments. Collaborate with RTL, DFT, DV, firmware, and physical design teams. Run regression simulations and ensure verification quality through coverage metrics. Automate verification flows and improve efficiency using scripting languages. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related discipline. 4–10 years of experience in digital design verification. Strong knowledge of SystemVerilog and UVM methodology. Good understanding of digital design concepts, RTL, and timing. Experience in using simulators like VCS, Incisive/Xcelium, Questa, etc. Hands-on experience with code and functional coverage, assertions, and checkers. Exposure to industry-standard protocols (AXI, AHB, I2C, SPI, PCIe, DDR, etc.). Experience in debugging RTL issues using waveform viewers (e.g., DVE, SimVision). Strong scripting skills in Python, Perl, Shell, or Make.

Job Title: PCB Designer Job Description: We are seeking a skilled PCB Designer to develop and layout printed circuit boards for electronic products. Responsibilities include schematic capture, PCB layout using design software (such as Altium, Eagle, or KiCAD), component placement, routing, and generating fabrication and assembly files. The ideal candidate should have knowledge of industry standards, DFM/DFT practices, and basic understanding of electronic circuits. Key Skills: PCB layout, schematic design, CAD tools, Gerber file generation, electronics basics.

Position Summary: We are seeking a 3D Product Design Engineer with strong expertise in enclosure design for consumer electronics, IoT devices, or industrial products. The role focuses on creating plastic and metal enclosures from concept to production, ensuring both aesthetic appeal and functional integrity. Key Responsibilities: Design 3D models of enclosures for electronic products using CAD software (SolidWorks / Creo / Fusion 360 / CATIA). Develop designs for plastic injection molding, sheet metal fabrication, die casting, and CNC parts . Collaborate with cross-functional teams including electronics, PCB, mechanical, and industrial design teams . Prepare 2D drawings with GD&T and manufacturing documentation for tooling and production. Conduct DFM (Design for Manufacturing) and DFT (Design for Tooling) reviews. Work closely with vendors and suppliers to optimize design for cost, manufacturability, and assembly. Run prototype validations , fitment tests, and enclosure stress simulations (if required). Implement IP-rated sealing, thermal management, and EMC shielding considerations where applicable. Ensure product designs meet aesthetic, ergonomic, mechanical, and functional requirements . Maintain version control, BOMs, and design documentation throughout product life cycles. Required Skills & Qualifications: Bachelor’s Degree in Mechanical Engineering, Product Design, or related field . 1+ years of experience in 3D product and enclosure design (plastics and metals). Proficiency in SolidWorks, Creo, Fusion 360, or equivalent 3D CAD tools . Knowledge of manufacturing processes : injection molding, sheet metal, CNC, and die casting. Strong understanding of GD&T (Geometric Dimensioning and Tolerancing) . Experience in DFM and DFA (Design for Manufacturing & Assembly). Familiarity with IP ratings, EMC shielding, and thermal management in product enclosures. Ability to communicate with toolmakers, vendors, and cross-disciplinary teams . Problem-solving mindset with attention to detail and quality . Experience in prototyping techniques (3D printing, CNC, etc.) is a plus. Preferred Qualifications: Experience in consumer electronics, IoT devices, medical devices, or automotive enclosures . Knowledge of simulation tools (FEA, thermal analysis, etc.) is a plus. Exposure to UX-focused design iterations and collaboration with industrial designers. Job Types: Part-time, Internship Contract length: 12 months Pay: From ₹118,284.34 per year Expected hours: 30 per week Schedule: Day shift Work Location: In person

Job Summary We are seeking a detail-oriented and innovative Electronics Hardware Engineer to design, develop, and test cutting-edge electronic systems and products. The ideal candidate will be responsible for schematic design, PCB layout, prototyping, testing, and hardware validation across the full product development lifecycle. You will work closely with cross-functional teams including software, mechanical, and manufacturing engineers. Key Responsibilities Design and develop analog and digital circuits based on project requirements. Create schematics and PCB layouts using tools such as Altium Designer, KiCAD, Eagle, or OrCAD. Select and source appropriate electronic components based on performance, cost, and availability. Build and test prototypes , and iterate based on performance and reliability testing. Conduct circuit simulations and signal integrity analysis. Work with firmware/software teams to ensure proper hardware-software integration. Perform DFT (Design for Test) and DFM (Design for Manufacturing) analysis. Collaborate with production teams to bring designs to mass production. Document hardware specifications, test procedures, and design decisions. Troubleshoot hardware failures and support debugging in lab and field environments. Stay current with emerging technologies and regulatory standards (e.g., CE, FCC, RoHS, EMC/EMI). Qualifications Required: Bachelor’s or Master’s degree in Electronics Engineering , Electrical Engineering , or related field. Strong understanding of analog/digital electronics , microcontrollers , power supplies , and communication interfaces (I2C, SPI, UART, CAN, etc.). Experience in schematic capture and multi-layer PCB design . Hands-on experience with oscilloscopes, multimeters , and lab testing tools . Familiarity with circuit simulation tools (e.g., LTSpice, PSpice). Proficiency in hardware debugging and root cause analysis. Preferred: Experience with embedded systems , RF design , or IoT hardware . Knowledge of compliance testing (EMC/EMI, safety standards). Exposure to automated test frameworks or hardware validation scripting . Soft Skills Strong analytical and problem-solving abilities Excellent communication and teamwork skills Ability to manage multiple projects and meet deadlines Passion for technology and continuous learning Job Type: Full-time Pay: From ₹8,000.00 per month Ability to commute/relocate: Madurai, Tamil Nadu: Reliably commute or planning to relocate before starting work (Preferred) Education: Bachelor's (Required)

Change the world. Love your job. The Validation Engineers at Texas Instruments are powered by a passion for continual improvement. Our solutions make a real difference and yours will, too. We make the semiconductor product design process easier and faster, which helps our customers succeed in today's fast-paced marketplace. Job Description: We are seeking a skilled and experienced Validation Engineer to take ownership of the validation function for our IC projects. The successful candidate will be responsible for designing and implementing comprehensive validation plans, developing validation hardware and software, automating test setups, and ensuring the overall quality of silicon sign-off for production release. Key Responsibilities: Lead Validation Efforts: Design and execute hands-on validation plans for automotive IC projects, including hardware and software development for validation and automation setups. Silicon Debugging: Perform silicon debugging to identify and resolve issues, ensuring production-grade quality for silicon sign-off. EMI/EMC Testing: Conduct in-house EMI/EMC tests and coordinate with external certification bodies for testing and approval. Cross-Functional Collaboration: Work closely with the Design and DV (Design Verification) teams pre- and post-PG to ensure closure on DFT (Design for Test), validation plans, and specifications. Collaborate with the Test team to correlate validation and test results, ensuring optimal fault coverage (FT) and a high-quality, cost-effective build. Partner with the Product Engineering team to execute all IC qualification requirements and oversee release to production. Project Management Support: Collaborate with Program Managers to ensure the project remains on track with respect to budget and schedule commitments. Participating in APPIT: actively plan and contribute to continues improvement of Automation Process Package IP and Test. Mentoring Junior Engineers : Mentor and guide new college graduate engineers (>2 NCGs), helping them develop skills in validation and ensuring their successful integration to the team QUALIFICATIONS Job Qualifications: Proven experience in silicon validation, including hands-on development of validation hardware, software, and test automation. Strong understanding of EMI/EMC testing and debugging, including experience coordinating with external certification houses. Experience working in cross-functional teams, including Design, DV, Test, and Product Engineering teams. Proven ability to mentor and guide junior engineers. Experience in contributing to APPIT and paper presentation skills Solid knowledge of DFT principles, silicon debug methodologies, and IC qualification processes. ABOUT US Why TI? Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. About Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com. Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. If you are interested in this position, please apply to this requisition. TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment. JOB INFO Job Identification 240006GS Job Category Engineering - Product Dev Posting Date 07/19/2025, 12:31 PM Degree Level Bachelor's Degree Locations BAN4 2,3rd and 4th Floors, Bangalore, 560093, IN ECL/GTC Required Yes

Meta is hiring talented individuals to join our Infrastructure organization as ASIC Frontend Implementation Engineers (RDC/CDC). In this role, you will play a critical part in designing and developing efficient System on Chip (SoC) and IP for data center applications. As an ASIC Frontend Implementation Engineer, your primary focus will be on the front-end implementation process and static verification tools, transforming RTL designs into optimized netlists. You will utilize your expertise in RTL Lint, CDC analysis, timing constraints, and synthesis to ensure seamless integration of various components to build efficient System on Chip (SoC) and IP for data center applications.By joining our team, you'll have the opportunity to contribute to the development of cutting-edge technology that powers Meta's infrastructure. ASIC Engineer, Frontend Implementation RDC/CDC Responsibilities: Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power Developing Automation scripts and Methodology for all Front End (FE)-tools including (Lint, CDC, RDC,) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in static verification tools Experience with Lint, Clock Domain & Reset Domain crossing Knowledge of SOC Integration (Clocking, Reset, PLL, etc) Knowledge of front-end ASIC flows Experience with RTL design using SystemVerilog or other HDL Successful candidates must remain in role in the same team in India for a minimum period of 24 months before being eligible for transfer to another role, team or location Preferred Qualifications: Scripting and programming experience using Perl/Python, TCL, and Make Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Experience with SOC Design Integration and Front-End Implementation Experience with developing structural rule based checks for RTL & Netlist Experience with Netlist-CDC Analysis and improving MTBF Knowledge of Timing/physical libraries, SRAM Memories About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As an ideal candidate for the ASIC Digital Design Engineer, Senior role, you are a highly motivated and innovative individual with a deep understanding of ASIC development flow. You possess a strong theoretical and practical background in high-speed serializer and data recovery circuits. You are someone who thrives in dynamic environments and embraces the challenges that come with constant technological changes. You are self-motivated, proactive, and able to balance good design quality with tight deadlines. Your excellent communication skills enable you to interact seamlessly with different design groups and customer support teams. You are known for your ability to resolve issues creatively and exercise independent judgment in selecting methods and techniques to obtain solutions. You are a team player who can produce excellent results both as an individual and as part of a team. What You’ll Be Doing: Supporting development and verification of digital designs for next-generation NRZ and PAM-based SerDes products. Setting up and Running lint/cdc/rdc checks and synthesis flow. Working with Verilog and VCS to ensure design accuracy. Defining synthesis design constraints and resolving STA issues. Collaborating with mixed-signal engineers to deliver high-end mixed-signal designs from specification development to functional and performance tests. Setting up flows/process for quality checks, release management for different front-end flows. Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry. Enhancing the performance, power, and size efficiency of our silicon IP offerings. Enabling rapid market entry for differentiated products with reduced risk. Driving innovation in high-speed digital design and data recovery circuits. Supporting the creation of high-performance silicon chips and software content. Collaborating with a world-class team to solve complex design challenges. What You’ll Need: BSEE or MSEE with a minimum of 4 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience in coding, verifying verilog and system verilog design. Experience of working with minimum supervision and owning and delivering for Front end activities in IP/SOC Experience of leading technically for Front end activities. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams. Self-motivated and proactive, with a strong attention to detail. A creative problem-solver who can think independently. Capable of working under tight deadlines while maintaining high-quality standards. A team player who can contribute effectively both individually and collaboratively. The Team You’ll Be A Part Of: Join our highly experienced mixed-signal design and verification team, where you will work alongside experts in digital and mixed-signal engineering. Our team is dedicated to developing innovative solutions for the next generation of high-speed SerDes products, providing continuous training and opportunities for growth. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Design and develop high-efficiency LED drivers. Work with both AC and DC circuits to ensure drivers meet industry standards for performance, safety, and reliability. Design and develop printed circuit boards (PCBs) for LED driver systems, ensuring proper layout, signal integrity, and thermal management. Use tools like Altium, Eagle, or similar to create schematic diagrams and PCB layouts. Perform Design for Manufacturing (DFM) and Design for Testing (DFT) to optimize designs for production, reliability, and ease of testing. Analyze component datasheets to ensure designs meet the required specifications. Conduct in-depth testing of prototypes, LED drivers, and finished products using oscilloscopes, multimeters, and other electrical testing tools. Identify and resolve circuit-level issues, such as power instability, thermal management, or electromagnetic interference (EMI). Work closely with RD, quality control, and production teams to integrate designs smoothly into the manufacturing process. Collaborate with senior engineers to improve and optimize existing LED driver products. Maintain comprehensive documentation for designs, testing processes, component selections, and modifications to ensure efficient project tracking. Prepare detailed reports on product performance, test results, and design changes for internal and external communication. Ensure that all designs comply with relevant industry standards and certifications and meet quality assurance requirements for production and end-user safety. Knowledge of electronic components and circuits, particularly for driver applications. Hands-on experience with testing, debugging, and troubleshooting electronics. Familiarity with industry standards and safety protocols for electronics design. Ability to troubleshoot and optimize electronic components for reliability and efficiency. This job is provided by Shine.com

You are a highly skilled and experienced engineer with a deep understanding of synthesis, timing closure, power optimization, and constraints management. Your expertise includes working on advanced nodes under 5nm and proficiency in low-power, high-performance design. Familiarity with RTL, DFT, LDRC, TCM, VCLP, and PTPX gives you an edge in tackling complex design challenges. Your ability to use scripting languages such as TCL, Perl, and Python is a valuable asset. Holding a BS or MS in Electrical Engineering or a related field with over 9 years of relevant experience, you are well-equipped to drive continuous technological innovation and transform the future. Your responsibilities will include developing innovative methodologies for implementing high-performance CPUs, GPUs, and interface IPs. You will utilize advanced technologies and tool features to enhance quality of results and streamline the implementation process. Contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs will be a key part of your role. Working with industry-leading Synopsys tools such as RTLA and Fusion Compiler, you will solve critical design challenges and collaborate with a global team to stay ahead of technological advancements. Your impact will be significant as you advance the state-of-the-art in high-performance core and IP implementation, enhance the performance and efficiency of Synopsys" design methodologies and tools, and enable the development of cutting-edge semiconductor technologies at advanced nodes. You will contribute to the successful delivery of high-quality, high-performance IPs to the market, drive innovation, and support Synopsys" mission to lead in chip design, verification, and IP integration. To excel in this role, you will need deep knowledge of synthesis, timing closure, power optimization, and constraints management, along with experience in low-power, high-performance design at advanced nodes under 5nm. Proficiency in RTL, DFT, LDRC, TCM, VCLP, and PTPX, as well as familiarity with scripting languages such as TCL, Perl, and Python, are essential. A BS or MS in Electrical Engineering or a related field with 9+ years of relevant experience will further strengthen your qualifications. You are a detail-oriented and innovative engineer with a passion for pushing the limits of technology. Your problem-solving skills, ability to optimize design processes, and effective collaboration with a global team set you apart. Motivated by continuous improvement and making a significant impact in the field of semiconductor design, you are well-suited to join the growing global team at Synopsys dedicated to advancing high-performance core and IP implementation.,

Job Description Change the world. Love your job. The Validation Engineers at Texas Instruments are powered by a passion for continual improvement. Our solutions make a real difference and yours will, too. We make the semiconductor product design process easier and faster, which helps our customers succeed in today's fast-paced marketplace. Job Description: We are seeking a skilled and experienced Validation Engineer to take ownership of the validation function for our IC projects. The successful candidate will be responsible for designing and implementing comprehensive validation plans, developing validation hardware and software, automating test setups, and ensuring the overall quality of silicon sign-off for production release. Key Responsibilities: Lead Validation Efforts: Design and execute hands-on validation plans for automotive IC projects, including hardware and software development for validation and automation setups. Silicon Debugging: Perform silicon debugging to identify and resolve issues, ensuring production-grade quality for silicon sign-off. EMI/EMC Testing: Conduct in-house EMI/EMC tests and coordinate with external certification bodies for testing and approval. Cross-Functional Collaboration: Work closely with the Design and DV (Design Verification) teams pre- and post-PG to ensure closure on DFT (Design for Test), validation plans, and specifications. Collaborate with the Test team to correlate validation and test results, ensuring optimal fault coverage (FT) and a high-quality, cost-effective build. Partner with the Product Engineering team to execute all IC qualification requirements and oversee release to production. Project Management Support: Collaborate with Program Managers to ensure the project remains on track with respect to budget and schedule commitments. Participating in APPIT: actively plan and contribute to continues improvement of Automation Process Package IP and Test. Mentoring Junior Engineers : Mentor and guide new college graduate engineers (>2 NCGs), helping them develop skills in validation and ensuring their successful integration to the team QUALIFICATIONS Job Qualifications: Proven experience in silicon validation, including hands-on development of validation hardware, software, and test automation. Strong understanding of EMI/EMC testing and debugging, including experience coordinating with external certification houses. Experience working in cross-functional teams, including Design, DV, Test, and Product Engineering teams. Proven ability to mentor and guide junior engineers. Experience in contributing to APPIT and paper presentation skills Solid knowledge of DFT principles, silicon debug methodologies, and IC qualification processes. ABOUT US Why TI? Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. About Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com . Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. If you are interested in this position, please apply to this requisition. ABOUT THE TEAM TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.

In this role you will have the opportunity to Work as Principal Engineer, Quality Assurance accountable for overall product quality of the NPI releases. The Principal Engineer provides independent oversight of the design input process, design V&V activities, design transfer and product realization, and performance in the field to ensure that all design requirements are effectively met. The Principal Engineer also provides analytics to the Business on the efficacy, efficiency of the design and product realization processes. Opportunity to learn End to End product development as Responsible Quality representative driving compliance throughout Product life cycle. We are looking for a dynamic individual to join our Quality and Reliability Engineering team. The candidate is expected to have demonstrated proficiency in the philosophy of Quality. The candidate should demonstrate strong systems engineering fundamentals across all critical engineering domains important to product quality. The candidate should be able to challenge the status quo and be able to appropriately represent the voice of the customer to core teams while making decisions related to product quality. The ideal successful candidate Responsibilities: Responsible for all aspects of product quality from PRD to Production handover for high volume production development until sustaining. Single point of contact, representing and driving quality in all program team meetings. Conduct cross-site, cross-team lessons learned for any Quality issues during development and sustaining phases of Product Life-Cycle Participate in Engineering reviews ( PRD, DFx, Qualification sync, test plan, RDT ) and forecast potential quality risk Perform quality risk assessment to a project and drive for mitigations enabling business, apart from being a gatekeeper Identify process gaps in the Product Life Cycle (PLC) and continuously highlight improvement actions for the execution teams Influence quality culture and mindset across the company and bring in more strategic goals Demonstrated to take data based decisions and resolve contentions Qualifications Bachelor or Masters Degree in Electrical/Electronic based Engineering 10 to 12yrs of certified professional experience in quality engineering Thorough understanding on Product Life Cycle a

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SE NIOR SILICON DESIGN ENGINEER 1. Must have SoC implementation knowledge with deep level expertise in at least one domain. Have responsibility for processes of significant technical importance and for results in SoC implementation and/OR related areas. Solve complex, novel and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation. Influences technical decisions that have a significant impact on final product. Requires limited supervision and is evaluated according to project performance. Coaches and mentors less experienced staff; influences others as a technical leader. very good communication and presentation skills Proficiency in scripting Required Skills: SoC implementation expertise. Multi million gates integration. Low power implementation, Constraints validation, Formal verification Floorplanning, Power planning. Clock Tree Synthesis (CTS). Awareness of Synthesis, SCAN and DFT implementation Static Timing analysis (STA). Analysis: IR, EM, Noise. Physical Verification #LI-PK2 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing efforts with capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop Power Intent Specification in UPF for the multi-Vdd designs Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in Design Integration and Front-End Implementation Experience with Register-Transfer Level (RTL) Synthesis and design optimization for Power, Performance, Area Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other Hardware Description Language (HDL) Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues Experience with Electronic Design Automation (EDA) tools and scripting languages (Python, TCL) used to build tools and flows for complex environments. Experience with communicating across functional internal teams and vendors Preferred Qualifications: Experience Knowledge of Register-Transfer Level (RTL) coding using Verilog/System Verilog. Knowledge of Timing/physical libraries, Static Random Access Memory (SRAM) Experience with Power, Performance, Area Analysis and techniques for reducing power Knowledge of Clock Domain Crossing, Reset Domain Crossing, Logic Error Correction (LEC) Scripting and programming experience using Perl/Python, TCL, and Make Knowledge of Low power design. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Synthesis Background, Timing Constraints Development, Floorplanning and Static Timing Analysis (STA) About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

As a member of the Common Hardware Group (CHG) at Cisco, you will be part of a team that delivers cutting-edge silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Our work involves designing networking hardware for Enterprises, Service Providers, Public Sector, and Non-Profit Organizations worldwide. Join us in shaping Cisco's groundbreaking solutions by participating in the design, development, and testing of advanced ASICs that are at the forefront of the industry. Your role will involve implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics requirements of the designs. You will collaborate with multi-functional teams to develop innovative DFT IP and play a crucial role in integrating testability features in the RTL. Working closely with design and PD teams, you will ensure the seamless integration and validation of test logic throughout all phases of implementation and post-silicon validation flows. Your team will contribute to the creation of innovative Hardware DFT and physical design aspects for new silicon device models, bare die, and stacked die. You will drive re-usable test and debug strategies while showcasing your ability to craft solutions and debug with minimal mentorship. To excel in this role, you are required to have a Bachelor's or Master's Degree in Electrical or Computer Engineering along with a minimum of 10 years of relevant experience. Your expertise should encompass knowledge of the latest trends in DFT, test, and silicon engineering. Proficiency in Jtag protocols, Scan and BIST architectures, ATPG, EDA tools, and verification skills like System Verilog Logic Equivalency checking will be essential. Preferred qualifications include experience in Verilog design, DFT CAD development, Test Static Timing Analysis, and Post-silicon validation using DFT patterns. Your background in developing custom DFT logic and IP integration, familiarity with functional verification, and scripting skills like Tcl, Python, or Perl will be advantageous. At Cisco, we value diversity, innovation, and collaboration. We empower our employees to bring their unique talents to work, driving positive change and powering an inclusive future for all. As a company that embraces digital transformation, we encourage creativity, innovation, and a culture that supports learning and growth. Join us at Cisco, where every individual is valued for their contributions, and together, we make a difference in the world of technology and networking.,

You should be an ASIC designer with a minimum of 1-15 years of experience in RTL design using Verilog/System Verilog. Your expertise should cover all aspects of the RTL design flow, including Specification/Microarchitecture definition, design and verification, Timing Analysis, DFT, and Implementation. You should also have experience in Integration, RTL signoff tools, UPF/Low power signoff, CDC/RDC, and Lint. Your domain knowledge should be strong in Clocking, System modes, Power management, debug, interconnect, safety, security, and other architectures. As a highly motivated individual, you should be a self-starter with excellent interpersonal skills and the ability to work effectively in a team. Strong communication, critical thinking, and problem-solving skills are essential for this role. Preferred education for this position is any degree.,

This position offers an excellent career opportunity for a computational chemist to leverage quantum chemistry skills in chemical process optimization and product development in the agrochemical industry. You should have a thorough understanding of DFT and ab initio electronic structure theory methods. Proficiency with Quantum Chemistry based software tools like Turbomole, Gaussian, deMon, GAMESS-US, Quantum espresso, VASP, etc. is required. Additionally, you should have proficiency with any of the scripting languages like Bash, Python, Perl, etc. and working in a Linux environment and high-performance computing platforms. Demonstrated experience in using electronic structure based software tools in understanding chemical reactivity and reaction mechanisms is essential. Experience in catalyst design and the use of data-based models to optimize industrial processes is preferred. Moreover, experience in utilizing in-house experimental data and modelled parameters towards predictive modeling and statistics would be a plus. You should have a working knowledge of classical methods like force fields and molecular dynamics simulations. The ability to work in a collaborative multidisciplinary scientific environment and communicate technical results to experimentalists is crucial for this role. The ideal candidate should have 3+ years of postdoc or industrial experience in a related field, with a PhD in Chemistry/Physics specializing in Theoretical Chemistry/Computational Chemistry/Chemical Physics or a related discipline from a reputed University/Institute in India or overseas with excellent academic credentials.,

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT.: Experience: 3-5 Years.