1063 Dft Jobs - Page 3

EE Department Ahmedabad, Gujarat, India Full Time No of Position: 1 Experience: 3-6 Years Expertise / Skills Footprint creation Layout, high-speed layout,multi-layer board design Orcad (must) Allegro (must) Job Description Guide and provide technical support to juniors for Project development. Experience in High-speed design and Analog design routing. Experience with PCB Layout design up to 4 layers is preferred. Conduct hardware design in DFM, DFA, and DFT format Should be open to working in a challenging environment with minimal supervision Design and Develop Multilayer PCB Basic knowledge of IPC Standards PCB Design as per the EMI / EMC standards Strong Skills for Library development, footprint creation, and Layout in software like Orcad (must), Altium, Allegro (must), Eagle, Mentor Graphics, etc Demonstrate robust design principles in the execution Continuously upgrade skills and knowledge of self Signal Integrity and Power Integrity. Knowledge of protocols including RS232, RS485, SPI, USB, CAN, ZigBee, Experience in Power supply- SMPS design, DC/DC converter, LDOs Apply Now

Location :- Bangalore Experience :- 12-20 years Required Skills And Experience: This role is for a Principal DFT engineer with 15 years plus experience Technical leadership in DFT and ability to train/work with junior team members Experience with Perl, TCL, and/or python with ability to build and deploy generic DFT flows Proficient in Unix/Linux environments One or more core DFT skills are considered crucial for this position including some of the following Knowledge of at-speed testing, test insertion and test coverage assessment, test pattern development, scan compression, Memory BIST, Logic BIST, JTAG, IJTAG, fault simulation, debug, verification, SSN, designing and conducting experiments/tool evaluations. Experience with Siemens, Cadence and/or Synopsys DFT tools Qualified candidates will have a university degree (or equivalent) in Electronic Engineering, Computer Engineering, or other relevant technical subject area.

Experience: 5 + Should have worked hands-on Full chip DFT implementation, Scan, DRCs, ATPGgeneration & Simulations along with Pattern Porting/re-targeting and Coverage improvement Experience with Scan, Compression, ATPG and simulations withSynopsys EDAtools. Should have participated in successful tape-outs of SoC/ASIC chips at 3nm or below and achieved test targets. Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process Excellent problem solving and debugging skills. Proactive in nature Excellent Customer interaction, Communication and Team work skills Skills Required Cadence Tools, Automatic Test Pattern Generation (ATPG), DFT, Memory Built-In Self Test (MBIST),Scan Insertion Location Hyderabad, India Desirable Skills Cadence Tools, Automatic Test Pattern Generation (ATPG), DFT, Memory Built-In Self Test (MBIST),Scan Insertion Designation Associate

Hi All, Greetings from Eximietas...! Position: Senior DFT Engineers/Leads/Architects Location: Visakhapatnam Mode of Work: On-site Exp: 5 to 15 Years We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches. Job Overview: Must be able to obtain and maintain a Department of Defense classified clearance Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT) Should possess intimate knowledge of DFT insertion flows Basic scan chain insertion using synthesis or other software tools Experience in compression scan insertion, LBIST and other scan technologies Intimate knowledge of memory build-in self-test (MBIST) Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals Debug and Analysis of failures to improve fault coverage Verification of ATPG testbenches and debugging root cause of simulation mis-compares Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687 Knowledge of timing analysis and equivalency checks would be added bonus Ability to work in collaborative team environment Should be able to finish DFT tasks independently Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers Self-driven and committed individual who can work in a fast-paced project environment This job might be for you if : You enjoy solving problems and love tackling difficult challenges with creative solutions. You persistently seek answers even when they are not readily available. You communicate clearly and write well . You are motivated, driven, and take initiative without waiting to be asked. You take ownership of your work and strive to make a difference. You can impress customers with your enthusiasm and ability to solve their issues. Qualifications: Bachelor’s degree in Computer Science, Electrical/Electronics Engineering , or a related field.

Hello All, Eximietas Design Hiring STA Engineers/Leads Experience: 5+ Years Job Description: Experience in Static Timing Analysis (STA) for ASIC designs. Experience in developing timing constraints. Experience in timing closure and optimization. Proficiency in using scripting languages such as Perl and TCL. Familiarity with EDA tools such as PrimeTime and Design Compiler. Experience in Physical Design and/or DFT is a plus. Bachelor’s or Master’s degree in Electrical/Electronics/Computer Science Engineering or related field. Interested Engineers, please share your updated resume: maruthiprasad.e@eximietas.design

Hi All, Greetings from Eximietas...! Position: Senior DFT Engineers/Leads/Architects Location: Visakhapatnam Mode of Work: On-site Exp: 5 to 15 Years We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches. Job Overview: Must be able to obtain and maintain a Department of Defense classified clearance Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT) Should possess intimate knowledge of DFT insertion flows Basic scan chain insertion using synthesis or other software tools Experience in compression scan insertion, LBIST and other scan technologies Intimate knowledge of memory build-in self-test (MBIST) Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals Debug and Analysis of failures to improve fault coverage Verification of ATPG testbenches and debugging root cause of simulation mis-compares Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687 Knowledge of timing analysis and equivalency checks would be added bonus Ability to work in collaborative team environment Should be able to finish DFT tasks independently Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers Self-driven and committed individual who can work in a fast-paced project environment This job might be for you if : You enjoy solving problems and love tackling difficult challenges with creative solutions. You persistently seek answers even when they are not readily available. You communicate clearly and write well . You are motivated, driven, and take initiative without waiting to be asked. You take ownership of your work and strive to make a difference. You can impress customers with your enthusiasm and ability to solve their issues. Qualifications: Bachelor’s degree in Computer Science, Electrical/Electronics Engineering , or a related field.

Hi All, Greetings from Eximietas...! Position: Senior DFT Engineers/Leads/Architects Location: Visakhapatnam Mode of Work: On-site Exp: 5 to 15 Years We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches. Job Overview: Must be able to obtain and maintain a Department of Defense classified clearance Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT) Should possess intimate knowledge of DFT insertion flows Basic scan chain insertion using synthesis or other software tools Experience in compression scan insertion, LBIST and other scan technologies Intimate knowledge of memory build-in self-test (MBIST) Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals Debug and Analysis of failures to improve fault coverage Verification of ATPG testbenches and debugging root cause of simulation mis-compares Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687 Knowledge of timing analysis and equivalency checks would be added bonus Ability to work in collaborative team environment Should be able to finish DFT tasks independently Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers Self-driven and committed individual who can work in a fast-paced project environment This job might be for you if : You enjoy solving problems and love tackling difficult challenges with creative solutions. You persistently seek answers even when they are not readily available. You communicate clearly and write well . You are motivated, driven, and take initiative without waiting to be asked. You take ownership of your work and strive to make a difference. You can impress customers with your enthusiasm and ability to solve their issues. Qualifications: Bachelor’s degree in Computer Science, Electrical/Electronics Engineering , or a related field.

THE ROLE: As a member of the G&E SoC DFT Team, the successful candidate will own the DFX timing responsibilities for the next gen of AMD SoCs. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones.You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: The candidate must have thorough knowledge of DFT basics such as scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Need to work with product engineering team for Silicon Bring-up and also support post-silicon debug. DFX timing constraints development Review timing reports Timing closure for different modes : AC/DC scan capture , scan shift , MBIST Interfacing with the design teams to ensure DFT design rules and guidelines are met Interact with PD and Front End Integration team for Scan Insertion Generating high quality manufacturing test patterns for stuck-at, transition fault models and CA model Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, enhancing and maintaining scripts as necessary Able to technically guide and mentor junior folks in the team PREFERRED EXPERIENCE: Experience in creating and implementing complex chip-level DFT architecture DFX timing constraints development Review timing reports Timing closure for different modes : AC/DC scan capture , scan shift , MBIST Experience in DFT implementation including Scan insertion, ATPG and Simulations Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression Experience in debugging low coverage and DRC fixes Proficient in logic design using Verilog Experience of debugging test pattern issues Support the Silicon bringup activities to guarantee highest stability of the test pattern Knowledge of MBIST is a plus. Knowledge of synthesis is a plus Experience with post-silicon debug Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc Any Tessent Scan/ATPG certifications is a plus Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Prior experience as DFT engineer

THE ROLE: Be a member of the team that plays a significant role in ensuring the quality of next generation microprocessors through structured DFT, Automatic Test Pattern Generation (ATPG) and Logic Built-In Self-Test (LBIST) techniques. Key responsibilities: Collaborating with the design teams to ensure DFT design rules and guidelines are met The person should have experience in timing concepts Generating high quality manufacturing test patterns for stuck-at, transition fault models and through the use of on-chip test compression techniques Exercising the LBIST circuitry and ensuring that repeatable signatures can be produced Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, improving and maintaining scripts as vital Desired profile - The candidate must have detailed knowledge of DFT basics such as scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Experience with test tools such as FastScan and TestKompress is highly desirable.Scan/ATPG, knowledge of industry standard DFT features, simulation debug, MBIST Academic credentials: MS/M Tech/BE in Computer Engineering/Electronics/Electrical Engineering Demonstrated success in a senior ICteam role with similar skills Location: Hyderabad Telangana

MTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs.?As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Understanding of DesignforTest methodologies and DFT verificationexperience (eg.IEEE1500, JTAG 1149.x, Scan, memory BISTetc.) Experience with Mentortestkompressand/or SynopsysTetramax/DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

THE ROLE: Be a member of the team that plays a significant role in ensuring the quality of next generation microprocessors through structured DFT, Automatic Test Pattern Generation (ATPG) and Logic Built-In Self-Test (LBIST) techniques. Key responsibilities: Collaborating with the design teams to ensure DFT design rules and guidelines are met The person should have experience in timing concepts Generating high quality manufacturing test patterns for stuck-at, transition fault models and through the use of on-chip test compression techniques Exercising the LBIST circuitry and ensuring that repeatable signatures can be produced Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, improving and maintaining scripts as vital Desired profile - The candidate must have detailed knowledge of DFT basics such as scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Experience with test tools such as FastScan and TestKompress is highly desirable.Scan/ATPG, knowledge of industry standard DFT features, simulation debug, MBIST Academic credentials: MS/M Tech/BE in Computer Engineering/Electronics/Electrical Engineering Demonstrated success in a senior ICteam role with similar skills Location: Hyderabad Telangana AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV

THE ROLE: We are looking for an adaptive, self-motivated design for test verification engineer to join our growing server SOC DFT team. Identified candidate will be responsible for high quality verification of our DFT features for next generation server SOCs. This team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion design for test, and verification. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Create and execute test plans for DFT features for next generation EPYC server SOCs. Carryout verification of DFT features such as JTAG/1500/1687, MBIST, Scan, Fuse, Clocks, Resets, high speed IO testing and much more at SOC level. Will be creating test bench and verification infra using SV or C++. Debug regression test failures and root cause design issues, identify verification gaps and address the same. Debug fails and root cause them to design / verification issues. Planning and projecting timelines for areas owned such as test plan creation, test writing, development of verification components, pattern generation etc. Collaborate with large set of stakeholders such as architects, design engineers, functional verification engineers, post silicon engineers etc. Work on code and functional coverage. Generate patterns for post silicon testing and support ATE bring up. Carryout post silicon debugs and help post silicon team achieve high coverage. Work on emulation platforms to augment verification. PREFERRED EXPERIENCE: Prior experience in verifying DFT features at subsystem / SOC level. Proficient in standard simulation & debug tools?such as VCS, Verdi etc. Experienced with Verilog, C, C++, Linux and Windows environments. Scripting language experience: Perl, Python,Ruby, Makefile, shell preferred. Knowledge in few of the DFT features such as JTAG, Memory BIST, Logic BIST, Scan, ATPG is highly desirable Exposure to post silicon debugs and bring up highly is desired.

KEY RESPONSIBILITIES: ? Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues? Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements ? PREFERRED EXPERIENCE: ? Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools? Proficient in using UVM test benches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++?? Graphics pipeline knowledge Developing UVM based verification frameworks and test benches, processes and flows Automating workflows in a distributedcomputeenvironment.?? Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts andSystem Veriloglanguage Good working knowledge ofSystem Cand TLM with some related experience.?? Scripting language experience: Perl, Ruby,Make file, shell preferred.?? Exposure to leadership or mentorship is an asset Desirableassetswith prior exposure to video codec system or other multimedia solutions.?? ? ACADEMIC CREDENTIALS: ? Bachelors orMastersdegree in computer engineering/Electrical Engineering#LI-NS1

Bengaluru, Karnataka Job ID JR2025464648 Category Engineering - Electronic and Electrical Role Type Onsite Post Date Jul. 24, 2025 Job Description At Boeing, we innovate and collaborate to make the world a better place. We’re committed to fostering an environment for every teammate that’s welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us. Overview As a leading global aerospace company, Boeing develops, manufactures, and services commercial airplanes, defense products and space systems for customers in more than 150 countries. As a top U.S. exporter, the company leverages the talents of a global supplier base to advance economic opportunity, sustainability, and community impact. Boeing’s team is committed to innovating for the future, leading with sustainability, and cultivating a culture based on the company’s core values of safety, quality, and integrity. Technology for today and tomorrow The Boeing India Engineering & Technology Center (BIETC) is a 5500+ engineering workforce that contributes to global aerospace growth. Our engineers deliver cutting-edge R&D, innovation, and high-quality engineering work in global markets, and leverage new-age technologies such as AI/ML, IIoT, Cloud, Model-Based Engineering, and Additive Manufacturing, shaping the future of aerospace. People-driven culture At Boeing, we believe creativity and innovation thrives when every employee is trusted, empowered, and has the flexibility to choose, grow, learn, and explore. We offer variable arrangements depending upon business and customer needs, and professional pursuits that offer greater flexibility in the way our people work. We also believe that collaboration, frequent team engagements, and face-to-face meetings bring Inclusive perspectives and thoughts – enabling every voice to be heard and every perspective to be respected. No matter where or how our teammates work, we are committed to positively shaping people’s careers and being thoughtful about employee wellbeing. At Boeing, we are inclusive and transformative. With us, you can create and contribute to what matters most in your career, community, country, and world. Join us in powering the progress of global aerospace. Boeing India Engineering has an immediate opening for an Engineering Manager - Digital Circuitswho will be responsible for development and management of engineers in India to perform engineering work-statements for Boeing product life cycle management. This position will work collaboratively with teams from across the globe in an integrated design environment to help deliver an engineering statement of work. The selected individual will develop and handle Engineers, interact with the program leaders from across the globe, with a vision to grow ownership in execution with their team. This position will be in Bengaluru, India , and will be reporting directly to the Sr. Electronic Manager, India. Primary Responsibilities: Manage employees performing engineering and technical activities in the areas of ASIC/FPGA verification and design. Develops and executes integrated departmental plans, policies and procedures and provides input on departmental business and technical strategies, goals, objectives. Acquires resources for department activities, provides technical management of suppliers and leads process improvements. Develops and maintains relationships and partnerships with customers, stakeholders, peers, partners and direct reports. Provides oversight and approval of technical approaches, products and processes. Provides project/Activity planning, and key milestone tracking. Manages post silicon debug support activities for validation, SW development and Test Team. Manages directly (including people reporting) the RTL, DV and DFT primarily. Integrated PD and Emulation activities Understand complex protocols and create implementable objectives for team, Protocols would include PCIe, ARINC, MIL 1553, USB, I2C and other proprietary protocols related to space and flight systems Manages, develops and motivates employees along with functional capability planning. Build capability and capacity upon SV & UVM. Nurture directed test case scenarios using VHDL and similar platforms. Should have strong verbal and written communication skills. Basic Qualifications (Required skills/experience): Bachelor’s degree or higher is required At least 12 years of experience in Digital IC design and verification, involved in at least 3 Chip Tape outs or equivalents. Proficient in tools such as Vmanager and similar tools with other EDA vendors to track and maintain verification workflow metrics for the team. Proficient in concepts such as cross domain clock sync, polymorphism. Proficient in validating the verification workflow with available limitations on tools and resources to provide maximum functional coverage on priority. Demonstrated success leading development efforts, including project management and earned value tracking. Preferred Qualifications (Desired skills/experience): Experience leading or managing in an engineering organization. Familiarity with FAA DO-254 certification. Familiar with Emulation and Safety Flow Analysis Familiar in Formal Verification techniques Familiar in Design Concepts US Person as defined by 22 C.F.R § 120.15 is advantageous. Familiar with LOR verification based VCRM structure Typical Education & Experience: Education/experience typically acquired through advanced education (e.g. Bachelor) and typically 13 to 16 years' related work experience or an equivalent combination of education and experience (e.g. Master+12 years of related work experience etc.) Applications for this position will be accepted until Aug. 02, 2025 Export Control Requirements: This is not an Export Control position. Education Bachelor's Degree or Equivalent Required Relocation This position offers relocation based on candidate eligibility. Visa Sponsorship Employer will not sponsor applicants for employment visa status. Shift Not a Shift Worker (India) Equal Opportunity Employer: We are an equal opportunity employer. We do not accept unlawful discrimination in our recruitment or employment practices on any grounds including but not limited to; race, color, ethnicity, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military and veteran status, or other characteristics covered by applicable law. We have teams in more than 65 countries, and each person plays a role in helping us become one of the world’s most innovative, diverse and inclusive companies. We are proud members of the Valuable 500 and welcome applications from candidates with disabilities. Applicants are encouraged to share with our recruitment team any accommodations required during the recruitment process. Accommodations may include but are not limited to: conducting interviews in accessible locations that accommodate mobility needs, encouraging candidates to bring and use any existing assistive technology such as screen readers and offering flexible interview formats such as virtual or phone interviews. Your Benefits No matter where you are in life, our benefits help prepare you for the present and the future. Competitive base pay and incentive programs. Industry-leading tuition assistance program pays your institution directly. Resources and opportunities to grow your career. Up to $10,000 match when you support your favorite nonprofit organizations.

As a Semiconductor Sales/Business Development Manager based in India, you will play a crucial role in leading and expanding semiconductor business engagements throughout the country. This position is well-suited for individuals who possess a proven track record in ASIC/SoC/IC services or product sales within the semiconductor industry. Your primary responsibilities will include owning the entire sales lifecycle, from prospecting and lead qualification to solution positioning, proposal development, and deal closure. You will be tasked with establishing and nurturing relationships with Tier-1 and Fabless semiconductor customers, while collaborating closely with internal engineering and delivery teams to craft customized solutions. With at least 5 years of experience in semiconductor industry sales and a focus on working with semiconductor services or product companies, you will be expected to bring a hybrid sales approach that combines both hunting (acquiring new clients) and farming (growing existing accounts). Your expertise in Semiconductor Design and end-to-end ASIC turnkey solutions will be instrumental in delivering comprehensive services ranging from Specifications to Silicon, encompassing spec definition, RTL, physical design, verification, DFT, and tape-out support. The ideal candidate for this role will possess a deep understanding of ASIC/SoC design lifecycles and semiconductor engagement models, along with a demonstrated ability to establish new accounts and expand existing ones. You should feel comfortable engaging with technical and business stakeholders, such as engineering and procurement teams, and have familiarity with turnkey project delivery or IP/ASIC services sales. This challenging yet rewarding position offers significant ownership in shaping the semiconductor sales footprint of our organization. If you are passionate about building strong customer relationships and delivering high-value technical solutions, this role presents an exciting opportunity for professional growth. If you are interested in this role or know someone who might be a great fit, please reach out via email to ranjith.allam@cyient.com.,

If you are passionate about pushing the boundaries of Design technology and thrive in a collaborative, dynamic environment, we invite you to join our team as a Design Engineer. Join us to be part of our journey in shaping the future of SoC design and innovation. Responsibilities As a creative design engineer with a knowledge of subsystems and SoCs you will be part of a team integrating IP and developing logic for SoCs. You will work with the project team to understand and review the architecture and develop the design specifications. Your key responsibilities will include writing micro-architecture specifications, developing the RTL, fixing bugs and running various design checks. You will work with the verification team to review test plans and help debug design issues. You will work with the performance analysis team to evaluate and improve subsystem performance. You will also contribute to developing and enhancing the design methodologies used by the team. You will guide and support other members of the team as needed to enable the successful completion of project activities. You will balance other opportunities such as working with Project Management on activities, plans, and schedules Required Skills and Experience: In addition to bringing your accomplishment of either Bachelors or masters degree or equivalent experience in Computer Science or Electrical/Computer Engineering. Experience of 8+ years working in design of complex compute subsystems or SoCs, you will need: Strong knowledge of digital hardware design and Verilog HDL! A thorough understanding and experience of the current design techniques for complex SoC development. Experience creating design specifications Experience developing RTL for SoC projects Experience with Perl, Python or other scripting language Desired Skills and Experience: Experience with ARM-based designs and /or ARM System Architectures Experience integrating subsystems for PCIe, LPDDR, HBM, UCIe, Ethernet Experience with SystemVerilog and verification methodologies UVM/OVM/e Experience leading small teams or projects Experience or knowledge in the following areas Synthesis and timing analysis Static design checks, including CDC, RDC, X-Propagation, Linting Power management techniques DFT and physical implementation

"> Search Jobs Find Jobs For Where Search Jobs Staff RTL Design Engineer Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12211 Remote Eligible No Date Posted 21/07/2025 Alternate Job Titles: Senior Digital Design Engineer ASIC Design Engineer High-Speed SerDes Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced ASIC Digital Design Engineer with a strong background in digital design for high-speed serial interfaces. You have a deep understanding of USB, PCIe, Ethernet, Display, and HDMI protocol standards, and you thrive in a collaborative environment. Your expertise in Verilog RTL design, microarchitecture, and timing constraints development makes you a valuable asset to any team. You are adept at using tools like Spyglass for CDC/RDC/Lint and have excellent debugging skills. Your ability to propose and implement design updates based on various requirements, coupled with your experience in test coverage and physical design timing closure, sets you apart as a leader in your field. With a passion for innovation and a keen eye for detail, you are ready to take on new challenges and contribute to the success of Synopsys. What You ll Be Doing: Driving and working on digital design for high-speed serial interface PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Proposing micro-architecture of design/design updates based on customer requirements, analog requirements, system performance improvements, Link layer interface changes, or overall robustness of design. Implementing RTL in Verilog and running Spyglass CDC/RDC/Lint. Collaborating with verification teams to test desired functionality and corner cases. Developing timing constraints, DFT insertion, and test coverage, and closing timing with physical design teams. Well versed in Micro-Architecture and Block Ownership, Design from scratch. The Impact You Will Have: Enhancing the performance and reliability of high-speed serial interface PHY IPs. Contributing to the development of cutting-edge technologies that power modern electronics. Driving innovation in digital design and influencing the future of semiconductor technology. Collaborating with cross-functional teams to deliver robust and high-quality designs. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous improvement and excellence. Supporting customers by providing high-performance and reliable IP solutions that meet their needs. What You ll Need: 5-8 years of relevant experience in digital design for ASICs. Strong knowledge of Verilog RTL design and microarchitecture. Experience with timing constraints development and synthesis flow. Proficiency in using Spyglass or similar tools for Lint/CDC/RDC. Proficiency in scripting and automation using TCL, PERL, or Python. Excellent debugging skills and attention to detail. Who You Are: A collaborative team player with strong communication skills. A problem solver with a proactive approach to challenges. A detail-oriented professional with a passion for innovation. A self-motivated individual who thrives in a fast-paced environment. An adaptable engineer who can handle multiple tasks and priorities. The Team You ll Be A Part Of: You will be part of the High-Speed SerDes Digital Design Team, a group of talented engineers dedicated to developing high-performance serial link PHY IPs. The team focuses on innovation, quality, and collaboration to deliver industry-leading solutions. Together, you will work on challenging projects that push the boundaries of technology and make a significant impact on the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

CAD Engineer 3 Duties of Position: (Include specific duties and responsibilities) Requires a broad knowledge of PCB Layout Engineering practices, manufacturing process and IPC standards Should be responsible to adhere the DFM/DFA and DFT process and preparing the files for PCB Fabrication and Assembly Execute the High speed Design boards and support team members to develop skill sets for Sanmina Design specifications. Should interact with SI and PI team. Design consideration for EMI/EMC, thermal and Mechanical performance enhancement Design the complex and multi-Layer PCB Board using Cadence Allegro Tool. Technical expertise to handle project independently Design consideration for EMI/EMC, thermal and Mechanical performance enhancement Excellent Team player who interact with other Team Members and Supervisors Experience in skill development, Design automation are preferred Experience in Library database management is preferred. Experience in EDA tool automation is preferred. Qualifications Required: (Education, experience, skills, etc. Please be specific) BE/B.Tech in Electronics, Electronics and Communication , Electrical and Electronics Engineering Minimum of 5 years of experience in PCB Layout development experience in computer, Server, Storage PCBAs or related fields. Technical expertise in High Speed Digital , Analog and Power Supply designs Experience in board layout for x86 based Computing, Server and Storage Application domain. Experience in Intel designs especially Sandy bridge and Server platform designs. Familiarity in High End Processor based Mother Board Design, DDRx memory interfaces, Ethernet interfaces Familiarity with Signal Integrity concepts and its implementation Strong knowledge in EDA Tool (Cadence Allegro). Knowledge in other EDA tools like Mentor Graphics and Altium is added advantage. Expertise in DFx concepts and its implementation. Familiarity with Valor/CAM350 or DFM/DFA tool is preferred The Candidate should have experience in successful participation in development projects from design to production. Should be proficient with office productivity tools including Microsoft Office. Candidate should have basic knowledge of project management methods, and strong verbal and written communication skills. Solid understanding of manufacturing pcb assembly flows. Experience in EDA tool automation is preferred. Must be detail oriented and have a proven ability to organize, analyze, set priorities, and multi task in a fast paced environment Must be self-disciplined, highly productive and work effectively in team.

Design and develop complex multilayer PCB HDI layouts (analog, digital, RF, power electronics) as per layout guidelines. Creating ECU layouts for automotive applications Collaborate with hardware engineers, signal integrity experts, and manufacturing teams to ensure designs meet performance, manufacturability (DFM), and testability (DFT) requirements. Worked on high-speed PCB design, impedance control, power planes, and signal integrity. Participate in design reviews, continuous improvement initiatives. Interface with PCB manufacturers and vendors for prototype procurement and cost optimization.

About Us At Triveni Wires, we are building next-generation battery technologies with real-world impact. Whether it’s enhancing material performance, innovating manufacturing processes, or integrating AI into battery design and testing, we thrive at the intersection of science, engineering, and adaptability. We’re seeking curious minds who can learn fast, build prototypes, test with rigor, and grow with the company. Role Description A technical generalist —comfortable jumping between lab work, simulations, data, and whiteboards. Maybe you’ve worked on lithium-ion, solid-state, sodium-ion, or just have a strong chemistry or materials background and a burning desire to build better batteries. You love experimenting, iterating, and thinking across disciplines. What You’ll Do Stay up to date with scientific literature and propose new ideas or improvements Design, set up, and execute experiments on battery materials, electrodes, and full-cell configurations Analyze performance metrics such as cycle life, energy density, conductivity, and degradation Work with cross-functional teams to apply insights into design improvements Support the development of test protocols and SOPs Optionally explore AI/ML or simulation tools (e.g. COMSOL, PyBaMM, DFT, etc.) if you have a tech/software bend Ideal Qualifications Bachelor’s/Master’s in Chemical Engineering, Materials Science, Physics, Electrochemistry, or related field Hands-on lab experience with batteries or electrochemical systems Passion for working across functions—lab, literature, computation, and real-world application Exposure to characterization techniques (SEM, XRD, EIS, etc.) is a plus Curious, resourceful, and proactive learner Bonus: Some coding or simulation experience (Python, MATLAB, COMSOL, or PyBaMM) Why Join Us? Work directly with founders and senior researchers on cutting-edge battery R&D Shape the direction of innovation in a fast-moving deep-tech environment Access to global collaborators and exposure to full-cycle battery development Flexible and growth-focused work culture

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Preferred Qualifications: Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 8+ years of Hardware Engineering or related work experience. 2+ years of experience with circuit design (e.g., digital, analog, RF). 2+ years of experience utilizing schematic capture and circuit simulation software. 2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. 1+ year in a technical leadership role with or without direct reports. Principal Duties and Responsibilities: Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Integrates complex features and functionality into hardware designs in line with proposals or roadmaps for complex products. Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area. Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality. Evaluates, characterizes, and develops the novel manufacturing of solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules. Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues. Writes detailed technical documentation for complex Hardware projects. Level of Responsibility: Works independently with minimal supervision. Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Category Engineering Hire Type Employee Job ID 12211 Remote Eligible No Date Posted 21/07/2025 Alternate Job Titles: Senior Digital Design Engineer ASIC Design Engineer High-Speed SerDes Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced ASIC Digital Design Engineer with a strong background in digital design for high-speed serial interfaces. You have a deep understanding of USB, PCIe, Ethernet, Display, and HDMI protocol standards, and you thrive in a collaborative environment. Your expertise in Verilog RTL design, microarchitecture, and timing constraints development makes you a valuable asset to any team. You are adept at using tools like Spyglass for CDC/RDC/Lint and have excellent debugging skills. Your ability to propose and implement design updates based on various requirements, coupled with your experience in test coverage and physical design timing closure, sets you apart as a leader in your field. With a passion for innovation and a keen eye for detail, you are ready to take on new challenges and contribute to the success of Synopsys. What You’ll Be Doing: Driving and working on digital design for high-speed serial interface PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Proposing micro-architecture of design/design updates based on customer requirements, analog requirements, system performance improvements, Link layer interface changes, or overall robustness of design. Implementing RTL in Verilog and running Spyglass CDC/RDC/Lint. Collaborating with verification teams to test desired functionality and corner cases. Developing timing constraints, DFT insertion, and test coverage, and closing timing with physical design teams. Well versed in Micro-Architecture and Block Ownership, Design from scratch. The Impact You Will Have: Enhancing the performance and reliability of high-speed serial interface PHY IPs. Contributing to the development of cutting-edge technologies that power modern electronics. Driving innovation in digital design and influencing the future of semiconductor technology. Collaborating with cross-functional teams to deliver robust and high-quality designs. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous improvement and excellence. Supporting customers by providing high-performance and reliable IP solutions that meet their needs. What You’ll Need: 5-8 years of relevant experience in digital design for ASICs. Strong knowledge of Verilog RTL design and microarchitecture. Experience with timing constraints development and synthesis flow. Proficiency in using Spyglass or similar tools for Lint/CDC/RDC. Proficiency in scripting and automation using TCL, PERL, or Python. Excellent debugging skills and attention to detail. Who You Are: A collaborative team player with strong communication skills. A problem solver with a proactive approach to challenges. A detail-oriented professional with a passion for innovation. A self-motivated individual who thrives in a fast-paced environment. An adaptable engineer who can handle multiple tasks and priorities. The Team You’ll Be A Part Of: You will be part of the High-Speed SerDes Digital Design Team, a group of talented engineers dedicated to developing high-performance serial link PHY IPs. The team focuses on innovation, quality, and collaboration to deliver industry-leading solutions. Together, you will work on challenging projects that push the boundaries of technology and make a significant impact on the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Dear Connections, We are Hiring " Position: RTL Design Engineer" Location: Ahmedabad and Noida (No other locations will be considered) Start Date: Immediate or Aug Experience: 3- 8 Years without any training or internship Job Description: Expertise and strong hands-on experience in RTL design using System Verilog or VHDL Digital system architecture, Processor subsystem architecture and block definition Experience working on complex SoCs RTL design quality analysis – Lint, CDC, RDC Good understanding of digital design Synthesis, DFT and Static Timing Analysis Basic understanding of mixed-signal designs Experience with gate level simulations [GLS] and debug Experience in digital verification is a plus Strong written and verbal communication skills If you are looking for job change share your updated resume to vagdevi@semi-leaf.com “Your reference would be greatly appreciated”

Institute Description Indian Institute of Science Education and Research (IISER), Thiruvananthapuram is an autonomous institution dedicated to scientific research and science education of international standards. Role Description This is a full-time on-site role for a Postdoctoral Researcher at IISER Thiruvananthapuram. The Postdoctoral Researcher will be responsible to utilize Machine Learning (ML) or DFT and apply them in cross-coupling reactions. Qualifications Ph.D. in a related field. Experience in ML or experience in DFT compulsory. Knowdledge in PyTorch and deep learning is advantageous. Apply Here https://forms.gle/3ZMfRtbzdPvnVVnW7

The culture at our organization is defined by the people who contribute to it. We foster a culture of passion for technology solutions that have a tangible impact on businesses. Additionally, we prioritize the pursuit of individual passions by our team members. Collaborating with us offers you the opportunity to gain a deep understanding of various industries and cutting-edge technologies. This knowledge enables us to develop forward-thinking and impactful solutions. Moreover, being a part of MarvyLogic can facilitate personal growth, leading you towards a more enriching and fulfilling life. To be considered for this role, you should possess the following qualifications: - A minimum of 10 years of experience in FPGA Design and Debug, preferably working with Xilinx Ultrascale+ and Virtex7 - Proficiency in utilizing tools such as Xilinx Vivado/Coregen/Synplify and developing/maintaining Timing/IO constraints (UCF) - Experience with managing multiple high-speed clock domains and integrating third-party IP onto Xilinx transceivers - Familiarity with working on FMC daughter-cards, High-Speed Cables/Connectors, etc. - Extensive debugging experience using Xilinx ILA, Protocol Analyzers, Oscilloscope, Logic Analyzers, etc. - Proficiency in PERL/TCL scripting and database management between FPGA and ASIC RTL - Knowledge of front-end RTL tools such as RTL Simulation, Synthesis, DFT, Timing - Ability to modify/adapt RTL designs for FPGA implementation and optimize designs to achieve FPGA area/performance goals - Collaboration with DV and Firmware/Software teams throughout the validation process, including post-silicon bring-up Your responsibilities in this role will include: - Effectively collaborating and communicating with multi-site teams - Reviewing FPGA netlist releases (block/chip) and overseeing ASIC product life cycle stages, including requirements, design, implementation, testing, and post-silicon validation If you meet the specified qualifications and are ready to take on these responsibilities, we welcome you to apply for this challenging and rewarding opportunity.,