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Design Verification Manager

7 years

0 Lacs

Hyderabad Telangana India

Posted:1 day ago| Platform: Linkedin logo

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Skills Required

design verification ip verilog interface uart usb coding test strategies cadence synopsys simulation unix linux python script synthesis

Work Mode

On-site

Job Type

Full Time

Job Description

Design Verification Manager


We need an experienced DV lead/manager to verify IP/SoC using System Verilog/UVM


Exposure to various interface IP like I2C/SPI/UART/USB/NVM/PCIe; Buses AXI/AHB/APB; ARM based SoC designs is needed.


Skills:

  • Overall 7+ years industry experience with 5+ years in Design Verification using System-Verilog/C/UVM.
  • Generic knowhow on Digital Design and Verification methodologies.
  • Experience in System Verilog/UVM based IP/SoC verification using advanced technologies.
  • Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement
  • Proficient in EDA tools used for Design Verification (e.g. Cadence/Mentor/Synopsys simulation suites; Verilator).
  • Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability.
  • Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills


Traits:

  • Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.
  • Solutions orientation; Quality driven; Execution minded

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