705 Uvm Jobs - Page 13

Our Company Were Hitachi Vantara, the data foundation trusted by the worlds innovators. Our resilient, high-performance data infrastructure means that customers from banks to theme parks can focus on achieving the incredible with data. If youve seen the Las Vegas Sphere, youve seen just one example of how we empower businesses to automate, optimize, innovate and wow their customers. Right now, were laying the foundation for our next wave of growth. Were looking for people who love being part of a diverse, global team and who get excited about making a real-world impact with data. RoleSAN Storage Administrator Migration & Replication Specialist : Minimum 6 years of total IT experience with at least 5 years in SAN storage Replication/ Migration support . Should be willing to work in-office in BKC, Mumbai on a 24x7 rotational shift Key Responsibilities: Manage and support SAN environments with at least 5-10 years of hands-on experience in L2 support, focused on SAN migrations and replications . Execute and lead block-level data migrations using tools like UVM, NDM, etc. Handle file-level data migrations and understand best practices. Design and implement storage infrastructure solutions across block, file, and object storage. Create Low-Level Designs (LLDs) and detailed implementation plans. Understand and work with 2DC and 3DC storage architectures . Implement and manage director-class fabric networks (Cisco, Broadcom/Brocade). Use replication technologies including remote/in-system replication, snapshots, and clones . Handle day-to-day storage operations across block, file, and object platforms. Engineering degree About us Were a global team of innovators. Together, we harness engineering excellence and passion for insight to co-create meaningful solutions to complex challenges. We turn organizations into data-driven leaders that can a make positive impact on their industries and society. If you believe that innovation can inspire the future, this is the place to fulfil your purpose and achieve your potential. #LI-RS1 Championing diversity, equity, and inclusion Diversity, equity, and inclusion (DEI) are integral to our culture and identity. Diverse thinking, a commitment to allyship, and a culture of empowerment help us achieve powerful results. We want you to be you, with all the ideas, lived experience, and fresh perspective that brings. We support your uniqueness and encourage people from all backgrounds to apply and realize their full potential as part of our team. How we look after you We help take care of your today and tomorrow with industry-leading benefits, support, and services that look after your holistic health and wellbeing. Were also champions of life balance and offer flexible arrangements that work for you (role and location dependent). Were always looking for new ways of working that bring out our best, which leads to unexpected ideas. So here, youll experience a sense of belonging, and discover autonomy, freedom, and ownership as you work alongside talented people you enjoy sharing knowledge with. Were proud to say were an equal opportunity employer and welcome all applicants for employment without attention to race, colour, religion, sex, sexual orientation, gender identity, national origin, veteran, age, disability status or any other protected characteristic. Should you need reasonable accommodations during the recruitment process, please let us know so that we can do our best to set you up for success.

Educational requirement Bachelor or Masters in EE/ECE/CS or related specializations with 3+ years of relevant experience.Strong in UVM/System Verilog/C/C++/scripting, Simulation, Formal verification. Good understanding of SoC architectures Required Candidate profile GLS verification experience at Core level. SV - UVM understanding. Scripting in perl, python. Debug of complicated designs using Verdi. Power aware verification, SDF / timing simulation.

Proficient in Verilog-AMS, System Verilog, and UVM methodologies Experience with Cadence Spectre or similar AMS simulation tools Strong understanding of analog circuit design principles (op-amps, transistors, etc.) What You Need to Be Successful: Proficient in Verilog-AMS, System Verilog, and UVM methodologies Bonus Points if You Have: Experience with Cadence Spectre or similar AMS simulation tools Strong understanding of analog circuit design principles (op-amps, transistors, etc.) What Makes You Eligible: An accomplished leader with a minimum of 8+ years of experience in software design & development and a Bachelor's / Master's degree Excellent communication skills (written/verbal) & team spirit Risk taker with passion for innovation Autonomous working to explore new technologies

Position: RTL Verification Experience: 5+ Years Location: Hyderabad Skill Required: System Verilog and UVM, HW Testing, PCIe/SPI/I2C/, Perl, Python or TCL If interested to send your updated resume to irfanai@canvendor.com / reach out to 9585544407

- Lead the architecture, design and development of Processor Core Vector- Scalar Execution unit for high-performance IBM Systems. - Architect and design Fixed point/Floating point/Vector/SIMD/Crypto instructions of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise - 8 or more years of demonstrated experience in architecting and designing Execution unit of CPU - Hands on experience of implementing Arithmetic/Crypto/SIMD functions - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of instruction dispatch and load/store units - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of one object oriented language and scripting language - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Master's Degree/PhD

Opportunity for a talented individual for their memory interface products. We are looking for a candidate with a strong background in verifying complex integrated circuits. The candidate needs to have skills that are up to date with the latest IC verification tools and flow. The candidate will work closely with design, and verification engineering. In addition, strong collaboration and communication skills are a must. Duties/Responsibilities: Develop verification testbench components for chip/module level using SystemVerilog. Use high-level concepts (Object-oriented, UVM, etc) to develop an extendable environment. Define and execute detailed verification plan from spec working with architects and designer engineers Incorporate code coverage, functional coverage, assertions, cover groups, etc to achieve 100% verification completeness before tape-out. Debug tests, and regression failures. Participate in silicon debugging and analysis. Qualifications MS in Computer or Electrical Engineering with a minimum of 5+ years of experience in design/verification management of highly complex projects. Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required. Must be good in building verification environments preferably using the verification subset of high-level languages like System Verilog (UVM). Understanding or prior experience with Industry standard protocols like DDR4/DDR5 is preferred. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based onImplementation means trying, testing, and improving outcomes until a final solution emerges. Knowledge means exchange discussions with colleagues from all over the world. Join our team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation. We make real what matters. This is your role! Questa verification IP’s help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and improve these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will cooperate with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We don’t need superheroes, just super minds We seek a graduate with an Electronics Engineer (B.Tech/ M.Tech) or related field from a reputed institute Phenomenal knowledge of verification engineering and have between 2 - 8 years of working experience as well. We value sound knowhow of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. Knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. You are a phenomenal teammate, resilient and candid, Enjoy learning new things and build knowledge base in new area. We’ve got quite a lot to offer. How about you This role is based in Noida but you’ll get the chance to work with teams impacting entire cities, countries – and the shape of things to come. The pace of innovation in electronics is constantly accelerating. To enable our customers to deliver life-changing innovations to the world faster and to become market leaders, we are committed to delivering the world’s most comprehensive portfolio of electronic design automation (EDA) software, hardware, and services. We, at Siemens EDA enable companies to develop better electronic products faster and more efficiently. Our innovative products and solutions help engineers conquer design challenges in the increasingly sophisticated worlds of board and chip design We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-EDA #LI-Hybrid

Bachelors or Masters degree in Electrical, Electronics or VLSI Engineering Expertise in DFX Verification preferred Expertise in DFT / ASIC Verification Expertise in System Verilog Expertise in UVM Expertise in python or perl scripting Expertise in verifying JTAG, scan chains, MBIST, LBIST, boundary scan and related test logic for large complex SoCs. Expertise in simulation tools like VCS, Questa, XSIM Excellent knowledge on RTL and DFT concepts Prior experience in Post-silicon validation is an added advantage Prior experience on automotive or AI SoCs is an added advantage Preferred resources with valid regional work permit

We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to handle the challenging problems in future technologies and designs. We are also looking for candidates with Strong C/C++background to lead our leading-edge algorithmswithin our EDA solutions to increase our design team’s productivity and chip quality and performance. Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world. We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Strong interpersonal skills are needed to coordinate deliverables and requirements from several areas within and outside of the organization.There are many opportunities to gain and utilize a deep understanding of future issues and provide input towards decisions affecting system development, logical and physical design as well as sophisticated methodology directions. Individuals who are chosen to become a part of our world class development teams will be helping advance IBM’s leadership in developing the highest performing computers and changing hardware solutions. Do you want to be an IBMerCome THINK with us! Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4+ years of IT experience Strong C/C++programming skills in a Unix/Linux environment is a must. VLSI knowledge, Knowledge in front end simulation tool development and UVM libraries isadditional plus. Great scripting skills – Perl / Python/Shell Proven problem-solving skills and the ability to work in a team environment are a must Preferred technical and professional experience Simulation tool development, Front end verification flow, UVM , VLSI knowledge, VHDL/Verilog, computer architecture

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 1-3 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

About Marvell . Your Team, Your Impact The Data Centre Engineering Group develops Custom Silicon products tailored for the Data Centre market, focusing on cutting-edge Accelerated Infrastructure solutions for Networking, Switching, Connectivity, and Compute. The team works on high-performance and scalable architectures, ensuring optimized performance, power efficiency, and reliability to meet evolving data center demands. By collaborating across multiple teams, the group delivers best-in-class silicon solutions that drive innovation in next-generation data center applications. What You Can Expect Develop the architecture for a functional verification environment, including reference models, bus-functional monitors, and drivers Contribute to the development methodology and extend RoCE-related learnings within the team Write comprehensive verification test plans using random techniques and coverage analysis, in collaboration with design teams Develop test cases and tune the environment to meet coverage goals; debug failures and work with designers to resolve issues Verify boot code and architect, develop, and maintain tools to streamline the design of advanced multi-core SoCs Translate engineering requirements into scalable and user-friendly software tools optimized for highly parallel compute environments Perform unit and regression testing of developed software tools What Were Looking For BS in Computer Engineering, Electrical Engineering, or Computer Science with 15+ years of verification or design experience, or MS/PhD with 10+ years of experience Hands-on expertise in RoCE (RDMA over Converged Ethernet) Strong experience with SystemVerilog and UVM Proven ability to write detailed test plans and develop sophisticated directed and random verification environments Proficiency in scripting languages such as Python or Perl, and familiarity with EDA verification tools Experience with object-oriented design and implementation Good understanding of Linux operating systems Solid programming skills, especially in C++ and ARM assembly Working knowledge of high-speed Ethernet Understanding of other networking protocols is a plus Diligent, detail-oriented, and proactive, with the ability to manage tasks independently Open to feedback and able to work with diverse perspectives Flexible and adaptable; quick to learn in a fast-paced environment Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-KP1

As a Logic design lead in the IBM Systems division, you will be responsible for the micro architecture, design and development of a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems. Design and architect different interconnect topologies as driven by bandwidth, latency and RAS requirements Develop the features, present the proposed architecture in the High level design discussion Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of relevant experience - At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC). - Expertise of SMP coherency - Experience in different on-chip interconnect topologies (e.g., mesh, crossbar) - Understanding of various snoop and data network protocols - Understanding of latency & bandwidth requirements and effective means of implementation - Working knowledge of queuing theory - numa/nuca architecture - Proficient in HDLs- VHDL / Verilog - Experience in High speed and Power efficient logic design -Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage - Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design - Experience in leading uarch, RTL design teams for feature enhancements.

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

The position involves designing, developing and deploying UVM based reusable testbenches for RTL unit blocks, sub-system level and top level systems with emphasis on verifying the functionality and generating the code/functional coverage reports. The candidate should come up with test plans and test cases in order to achieve 100% code coverage and functional coverage. Educational Qualification: Bachelor major in electronics, embedded programming, ECE, EEE. Key Requirements: Experience in ASIC/FPGA verification using System Verilog. Develop and sign off on test plans and test cases. Strong knowledge of digital design, Verilog, System Verilog, UVM, C/C++. Experience in AMBA AHB/AXI/APB based IPs design/verification. Experience in usage of assertions, constrained random generation, functional and code coverages. Experience in FPGA design and FPGA EDA tools will be a plus. Experience in scripting, such as TCL, Perl, Bash and python to automate the verification methodologies and flows. Able to build and set up scalable simulation / verification environments.

Roles and Responsibilities Independent Verification Ownership of IP DV. Collaborating with various across functional team at multiple geo location as part of execution. Expected to work hands on to close all aspects of verification activities including Testplan creation, building testbenches based on standard DV methodology, developing DV Infrastructure (Coverage/Regression/Simulation Scripts) Must have experience in developing test benches for IP/Subsystems/SoC. In depth knowledge and hands on experience in the execution of verification of SoC/SS/IP DV Previous experience of independently driving IP DV projects from Ability to lead a team by providing technical guidance as well as by part of execution by debugging and SoC architecture understanding capabilities Strong hands on experience with common verification tools and methodology including UVM/System Verilog/CDV/MDV, DV signoffs Must have a strong domain expertise in one or more following areas - CPU/Cache Coherency/CPU Pipeline/Cache/Branch Prediction/MMU Experience in Hybrid testbenches (SV, C/C++, Python) and C/C++ based CPU vectors/stimulus based verification is desirable Experience/Exposure to RISC-V Core DV or any other Core DV is highly preferred Experience - 7-10 Years Qualifications B.Tech/B.E/M.Tech/M.E

Grow with us About this opportunity We are seeking a Tech Lead FPGA/ASIC Verification to join the Ericsson Silicon organization. In this key role, you will provide strategic leadership to a team of dedicated engineers focused on developing world-class Radio and RAN Compute products. You will lead the FPGA verification team in defining, implementing, and optimizing verification strategies and environments for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking What you will do Lead the definition of advanced verification requirements and strategies for FPGA and/or ASIC designs based on functional specifications and Ericsson development processes. Architect and implement comprehensive verification environments and test cases to execute verification plans, ensuring high quality deliverables. Analyze and optimize functional and code coverage metrics, driving towards completion targets and continuous improvement. Debug RTL in collaboration with designers, Collaborate with hardware, software, systems, and integration teams to understand overall product requirements and drive strategic and efficient solutions. Champion the continuous improvement of products, tools, and processes, contributing thought leadership and innovative ideas. Produce and oversee the generation of comprehensive verification documentation, ensuring clarity and precision including test procedures and results documentation. Devise test plans that cover functional verification and on target lab verification. Provide mentoring and guidance to team member. You will bring 10+ years of experience in FPGA/ASIC verification, including leadership roles. Exceptional knowledge of UVM and SystemVerilog Proven ability to architect and create RTL testbenches from scratch, demonstrating advanced technical skills. Strong knowledge of object-oriented programming and embedded software design and testing. Expertise with modern FPGA device families and tools Experience with scripting languages such as Python, Tcl, shell scripting, etc. An analytical and strategic approach with a results-oriented mindset and the ability to deliver under pressure. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelors degree in Electrical or Computer Engineering or equivalent. Why join Ericsson What happens once you apply Primary country and city: India (IN) || Bangalore Req ID: 768586

Grow with us About this opportunity We are seeking a Tech Lead FPGA/ASIC Verification to join the Ericsson Silicon organization. In this key role, you will provide strategic leadership to a team of dedicated engineers focused on developing world-class Radio and RAN Compute products. You will lead the FPGA verification team in defining, implementing, and optimizing verification strategies and environments for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking What you will do Lead the definition of advanced verification requirements and strategies for FPGA and/or ASIC designs based on functional specifications and Ericsson development processes. Architect and implement comprehensive verification environments and test cases to execute verification plans, ensuring high quality deliverables. Analyze and optimize functional and code coverage metrics, driving towards completion targets and continuous improvement. Debug RTL in collaboration with designers, Collaborate with hardware, software, systems, and integration teams to understand overall product requirements and drive strategic and efficient solutions. Champion the continuous improvement of products, tools, and processes, contributing thought leadership and innovative ideas. Produce and oversee the generation of comprehensive verification documentation, ensuring clarity and precision including test procedures and results documentation. Devise test plans that cover functional verification and on target lab verification. Provide mentoring and guidance to team member. You will bring 10+ years of experience in FPGA/ASIC verification, including leadership roles. Exceptional knowledge of UVM and SystemVerilog Proven ability to architect and create RTL testbenches from scratch, demonstrating advanced technical skills. Strong knowledge of object-oriented programming and embedded software design and testing. Expertise with modern FPGA device families and tools Experience with scripting languages such as Python, Tcl, shell scripting, etc. An analytical and strategic approach with a results-oriented mindset and the ability to deliver under pressure. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelors degree in Electrical or Computer Engineering or equivalent. Why join Ericsson What happens once you apply Primary country and city: India (IN) || Bangalore Req ID: 768584

Mesh / Coherency Design Verification Engineer in Pune, MH, India Mesh / Coherency Design Verification Engineer Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team we d love to have you apply. Come invent the future with us. About the role: You will work on the verification of a server-class microprocessor-based CPU/Coherent Mesh interconnect. Youll be involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of microprocessors. Youll also partner with other teams to accelerate post-silicon validation and debug of the product. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. Define requirements for block level and subsystem level testing infrastructure Create test plans for unit-level and chip-level verification and post-silicon validation Architect, design and implement test benches and other components of design verification environment Create random test generators to find bugs in design Debug failures and drive speedy resolution of bugs Create coverage monitors and drive coverage to required quality targets Define post-silicon validation plans, and engage in post-silicon activities to accelerate product launch Lead verification activities within a team and guide other engineers to achieve project goals M.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 5+ years of semiconductor experience Solid understanding of high-performance microprocessor architecture concepts Experience using industry standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools Experience developing verification environments in one or more industry standard languages like SVTB UVM/OVM Programming experience in languages common to the industry (e.g., C, C++, Perl, Python) Experience in automating design, verification, and validation tasks Hands on experience in post-silicon validation Knowledge of ARM or x86 architecture and assembly language programming Previous experience in CPU/core design verification is preferred Previous experience in Network-on-chip (NoC) design verification is preferred Previous experience with Arm AMBA (APB/AHB/AXI/ACE/CHI) protocols is preferred Previous experience with formal verification is preferred What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Mesh / Coherency Design Verification Engineer in Pune, MH, India Mesh / Coherency Design Verification Engineer Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: You will work on the verification of a server-class microprocessor-based CPU/Coherent Mesh interconnect. Youll be involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of microprocessors. Youll also partner with other teams to accelerate post-silicon validation and debug of the product. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. Define requirements for block level and subsystem level testing infrastructure Create test plans for unit-level and chip-level verification and post-silicon validation Architect, design and implement test benches and other components of design verification environment Create random test generators to find bugs in design Debug failures and drive speedy resolution of bugs Create coverage monitors and drive coverage to required quality targets Define post-silicon validation plans, and engage in post-silicon activities to accelerate product launch Lead verification activities within a team and guide other engineers to achieve project goals M.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 5+ years of semiconductor experience Solid understanding of high-performance microprocessor architecture concepts Experience using industry standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools Experience developing verification environments in one or more industry standard languages like SVTB UVM/OVM Programming experience in languages common to the industry (e.g., C, C++, Perl, Python) Experience in automating design, verification, and validation tasks Hands on experience in post-silicon validation Knowledge of ARM or x86 architecture and assembly language programming Previous experience in CPU/core design verification is preferred Previous experience in Network-on-chip (NoC) design verification is preferred Previous experience with Arm AMBA (APB/AHB/AXI/ACE/CHI) protocols is preferred Previous experience with formal verification is preferred What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Mesh / Coherency Design Verification Engineer in Bangalore, KA, India Mesh / Coherency Design Verification Engineer Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: You will work on the verification of a server-class microprocessor-based CPU/Coherent Mesh interconnect. Youll be involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of microprocessors. Youll also partner with other teams to accelerate post-silicon validation and debug of the product. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. Define requirements for block level and subsystem level testing infrastructure Create test plans for unit-level and chip-level verification and post-silicon validation Architect, design and implement test benches and other components of design verification environment Create random test generators to find bugs in design Debug failures and drive speedy resolution of bugs Create coverage monitors and drive coverage to required quality targets Define post-silicon validation plans, and engage in post-silicon activities to accelerate product launch Lead verification activities within a team and guide other engineers to achieve project goals M.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 5+ years of semiconductor experience Solid understanding of high-performance microprocessor architecture concepts Experience using industry standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools Experience developing verification environments in one or more industry standard languages like SVTB UVM/OVM Programming experience in languages common to the industry (e.g., C, C++, Perl, Python) Experience in automating design, verification, and validation tasks Hands on experience in post-silicon validation Knowledge of ARM or x86 architecture and assembly language programming Previous experience in CPU/core design verification is preferred Previous experience in Network-on-chip (NoC) design verification is preferred Previous experience with Arm AMBA (APB/AHB/AXI/ACE/CHI) protocols is preferred Previous experience with formal verification is preferred What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Mesh / Coherency Design Verification Engineer in Bangalore, KA, India Mesh / Coherency Design Verification Engineer Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team we d love to have you apply. Come invent the future with us. About the role: You will work on the verification of a server-class microprocessor-based CPU/Coherent Mesh interconnect. Youll be involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of microprocessors. Youll also partner with other teams to accelerate post-silicon validation and debug of the product. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. Define requirements for block level and subsystem level testing infrastructure Create test plans for unit-level and chip-level verification and post-silicon validation Architect, design and implement test benches and other components of design verification environment Create random test generators to find bugs in design Debug failures and drive speedy resolution of bugs Create coverage monitors and drive coverage to required quality targets Define post-silicon validation plans, and engage in post-silicon activities to accelerate product launch Lead verification activities within a team and guide other engineers to achieve project goals M.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 5+ years of semiconductor experience Solid understanding of high-performance microprocessor architecture concepts Experience using industry standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools Experience developing verification environments in one or more industry standard languages like SVTB UVM/OVM Programming experience in languages common to the industry (e.g., C, C++, Perl, Python) Experience in automating design, verification, and validation tasks Hands on experience in post-silicon validation Knowledge of ARM or x86 architecture and assembly language programming Previous experience in CPU/core design verification is preferred Previous experience in Network-on-chip (NoC) design verification is preferred Previous experience with Arm AMBA (APB/AHB/AXI/ACE/CHI) protocols is preferred Previous experience with formal verification is preferred What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Rivos is on a mission to build the best enterprise SOCs in the world with class leading performance, power, security and RAS features. We are seeking Memory Controller design verification engineers to join our team in building the best high performance memory interface in the world. As a memory subsystem design verification engineer, youll be responsible for all aspects of digital verification such as functional, performance, DFD and DFT features around DDR and HBM memory subsystem designs. Responsibilities Work closely with architect and design team to verify the feature sets of the DDR and HBM memory subsystem design Work closely with 3rd party IP vendors to validate the correctness of integration and custom features. Develop testplan and testbench Integrate and bring up VIPs such as DDR_PHY, DDR_Model as part of testbench Develop test stimulus, checkers and scoreboard in SystemVerilog/UVM Debug, regression and coverage closure Provide debug support to emulation and silicon-bring up teams. Able to work with teams across the continents Key Qualifications Hands-on experience of verifying digital logic portion of DDR/HBM memory subsystem design Knowledge in JEDEC specification of LPDDRx/DDRx/HBMx Knowledge in the DDR DFI specification and protocol Knowledge in Reliability, availability and serviceability (RAS) features in the context of memory subsystem such as Error detection/correction and Encryption Education and Experience Master s Degree or Bachelor s Degree with 3-5 years of experience

Grow with us About this opportunity We are seeking a Tech Lead FPGA/ASIC Verification to join the Ericsson Silicon organization. In this key role, you will provide strategic leadership to a team of dedicated engineers focused on developing world-class Radio and RAN Compute products. You will lead the FPGA verification team in defining, implementing, and optimizing verification strategies and environments for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking What you will do Lead the definition of advanced verification requirements and strategies for FPGA and/or ASIC designs based on functional specifications and Ericsson development processes. Architect and implement comprehensive verification environments and test cases to execute verification plans, ensuring high quality deliverables. Analyze and optimize functional and code coverage metrics, driving towards completion targets and continuous improvement. Debug RTL in collaboration with designers, Collaborate with hardware, software, systems, and integration teams to understand overall product requirements and drive strategic and efficient solutions. Champion the continuous improvement of products, tools, and processes, contributing thought leadership and innovative ideas. Produce and oversee the generation of comprehensive verification documentation, ensuring clarity and precision including test procedures and results documentation. Devise test plans that cover functional verification and on target lab verification. Provide mentoring and guidance to team member. You will bring 10+ years of experience in FPGA/ASIC verification, including leadership roles. Exceptional knowledge of UVM and SystemVerilog Proven ability to architect and create RTL testbenches from scratch, demonstrating advanced technical skills. Strong knowledge of object-oriented programming and embedded software design and testing. Expertise with modern FPGA device families and tools Experience with scripting languages such as Python, Tcl, shell scripting, etc. An analytical and strategic approach with a results-oriented mindset and the ability to deliver under pressure. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelors degree in Electrical or Computer Engineering or equivalent. Primary country and city: India (IN) || Bangalore Req ID: 768584

Responsibilities As a creative design engineer with a knowledge of subsystems and SoCs you will be part of a team developing Subsystems & SoCs. You will work the Architecture team to gather the requirements and develop Micro-architecture specifications for one or more SOC Infrastructure areas such as Power management, Debug, Clocks, Resets. Your key responsibilities will include writing micro-architecture specifications, developing the RTL, fixing bugs and running various design checks. You will work with the verification team to review test plans, and help debug design issues. You will work with the Power and Performance analysis team to evaluate and improve Subsystem/SOC PPA. You will also contribute to developing and enhancing the design methodologies used by the team. You will guide and support other members of the team as needed to enable the successful completion of project activities. You will balance other opportunities such as working with Project Management on activities, plans, and schedules Required Skills and Experience: In addition to bringing your accomplishment of either Bachelors or Master s degree or equivalent experience in Computer Science or Electrical/Computer Engineering. Experience of 5+ years working in design of complex compute subsystems or SoCs, you will need: Expertise in creating Micro-architecture and Design specifications for the SoC Infrastructure areas such as Power management, Debug, Clocks and Resets. Strong knowledge of digital hardware design and Verilog HDL. A thorough understanding and experience of the current design techniques for complex SoC development. Experience leading and developing RTL for Subsystems or SoCs. Conversant with Lint, CDC and RDC flows. Good communication (written, verbal, presentations) skills. Experience with Perl, Python or other scripting language Desired Skills and Experience: Experience with ARM-based designs and/or ARM System Architectures Experience developing subsystems for PCIe, LPDDR, HBM, UCIe, Ethernet Experience with SystemVerilog and verification methodologies UVM/OVM Experience leading small teams or projects Experience or knowledge in the following areas Synthesis and timing analysis Static design checks, including CDC, RDC, X-Propagation, Linting Power management techniques DFT and physical implementation #LI-KR2 Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm

Expertise in ASIC verification, Expertise in System Verilog and UVM, Verilog. Experience in technical lead , leading a team of 2-5 engineers. Expertise in IP level verification, testbench architecture development, Testbench component developments. Expertise in coverage closer, code coverage, functional coverage Experience in Gate level simulations. The candidate should be able to define verification plan, create testbenches, testcases,gate level simulations etc independently. Knowledge on serial protocols PCIe, USB, UFS Knowledge on scripting languages like Python, Perl etc. Keen on continuous process improvement to improve Quality and time