939 Uvm Jobs - Page 16

About Marvell . Your Team, Your Impact Infrastructure Processor Business Unit, a part of Networking and Processor Business Group, encompasses OCTEON and the award-winning OCTEON Fusion-M product families. The SoC family of multi-core CPU processors and Radio Access SoCs offer best-in-class performance, low power, rich software ecosystem, virtualization features, and open source application support with highly optimized custom ARM CPU cores providing an excellent solution for a highly flexible end-to-end optimized 5G platform. As part of the Infrastructure Processor unit at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers specifications, whether they re a major telecom organization or automotive company, etc. What You Can Expect - Individual contribution for the block, SoC, and subsystem-level verification. - Develop a test bench, test plan, and design a verification environment at the block and full chip levels. - Technically, lead junior engineers. What Were Looking For - Must have a good digital logic and the fundamentals of digital design verification. - The candidate must have excellent skills in digital logic verification and hardware description language - Must have worked on SoC, subsystem-level verification. - Knowledge in object-oriented programming using languages such as SystemVerilog and UVM methodology is an added advantage. - Must be familiar with verification test planning, test execution, and sign-off for the verification activity. - Must have good experience in using simulation tools and proficiency in simulation debug techniques. - Strong knowledge/experience in building the verification environment. Must have hands-on knowledge of test-bench development and automation, bug tracking, and regression mechanisms - Should be able to act as the team lead to determine methods and procedures for new assignments and coordinate activities of other team members to ensure successful project completion. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

Experience with OVM/UVM/VMM/Test Harness, developing assertions, checkers, coverage, and scenario creation.,min 2 to 3 SoC Verification projects.developing test and coverage plans, verification environments, and validation plans,

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running.The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise Join Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, weve united two industry leaders to create an optical networking powerhousecombining cutting-edge technology with proven leadership to redefine the future of connectivity. Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group. As an FPGA Verification engineer, you will be responsible for designing verification plans, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up to ensure first time right quality of Infinera product. Candidate should be capable of handling projects independently and have a strong will to drive for solutions. Must have 12 16 yearsof experience in developing System Verilog UVM based test environments, developing and implementing test plans at block, sub-chip and chip levels. Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform-based debugging tools. Exposure to UVM (or similar) verification methodologies is required. Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. Working knowledge of RTL design is preferred. Should be conversant with technologies like the Ethernet, PCIe, I2C, SPI etc. Knowledge of telecom protocol is preferred. Structured and thorough with analytical and troubleshooting skills. Good written and oral communication skills are required. Flexible, innovative, self-driven and willing to take initiatives. Highly motivated team player with exceptional leadership capability. Develop and execute verification plans for high-complexity DWDM systems used in LH/ULH optical network applications. Design and implement simulation environments and testbenches to validate FPGA functionality and performance. Create and run functional and directed/random test scenarios to ensure comprehensive design coverage. Perform detailed coverage analysis and implement strategies to achieve full functional and code coverage. Collaborate closely with cross-functional R&D teams across multiple global locations throughout the product lifecycle. Provide lab support during board bring-up and assist in root cause analysis to ensure first-time-right product quality. Independently manage verification projects with a proactive and solution-driven approach to meet quality and timeline goals.

NVIDIA needs a Senior Custom SOC/IP Verification Engineer for next-gen solutions. Seeking hard-working individuals to build life-changing custom SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What youll be doing: Lead ASIC design verification for various processing blocks in a SOC, including planning, execution, Coverage and methodology development. Collaborate with multiple teams (Architecture, SW/FW, Design, Modeling, Emulation, Post-Silicon Validation) to ensure comprehensive verification plans. Support engineering teams in delivering solutions for purpose-built ASICs and collaborate with IP development teams for IP identification, selection, and licensing. Analyze SOC and IP architecture, develop verification plans, and establish performance metrics. Work with partners in a co-development environment during development, debug, and bringup. Plan tests, achieve coverage closure, and enable customer TB infrastructure. Validate use cases for power-on and boot requirements. What We Need To See: Proficient in design verification tools like Synopsys VCS, Cadence Xcelium Simulator, Verdi, JasperGold, and VC Formal. Consistent track record of first-pass success in ASIC Development. Holds a B. S. or M. S. degree in Computer Engineering or Electrical Engineering, with 7+ years of experience in ASIC, IP, or SoC design verification. Skilled in handling mixed language UVM and C++ testbenches, interpreting functional specs, and building comprehensive test plans. Experienced in developing tools and infrastructure using Perl or Python, with a strong background in AMBA protocols (AXI, ACE, CHI, ATB). Hands-on experience with subsystems in new technologies like ARM CPU, LPDDR, HBM, GPUs, DLA, PCIe, and Network on chip, including performance verification. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-Hybrid

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are now looking for passionate, highly motivated and creative individuals to be part of our automotive verification team. As a verification owner, you will work on projects that will define the next generation of automotive chips and systems. You will get firsthand exposure to high performance CPU and Memory sub-systems, NOC based Interconnect Fabric, High speed IOs and many other leading technologies deployed in our Tegra chips. What you will be doing: You will be responsible for creation of "state of the art" UVM based verification test benches and methodologies to verify complex IPs and Sub-systems. You will also get to work on System level verification using C/C++. During the course of a project you would end up driving the following aspects of verification for your unit: Architect the testbenches and craft verification environment using UVM methodology Define test plans, tests and verification infrastructure for modules, clusters and system Build efficient and reusable bus functional models, monitors, checkers and scoreboards Implement functional coverage and own verification closure Work with architects, designers, FPGA and post-silicon teams to ensure that your unit is robust What we need to see: You should be BTech/MTech with 5+ years of experience in verification closure of complex Unit, Sub-system or SOC level verification. If you have experience in at least a few of the following domains, we will have an excellent match for our needs: CPU verification, Memory controller verification, Interconnect verification High Speed IO verification (UFS/PCIE/XUSB) 10G/1G Ethernet MAC and Switch Bus protocols (AXI/APB) System functions like Safety, Security, Virtualization and sensor processing Experience in the latest verification methodologies like UVM/VMM Exposure to industry standard verification tools for simulation and debug is a requirement Exposure to Formal verification would be excellent Good debugging and analytical skills. Good interpersonal skills, ability to work as an excellent teammate with e xcellent communication skills to collaborate with cross-cultural teams and work in a matrix organization With highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If youre creative and independent, with a genuine real passion for technology, we want to hear from you. #LI-Hybrid

Job Description Must have: Must Have Required Expertise: Should be able to build test plan, tests, coverage assertions from Specification. Architect and build testbench and testbench components. Good in UVM,SV,C SVA. Familiar with industry protocols, such as AXI, APB, AHB, PCIe, SoC. Very good in debugging. Worked with industry standard EDA tools Synopsys, Cadance simulators and debugging tools. Good to have skills: Experience with scripting and automation. Demonstrated leadership and collaboration abilities, including mentoring, cross-functional communication, UPF-simulations, GLS and a proactive approach to automation. Exposure to SOC verification, Formal verification methodologies.

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers. Skills (competencies)

Role & responsibilities Test bench development and debug UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based testing. Coverage analysis (code, functional, assertion) Verification plan reviews, Verification reviews Back-annotated netlist simulation execution and debug Debug failing cases & Coverage improvements.

About the Role Skills: Strong in IP / SoC-level verification Responsibilities Proficient in testbench and testcase development (SystemVerilog/UVM preferred) Clear understanding of verification plans, coverage metrics, and debugging Experience: 5+ years in Design Verification Required Skills Strong in IP / SoC-level verification Proficient in testbench and testcase development (SystemVerilog/UVM preferred) Clear understanding of verification plans, coverage metrics, and debugging Availability: Immediate to within 4 weeks

Role & responsibilities Please interested candidate send me cv : galeiah.g@honeybeetechsolutions.com call me :7995220108. Client Name: Proxelera Industry: SEMICON Position Name SoC NoC Verification Engineer Job No : PROX-14080 Position type: Permanent Total Exp: 7+ years to 15y HBTS Budget: Open Notice Period: Immediate to 15days Work Location: Bangalore Job Description Must have: SoC NoC Verification Engineer with 7+ years of experience This role involves developing test plans, writing verification code, debugging issues, and collaborating with design teams to validate complex interconnect systems. Key Responsibilities Develop and execute verification plans for SoC and NoC architectures. Write and maintain test benches using SystemVerilog/UVM. Perform functional, performance, and power verification. Debug and resolve design and verification issues. Work with high-speed interconnect protocols (AXI, CHI, PCIe, Ethernet, CXL, UCIe). Work closely with design and architecture teams to ensure compliance with specifications. Client is looking for Network on chip , just look for the NoC verification AMD (Dont Share AMD Profiles) Preferred candidate profile

Responsibilities Understand the standards/specifications Architecture development and documenting implementation level details Hands on work for every aspect of verification cycle Responsible for the compliance with the latest Methodologies. Developing Verification IPs Define Functional Coverage matrix and Comprehensive Test plan Regression management and functional coverage closure DUT integration and verification for IP delivery sign-off Leading small team Person Specification Required Skills Hands-on experience of complete verification cycle with strong verification concepts Strong knowledge of Verilog, SystemVerilog and UVM Experience in UVM based Verification IP development Experience in AMBA AXI/AHB/APB System buses Hands on work experience on any of PCIe/Eth/USB/DDR etc. Hands on experience with System Verilog Assertions Scripting for automation, release process, simulations, regressions Good command over written and oral communication Desirable Skills Lead the Verification IP development with 2 or more junior engineers Exposure to full verification cycle Desired Skills and Experience DV Engineer, Design Verification, Verification Engineer

Role & responsibilities 7+ years of design verification experience. MS (or higher) in EE/EC/ECC Engineering As a member of the Design Verification [ Pre-Silicon DV ] Team for client WCS/SCE BU You will be responsible for verification of various IPs and/or SoC. Candidate must be self-motivated and capable of working independently or as part of a team You will implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will also assist with developing test-plans, debugging failures and analyzing coverage information. Must have excellent knowledge of computer architecture and design verification fundamentals Must have experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies Must have experience in developing complex test bench in System Verilog using OVM/ UVM methodology Hands-on experience in AMBA protocol, PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol Experience in Low Power Simulation/UPF setup, debug low power simulation failures. Exposure to scripting languages like Perl, Unix shell or similar languages Good to have some experience with assembly language programming required Excellent written and oral communication skills necessary

Experience : 3 to 10 Years Qualification : Bachelors or Masters (Electronics and Communication Engineering or equivalent) Job Description: As an Emulation Engineer, youll be an integral part of a dynamic team dedicated to creating cutting-edge ASIC solutions for High-Performance Computing (HPC) systems. Your role will involve defining the validation strategy leading to functional sign-off for these high-performance computing designs. Key functions and responsibilities: Proficient in various emulation technologies, including simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, and hybrid methods. Familiarity with tools such as Palladium, Protium, Veloce, or Zebu. Good Knowledge of SystemC/C/C++ and UVM/SV verification languages Experience with SystemVerilog and C++ for modelling RTL components and transactors. Ability to develop C/C++/SystemC/SV tests in HDL-HVL (Hardware Description Language-Hardware Verification Language) Co-emulation platforms. Understanding of compilation and build flow. Skilled at building images from scratch, making necessary design modifications to adapt to emulation. Work closely with verification teams to define and implement comprehensive pre and post silicon test plans. Interface effectively with design, verification, validation, and software development teams to understand their needs from an emulation perspective. Experience in architecting emulation systems for various design scales (IP blocks, SOC, multi-chip systems). Balancing performance and ease of debug. Proficient in post-silicon bring-up, debugging, and issue reproduction on emulators. Familiarity with Python and TCL scripting languages. Exposure to domains such as PCIe, CXL, DDR, Flash, Memory, USB, and CPU. Strong communication and collaboration skills to work effectively with cross-functional teams and domain experts. Successfully manage multiple design releases and provide support for debugging customer issues.

SOC Emulation Lead: THE ROLE: As an Emulation Verification Engineer in AMD s Server SoC team, you ll be at the forefront of validating next-generation server-class SoCs using advanced emulation platforms. Your mission: ensure AMD s silicon hits the ground running bug-free, high-performance, and server-grade reliable. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Bring-up and debug of large SoC designs on emulation platforms (e.g., Palladium, Veloce, Zebu). Develop and execute test plans to validate functionality, performance, and power on emulators. Create and integrate monitors, checkers, and assertions in SystemVerilog/UVM environments. Collaborate with cross-functional teams including RTL design, architecture, firmware, and post-silicon validation. Analyze failures, root-cause bugs, and drive fixes in pre-silicon environments. Maintain and enhance emulation infrastructure and workflows. PREFERRED EXPERIENCE: Strong experience in SystemVerilog, UVM, and emulation platforms. Proficiency in debugging tools and scripting languages like Python, Perl, or TCL. Familiarity with RTL design (Verilog/VHDL) and simulation tools. Solid understanding of SoC architecture, memory protocols, and interface standards. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #L1-RG2 #hybrid Benefits offered are described: AMD benefits at a glance .

We are seeking a skilled SoC Frontend Design Engineer to join our integrated circuit (IC) design team. Will be focusing on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for ASIC projects. Work closely with cross-functional teams to deliver high-quality and efficient SoC (System on Chip) designs. This role requires good knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging. You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred) 3+ years of experience in RTL design and digital logic design. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies Familiarity with verification methodologies (UVM, System Verilog), testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues Required Tools: Synopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Familiarity with high-level synthesis (HLS) tools Knowledge of scripting languages such as Python, Tcl, or Perl for automation Develop RTL designs using VHDL/Verilog for ASIC projects Perform digital logic design, synthesis, and timing analysis Conduct linting and static analysis to ensure code quality Develop and implement verification methodologies (UVM, System Verilog) Create and maintain testbenches for simulation and functional coverage Perform simulations and debugging to ensure design correctness Participate in design reviews and provide feedback to improve design quality

Expertise in block level and system level verification using UVM Proficiency in coding UVM tests Strong debugging skills for resolving failure In-depth experience in coverage analysis and functional coverage Knowledge in scripting

This position is an excellent opportunity for an experienced and highly motivated verification engineer to join the hardworking System IP team! This is a fast-paced technical role employing the latest hardware design and verification methodologies to develop complex and highly configurable hardware IP that sit at the heart of Arm-based Systems! About System IP This role is for the System MMU product teams The SMMU team owns the development of next-generation Arm SMMU targeting high-end mobile, networking and enterprise markets The SMMU is a key component of the Arm Architecture that provides critical and complex functionalities that complement systems design with Arm processors and Multimedia IP What will I be accountable for You will specify and develop new hardware verification testbenches for future generation hardware IP You will improve existing testbenches to increase performance, quality and efficiency You will also identify areas for improvement in processes and methodologies, then implement those changes to advance our best-practises and state of the art for hardware verification The responsibilities of a member of the Verification team are Reviewing and assessing proposed design changes from a verification complexity point of view Develop and own verification plans for IP blocks based on architecture and design specifications Define testbenches, coverage goals, and verification environments using industry-standard methodologies Investigating and scripting new verification flows and optimising existing ones Developing methodology and deploying within the group and having full ownership of verification closure and mentoring other members of the team Collaborate with architects, RTL designers, and software teams to define verification scope and goals Close collaboration with other Arm engineering teams leading to high quality IP that works well in a complete system Essential skills and experience You can demonstrate experience in working with constrained-random verification including ownership of a suitably complex verification environment Experience of architecting and implementing functional verification environments for complex IP Experience developing re-usable and scalable code whilst having good knowledge of UVM Strong scripting skills being able to develop scripting to support new flows Proven software engineering skills including understanding of object-oriented programming, data structures, and algorithms You are familiar with the tools and processes for developing testbenches and finishing all aspects of the verification process Strong communication skills and ability to work well as part of a team Dedicated with a focused approach to problem analysis and solving Strong experience in planning and estimation Desirable skills Team leadership and mentoring experience Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e g AMBA5 CHI, AMBA4 ACE or AXI) Experience in Formal Verification testbenches is a plus Core Beliefs The opportunities ahead of us are immense To seize these opportunities, speed, efficiency and impact matter We need to work fast, make decisions quickly, be nimble and efficient, and operate as one Arm rather than in siloed teams thinking solution and product first At Arm, we aim to live fully the following three Core Beliefs 'Do great things' means we work with urgency, embrace challenges, find a way 'We, not I' means we embrace both collaboration and individual accountability for the success of Arm 'Be your brilliant self' mean we insist on excellence and we enable performance, individuality and inclusion across Arm Arm is committed to global talent acquisition, offering an attractive relocation package With offices around the world, Arm is a diverse organisation of dedicated, creative and highly talented engineers By enabling a dynamic, inclusive, meritocratic, and open workplace, where all our people can grow and succeed, we encourage our people to share their unrivalled contributions to Arm's success in the global marketplace We are an Equal Opportunity Employer, value diversity at our company and do not discriminate against any employee or applicant for employment on the basis of race, colour, gender, age, national origin, religion, sexual orientation, gender identity, status as a veteran, and basis of disability or any other federal, state or local protected class Accommodations at Arm At Arm, we want to build extraordinary teams If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm com To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility Please email us about anything we can do to accommodate you during the recruitment process Hybrid Working at Arm Arms approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the teams needs Details of what this means for each role will be shared upon application In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution Please talk to us to find out more about what this could look like for you Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded Underpinning our mission is the AMD culture We push the limits of innovation to solve the worlds most important challenges We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives AMD together we advance_ Lead SOC Verification Engineer The Role You have a passion for modern, complex processor architecture, digital design, and verification in general You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems The Person A successful candidate will work with senior silicon design engineers The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills Key Responsiblities Fair understanding on protocols : AXI3/DDR/ACE/CHI is a must Prior work experience on High-Speed Serials PCIe/CXL/USB/SATA/GT/SerDes IP's is preferred Preferred Experience Minimum 12+ year of industry experience in IP/SOC level design verification Have worked upon atleast one full cycle of SoC Verification flow Strong SV/UVM, UVC, Scoreboards, Functional coverage, SV assertions, C/C++ expertise Able to create APIs for SOC level test bench stimulus Strong debug expertise Must have good communication skills and ability to work in a team environment Experience in data path verification protocol like PCIe/CXL/AXI/SATA at SoC Level Experience in driving task independently and complete with excellent quality Academic Credentials Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law We encourage applications from all qualified candidates and will accommodate applicantsneeds under the respective laws throughout all stages of the recruitment and selection process

1. Knowledge of Electrical Vehicle. 2. Knowledge of CAD Tools. 3. Knowledge of Capital Harness/VeSys Electrical software. 4. Good Exposure of 3D ModelingAssy. Drafting in NX Software. 5. Detail design of wiring harness, lighting, switches, sensors, ECU, harness routing & instrument clusters, EV Battery, Motor, CAN and battery charging system. 6. Design knowledge of Subsystem of Tractor. 7. Having Exposure for the implementation of the new development of components, mainly responsible for the designing of Electrical Vehicle related components & involving during the development and proto activities. 8. Having the complete Tractor Knowledge. 9. Should be specialized in Vehicle Integration and Co-ordination with aggregate [Transmission/Hydraulic/Engine] Experience 4 - 7 Years Industry Engineering Engineering Design R&D Quality Qualification Other Bachelor Degree Key Skills Electrical Vehicle Capital Harness Can System Vehicle Integration Electric Vehicle Electrical Manager

We are seeking a highly skilled and experienced DV Lead to drive the verification of complex System-on-Chip (SoC) designs. The ideal candidate will be proficient in SoC-level verification methodologies , have strong expertise in writing C test cases for embedded systems, and lead verification planning and execution for SoC projects. Key Responsibilities: Lead the end-to-end SoC verification lifecycle, from test planning to coverage closure. Define verification strategy , test plans, and verification infrastructure for SoC-level designs. Develop and execute C-based test cases for processor and peripheral verification in a simulation/emulation environment. Collaborate with RTL design, firmware, and software teams to ensure complete SoC-level functional coverage. Drive debugging efforts across multiple functional blocks and coordinate with cross-functional teams to resolve issues. Utilize industry-standard verification tools and methodologies (e.g., UVM, System Verilog, C, scripting). Manage a team of verification engineers and ensure timely delivery of milestones.

Experience: 6 - 15 years Responsibilities: Verification engineer with a knowledge of SoC integration verification, SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx/AI accelarator integration verification in SoC RTL. Your key responsibilities will include writing test plans, defining test methodologies, developing C based software tests, SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues. Working with project management and leads on planning tasks, schedules, and reporting progress Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development Required Skills and Experience Proven understanding of digital hardware verification language Verilog/Systemverilog HDL Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM) Experienced in SoC verification using Experienced in one or more of various verification methodologies UVM/OVM, formal, power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. Knowledge of SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures, SoC Boot flow, Cache coherency Porting peripheral driver software for SoC tests Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Experienced in UPF Power Aware verification Automation experience with shell programming/scripting (g. Tcl, Perl, Python etc.)

We are seeking a highly skilled and experienced Staff Engineer for Functional Modeling Verification to join our innovative team in Bengaluru, India. As a Staff Engineer, you will play a crucial role in shaping our technical direction, leading complex projects, and mentoring junior engineers. Lead architectural decisions and provide technical guidance to cross-functional teams Collaborate with product managers and other stakeholders to define technical requirements and solutions Conduct code reviews and ensure code quality across projects Mentor and guide junior engineers, fostering their professional growth Identify and resolve complex technical issues across multiple projects Stay current with emerging technologies and industry trends, recommending innovations to improve our tech stack Contribute to the development of engineering best practices and coding standards Participate in system design discussions and technical planning sessions Optimize existing systems for improved performance and scalability Hands-on experience in C++ System C based Model development/test creation Prior Experience with C based Tests/Test bench development Python coding would be a plus Knowledge on NAND concepts will be an advantage Knowledge on Memory and Digital Design Concepts would be preferable (SRAM/DRAM/ROM/Flash) Circuits/Logic Languages Expertise - C, C++, Python, System C, SystemVerilog/UVM will be a plus - Tool Expertise - VisualStudio, Git, Bitbucket Hands-on contributions coding C++ System C models test creation Debug issues in Firmware environment Validating the developed model using SV/UVM testbench Debug failures and root-cause it by interacting with other teams/groups etc Qualifications Bachelors or Masters degree in Computer Science or a related field BE/BTech/ME/MTech in Engineering with Computer Science, ECE or related field MSc/MCA in Computer Science or a related field 8 to 14 years of software engineering experience, with a proven track record of leading complex technical projects Expert-level proficiency in one or more programming languages such as Java, Python, or C++ Strong experience with cloud platforms (e.g., AWS, Azure, GCP) and distributed systems In-depth knowledge of system design, architecture, and performance optimization Proficiency in version control systems, preferably Git Ability to work effectively in a fast-paced, agile environment Strong analytical and detail-oriented approach to software development

We are hiring a ASIC Verification Engineer to help contribute to rapidly expanding and innovative chip designs in both 7nm and 5nm process technologies. We are developing cutting-edge domain specific processors for the IAAS and smart-switch markets that leverage the P4 programming language to provide software-defined features and scale but with hard-wired performance attributes. Applications include advanced PCIe, networking, storage, and security virtualization services for both the public and private cloud markets. THE ROLE: In this role, you will be responsible for defining test strategies and plans, developing test benches and test cases, and debugging designs helping with micro-architecture. You will participate in design verification methodology definition as we'll as contribute to design verification infrastructure that facilitates maximum re-use of components, improves productivity, and guarantees to the maximum extent possible, bug-free designs. Your work and skills will be leveraged across module-level, full chip, emulation, prototyping, silicon bring-up, manufacturing diagnostics, compilers, and shipping platform software. KEY RESPONSIBILITIES: With your solid knowledge and understanding of Computer Architecture you will be: Developing and executing test plans for Unit/IP/Subsystem/ SOC level verification System Verilog test bench development including stimulus, checkers, transactors/BFMs, assertions and cover points Identifying bugs in architecture, functionality and performance with strong overall debug and analytical skills PREFERRED EXPERIENCE: Languages and tools: UVM, System Verilog, C or C++ System Verilog simulators and waveform debuggers Experience developing and executing test plans for Unit/IP/Subsystem/ SOC level verification Experience in System Verilog test bench development including stimulus, checkers, transactors/BFMs, assertions and cover points Experience identifying bugs in architecture, functionality and performance with strong overall debug and analytical skills Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy/DVE) Solid knowledge and understanding of Computer Architecture Excellent debugging and problem-solving skills ACADEMIC CREDENTIALS: BSEE or equivalent. MSEE preferred

Grow with us About this opportunity: We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrows mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport - to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we dont just follow industry trends we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, youll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, youll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements. Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. Youll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. You will bring Key Responsibilities: Lead a team of verification engineers, providing mentorship and guidance to ensure efficient and reusable verification practices. Collect and address, team status and metrics. Take full responsibility for the verification strategies that the team has responsibility for. Define and implement UVM-based test environments. Break down requirements to create a Verification Strategy and develop and execute a Verification Plan. Develop, run, and debug test cases to ensure design quality. Continuously improve and optimize verification methodologies. Generate comprehensive documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Develop competence in the technical domain. Foster cross-team collaboration to ensure seamless project delivery and integration. Required Qualifications: Bachelor s degree in electrical or computer engineering. 8+ years of industry experience in verification using SystemVerilog and UVM. Proven track record of leading verification test plan development in cross-site environments. Proficiency in/with: architecting and creating new grounds-up random and directed test environments and testcase strategies. formal verification for connectivity checks and using assertion-based VIPs. architecting and leading implementation of scoreboards, checkers, bus functional models SystemVerilog Assertions. Strong experience in low-power design verification. Additional Requirements: Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson? What happens once you apply? Primary country and city: India (IN) || Bangalore Req ID: 768638