868 Uvm Jobs - Page 16

Skillset: DV | System Verilog | UVM | Protocol Expertise Must-Have Skills: Strong expertise in System Verilog (SV) and UVM Proven experience in Test Bench Development Deep protocol knowledge in at least one of the following: PCIe / UCIe / CXL / NVM AXI / ACE / CHI Ethernet / RoCE / RDMA DDR / LPDDR / HBM Key Responsibilities : Lead and drive verification for block, subsystem, or SoC level designs Strong experience in IP/subsystem/SoC verification using SV/UVM Verification experience with ARM or RISC-V CPU based subsystems Work with C/Assembly for low-level testing Perform Power Aware Simulations using UPF Location : Bangalore | Hyderabad | Cochin | Pune

Roles and Responsibilities Design verification using UVM (Universal Verification Methodology) for PCIe, DDR, Ethernet interfaces on SOCs. Develop test benches in System Verilog for verifying complex digital designs. Collaborate with cross-functional teams to identify requirements and develop test plans. Utilize GLS (Golden Labs Simulation) tools for simulation setup and debugging. Participate in peer reviews to ensure high-quality deliverables. Must have good debugging skills. Experience in any of the slow speed peripherals like I2C, SPI, UART is a plus. Desired Candidate Profile 5 years of experience in SV/UVM Lead role with expertise in design verification using UVM methodology. Bachelor's degree (B.Tech/B.E.). Master's degree preferred but not mandatory (M.Tech). Strong understanding of SystemVerilog programming language and its application in DV testing.

• Develop SoC verification plans focused on IP block interoperability & SOC/ System level. • Develop RAL test plan at SOC/IP level. • Verify SoC using advanced verification methodologies. • HW/SW Co-Verification environment - test-benches, use-cases. Required Candidate profile • 10+ years in DV full-chip Exp. • Strong in UVM & testbench architecture • SV/UVM testbench & assertion Development • Hands-on RAL model development (UVM) • Interface knowledge: AXI, APB, AHB

Design of DC-DC High Frequency Switching Power Supplies using Analog Devices large portfolio of Power Management Integrated Circuits. New DC-DC Monolithic (Integrated Power and Controller) Power Products definition. Validation of the new generation Power Management Integrated Circuits. Full product life-cycle ownership - Definition, Validation and Market Introduction. Mentor junior Product Applications Engineers Responsibilities include: Development of product evaluation kits and system reference design boards Circuit schematic design and PCB layout creation, review, and release Performance optimization and characterization in application circuits Validate new products, creating new test methodologies. Data collection for datasheets and release notes Collate results with design and test engineers. Technical support for key customers and field engineers Simulation of Power Electronics Converters Take ownership of quality and on-time delivery Minimum Requirements: Masters degree in Power Electronics At least 8 years of hands-on experience in developing switching power supplies. Basic understanding of transistor-level analog circuit design Strong written and verbal communication skills

Verification of mixed signal designs and sub-systems using leading edge verification methodologies. Development of directed and constrained random test cases in System Verilog Architect, implement, and/or manage complete metric-driven System Verilog and UVM verification environments as determined by project complexity Define test plans, tests and verification methodology for block / chip-level verification. Work with the design team in generating test-plans and closure of code and functional coverage. Continuous interaction with analog and digital teams in enabling top-level chip verification. Support post-silicon verification activities of the products working with design, product evaluation, and applications engineering team. Minimum qualifications BSEE + 7 years or MSEE + 5 years Digital and/or Mixed Signal IC verification experience. Strong written and verbal communication skills. Strong coding, object-oriented programming, and documentation skills. Strong System Verilog fluency in verification domain. System Verilog Assertion for Dynamic and Formal Verification. Experience in developing test benches, testcases using System Verilog and UVM Knowledge of test-plan generation, coverage analysis, transaction level modeling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog Knowledge of and capability to execute the entire digital verification process without significant assistance Preferred qualifications Knowledge/verification of custom digital interfaces (I2C, SPI, UART, etc.). Extensive experience with a scripting language (Perl, Python, C, etc.) Experience with Mixed signal verification Mixed-signal simulation (Cadence AMS), interfacing with analog functions Experience with writing Verilog-AMS and Real Number Models for Analog Functions Familiarity with verification on multiphase DC-DC controllers Experience with verification of ARM/RISC-V based sub-systems or SoCs. Experience with verification of voltage interfaces like PMBUS, AVS, SVID, SVI3. Experience with formal verification methodology

We're looking for a highly skilled Senior Digital Verification Engineer with extensive hands-on experience in SystemVerilog (SV) and UVM methodology. In this role, you'll be instrumental in developing robust verification plans, building reusable testbench components, and driving comprehensive coverage closure for complex digital blocks at various levels. Responsibilities: Collaborate with cross-functional teams to meticulously review and refine architecture and design specifications. Develop comprehensive verification plans for complex digital modules at the IP, Subsystem, and SoC levels. Design and implement reusable testbench components , including drivers, monitors, and scoreboards, utilizing SV-UVM methodology. Work closely with design teams to achieve rigorous coverage closure. Coordinate with silicon test and evaluation teams to develop and deliver effective test patterns. Required Qualifications: Extensive hands-on experience (6+ years) in digital verification using SystemVerilog (SV) and UVM methodology . Proven expertise in developing verification plans for complex digital blocks. Proficiency in creating testbench environments at IP and/or Subsystem levels. Experience in constrained random stimulus generation and coverage closure . Competence in Gate-Level Simulation (GLS) setup and debugging. Strong debugging skills and analytical problem-solving capabilities . Familiarity with ARM-AMBA protocols . Advantageous Skills: Experience in formal verification and SystemVerilog Assertions (SV-Assertion) coding. Exposure to mixed-signal verification . Exposure to Ethernet interface standards .

Lead, Develop and deploy best-in-class Emulation/FPGA prototyping tools and methodologies across ADI Product Lines Develop and deploy Accelerated Verification IPs, Synthesizable BFMs and help in integration of memory models of various interfaces Engaging with EDA vendors to influence their development roadmaps to meet ADI s requirements into the future Support the product lines in bring-up of new designs, debug issues and explore new methodologies that improve the overall verification flow Training, deployment, and support of verification methodologies within ADI Position Requirements : Bachelors/master s degree in electrical/Electronics/VLSI with 4-8 years of experience Exposure to emulation platforms like Palladium/Zebu/Veloce and prototyping platforms like Protium/HAPS is highly preferred. Exposure to JTAG, UART and SpeedBridges (Ethernet/USB) validation is highly preferred Expertised in one or more of scripting languages(shell,python,perl) is highly preferred Proficient in SV, UVM, integration of third party VIPS, Accelerated VIPS is required Experience with Vplan/Testplan development and development of verification environment from ground up is good Experience in common communication protocols such as AMBA,I2C, SPI,UART and Ethernet is an added advantage Should be able to communicate technical details very effectively with both customers (product line teams) and peers Good debugging and analytical skills

Lead, Develop and deploy best-in-class Emulation/FPGA prototyping methodologies and execution across ADI Product Lines Proficient in developing unit and SoC level test benches using UVM Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology etc Skilled in enabling emulation for Software development and validation Develop and deploy Accelerated Verification IPs, Synthesizable BFMs and help in integration of memory models of various interfaces Engaging with EDA vendors to influence their development roadmaps to meet ADI s requirements into the future Support the product lines in bring-up of new designs, debug issues and explore new methodologies that improve the overall verification flow Training, deployment, and support of verification methodologies within ADI Position Requirements : Bachelors/master s degree in electrical/Electronics/VLSI with 8-12 years of experience Exposure to emulation platforms like Palladium/Zebu/Veloce and prototyping platforms like Protium/HAPS is highly preferred. Experience in bringing up designs from scratch in Palladium/Protium is highly preferred Exposure to JTAG, UART and SpeedBridges (Ethernet/USB) validation is highly preferred Expertised in one or more of scripting languages(shell,python,perl) is highly preferred Expertised in SV, UVM, integration of third party VIPS, Accelerated VIPS is required Experience with Vplan/Testplan development and development of verification environment from ground up is required Experience in common communication protocols such as AMBA,I2C, SPI,UART is required and Protocols like JESD, Ethernet is good Should be able to communicate technical details very effectively with both customers (product line teams) and peers Good debugging and analytical skills

Are you a highly skilled Formal Verification Engineer looking to make a significant impact across the entire product lifecycle Join Analog Devices in a senior role where you'll drive the formal verification of complex digital designs, from concept through to release. You'll collaborate with a wide technical community, gaining exposure to diverse technologies and products, all while building a promising career. Job Responsibilities: Formal Verification Planning and Execution: Develop and execute comprehensive formal verification plans for complex digital designs, including both block-level and system-level components. Define precise verification goals, metrics, and coverage targets to ensure exhaustive validation of design functionality. Model Development and Property Writing: Create robust formal models and assertions using industry-standard formal verification tools and techniques. Write and debug properties, constraints, and assumptions to rigorously verify design intent and proactively identify corner-case issues. Debugging and Issue Resolution: Analyze counterexamples and debug failures to pinpoint the root causes of design issues. Work closely with design and RTL teams to efficiently resolve issues and ensure complete alignment with design specifications. Tool and Methodology Expertise: Utilize advanced formal verification tools such as JasperGold, Questa Formal, or equivalent, to perform exhaustive verification. Stay updated on the latest advancements in formal verification methodologies and tools, actively driving their adoption and continuous improvement within the team. Collaboration and Communication: Collaborate effectively with architects, designers, and validation engineers to deeply understand design requirements and constraints. Documentation and Reporting: Document formal verification strategies, methodologies, and results for future reference and auditability. Generate detailed reports summarizing verification coverage, key findings, and actionable recommendations. Position Requirements: Bachelor's or Master's degree in Electrical/Electronics/VLSI with 4-6 years of relevant experience. Demonstrated experience with Formal tools such as Cadence Jasper, Synopsys VC Formal, Siemens Questa Formal, with prior implementation experience on SoCs, CPUs, GPUs, or other high-performance computing devices. Proficiency in writing SystemVerilog Assertions (SVA) or Property Specification Language (PSL). Solid understanding of digital design concepts, RTL design, and hardware description languages (Verilog, SystemVerilog, VHDL). Strong analytical and debugging skills to effectively identify and resolve complex design issues. Ability to analyze counterexamples and provide actionable feedback to design teams. Excellent communication and interpersonal skills to work effectively in a collaborative team environment. Familiarity with scripting languages (Perl, Python, TCL) for automation. Experience in common communication protocols such as ARM AMBA, I2C, SPI, UART is preferred.

In your new role you will: Be in continuous and intensive contact with our development sites worldwide; Advise and support the experts from our business units in verification projects; Drive the internal exchange of know-how and experience at Infineon; Work out optimization opportunities in the area of verification methodology and verification coverage through integrating the results achieved into Infineons design system and supporting their implementation in the development of new products; Collaborate with other disciplines (e.g. Application Engineering) to define the verification methodology and the verification plan; Design and develop the verification environment for ICs using the Universal Verification Methodology (UVM); Independently identify sub-modules that are particularly suitable for formal Verification and apply this methodology; Implement test scenarios using System Verilog and verify functionality using a Constrained Random Approach; Use the Unified Power Format (UPF) to verify the low-power aspects of our designs; Your Profile You are best equipped for this task if you have: You are best equipped for for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener

We are seeking a results-oriented Senior Digital Verification engineer to join our team focusing on development of the next generation of ADI s Gigabit Multimedia Serial Link products delivering best-in-class solutions for in-car infotainment and advanced driver-assistance systems (ADAS). A small amount of travel is expected. The position offers opportunities for development. JobResponsibilities: Verification of complex ASIC chips and sub-systems using leading edge verification methodologies Define test plans, tests and verification methodology for block and chip level verification. Employ UVM/SystemVerilog based verification methodologies and use scoreboard, assertions, functional/code coverage, formal verification etc to reach verification goals. Take complete ownership for a complex feature verification and technically mentor & guide junior verification engineers. Define and implement improvements in verification flow and methodology. Gate level simulations and debug of large digital blocks and full-chip ASICs Support post-silicon validation activities of the products working with design, applications and test team. Job Requirements: Bachelors or masters degree in Electrical or Computer Engineering with 7+ years of experience in digital verification. Expertise in Verilog, System Verilog, UVM, object-oriented programming, scripting and automation with Perl or Python. Firm understanding of constrained random functional verification, coverage, and assertions. Expertise in test plan development and development of verification environments from ground up. Extensive experience with verification of complex blocks, regressions and coverage closure. Experience with gate level simulations and debug. Excellent debugging, analytical and problem-solving skills. Strong inter-personal, teamwork and communication skills. Expected to be highly independent, proactive and result-oriented to achieve verification goals. Preferred qualifications: Knowledge of Video (DisplayPort, CSI/DSI), PCIe, Ethernet, I2C, UART, SPI and Audio I2S protocols.. Experience with lab silicon bring-up, validation and production test support. Experience in technically mentoring, coaching junior engineers.

We're looking for a highly experienced and self-motivated Lead Analog/Mixed-Signal Verification Engineer to join our team. In this pivotal role, you'll be responsible for the comprehensive verification of complex mixed-signal designs, from block to full-chip levels. You'll drive verification methodologies, mentor junior engineers, and play a crucial part in ensuring the quality of our cutting-edge products. Responsibilities: Lead the verification of complex mixed-signal designs and sub-systems , ensuring robust functionality and performance. Develop and utilize Analog Behavioral Models (SystemVerilog, Verilog-AMS, wreal, UDNs, EEnet) for efficient verification. Validate real number models against SPICE models , ensuring accuracy and correlation. Gain hands-on experience with SPICE simulations using industry-standard simulators such as SPECTRE. Define comprehensive test plans, tests, and verification methodologies for both block and chip-level verification of Mixed-Signal Designs. Continuously interact with the analog co-simulation team to enable seamless top-level chip verification. Contribute to and influence decisions on verification methodologies to be adopted across projects. Technically mentor and guide junior verification engineers on SoC Verification best practices. Support post-silicon verification activities of products, working closely with design, product evaluation, and applications engineering teams. Required Qualifications: B.Tech/M.Tech with 8-12 years of industry experience in analog/mixed-signal verification. Demonstrated experience in verification plan development, verification environment creation, and verification/debug of complex mixed-signal products at block and chip-top levels. Proven experience in co-simulations with analog model/transistor level and digital RTL/Gate+SDFs , as well as circuit simulations with Spice/Fast Spice simulators. Proven experience in leading full-chip level design verification of mixed-signal devices. Must have experience in modeling and validation of analog blocks (RNM, Verilog-AMS, etc.). Familiarity with latest digital verification methodologies , including Digital Mixed-Signal (DMS) verification using UVM. Strong communication skills and the ability to collaborate effectively with a global team. Self-motivated and enthusiastic. Excellent debugging and analytical skills. Additional Qualifications & Experience: Proficiency with Verification Planning tools (e.g., ePlanner, vManager). Experience with SystemVerilog Assertions (SVA) . Skilled in scripting languages (Shell, TCL, Perl, Python) for testbench automation. Hands-on UVM experience at the user level, including pseudo and constrained random techniques, and assertion-based verification with SystemVerilog. Experience in building and leading small verification teams . Strong interpersonal, teamwork, and communication skills are essential.

Hands-On UVM at user level, pseudo and constrained random techniques, assertion-based verification techniques with System Verilog. Verification of analog interface is a value add along with ARM based subsystem, core sight, security subsystem verification exposure. 3rd party, industry-standard simulator productivity improvements and breakthrough innovations, integration into ADI DV solutions and creating differentiating solutions Evaluate, utilize existing and develop new verification infrastructure frameworks, tools, and methodologies to enhance the verification process for efficiency and quality Job Requirements: BTech/MTech degree in Electrical/Electronics/VLSI with 3-6 years of experience from reputed institutes Strong hands-on experience in Cadence/Synopsys simulation and debug tools like Xcelium/VCS, vManager, Verisium, Verdi or similar is required Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by designer. Coding up in C tests on M3 Series Cortex based products. Expertise in automation and scripting languages like Perl, Python, and shell scripting Proficient in Version control systems, such as Perforce, SVN, SOS Proficient in Verilog, System Verilog and UVM Ability to manage multiple tasks and work effectively in a fast-paced environment Able to communicate effectively Good debugging and analytical skills

In your new role you will: Be in continuous and intensive contact with our development sites worldwide Advise and support the experts from our business units in verification projects Drive the internal exchange of know-how and experience at Infineon Work out optimization opportunities in the area of verification methodology and verification coverage through integrating the results achieved into Infineons design system and supporting their implementation in the development of new products Collaborate with other disciplines (e.g. Application Engineering) to define the verification methodology and the verification plan Design and develop the verification environment for ICs using the Universal Verification Methodology (UVM) Independently identify sub-modules that are particularly suitable for Formal Verification and apply this methodology Implement test scenarios using System Verilog and verify functionality using a Constrained Random Approach Use the Unified Power Format (UPF) to verify the low-power aspects of our designs You are best equipped for for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.

As a Digital Designer one should have working experience with AMS Verification on multiple SOCs or sub-systems. One should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. In your new role you will: Ability to lead MSV and/or DV verifications. Involved in verification for IPs. Handling project dynamics on scope, schedule and effort coming up with alternative verification plans, Mentoring Junior engineer. Test plan preparation as per the dynamics of product specifications. Behavioral modeling: Verilog, real or SV-RNM. Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS. Testcase Debug proposing new scenarios. Ability to strategize optimization of simulation bench for simulation time. Your Profile. You are best equipped for this task if you have: Bachelors with 9+ years or Masters with 8+ years of experience. Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage

Roles and Responsibility PFB the JD. JD Lead: 1 or 2 or 3 based on the options we get 15+ years of experience in Design Verification Strong experience in Processor based SoC verification Strong experience in ARM Cortex M or A series designs. Must have worked on bringing up the boot code, writing ISR, exceptions and other functions Strong experience in System Verilog and UVM based design verification Experience in Tensilica xtensa designs is a big plus Must have lead at least 2 to 3 SoC DV or Processor subsystem projects with a team size of 10+ Engineers Must have strong experience in AMBA protocols Must have strong understanding of functioning of Cache controllers, DMA & memory management controllers/ techniques JD Engineer: 9 members 1. 3 to 10 years of experience in Design Verification 2. Good experience in Processor based SoC Verification is a must 3. Experience in writing C or Assembly testcases is a must 4. Strong experience in AHB or AXI protocol is a must 5. System Verilog and UVM experience is a must JD Engineer: 6 members 1. 3 to 10 years of experience in Design Verification 2. Good experience in Processor based SoC Verification is a must OR strong experience in IP verification using SV/ UVM is a must 3. Experience in writing C or Assembly testcases is a plus 4. Strong experience in AHB or AXI protocol is a must Location: 1. Pune or Noida or Bangalore 2. Each location needs a lead + team of 3 to 4 to a minimum 3. If we can set it up in one location that would be great

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Looking for candidates between 3 to 13 years of experience. Worked on coverage driven module verification. Strong in System Verilog, UVM Sound experience in testbench (stimulus, agent, monitor, checker) development. Failure debugging with Verdi & log file. Worked in the verification having c based reference model inside the testbench Experience with assertion development. Familiar with the EDA tools IUS, VCS, Verdi etc. Exposure in scripting(perl, Python). Good team player. Need to interact with the designers and other verification engineers proactively. Prior experience with video pipeline is added advantage. Knowledge of tensilica Worked with sub-system verification with tensilica Experience in C based system modelling. Debug with C based reference model. Have exposure to the other verification tasks gate level simulation, Power aware simulation, formal verification, sub-system verification and emulation. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs ( PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support. Responsibilities Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation. Minimum Qualifications Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field. 12+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications Experience with Low power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc., Experience in scripting languages (Python, or Perl). Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Verification & Validation team is currently looking for self-motivated engineers who will perform ARM or DSP based SOC Pre-Si and Post Si validation including system level validation and debug. The ideal candidate should leverage his knowledge and experience to provide leadership, technical guidance, and execution of silicon validation of ARM or DSP based multiple SOC projects and platforms Experience in SoC pre/post silicon validation. ARM based System-On-Chip Pre-Silicon emulation and Post-Silicon ASIC Validation experience related to board bring up and debug. Perform system level validation and debug Debug experience with Lauterbach Trace32 environment. Test equipment like Logic analyzer, Oscilloscope and Protocol analyzers. Embedded software development of low level hardware drivers in C language. Working experience related to one or more of the following is required. ARM/DSP Processors/USB/PCIE, Ethernet Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2-6yrs experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Looking for candidates between 3 to 13 years of experience. Worked on coverage driven module verification. Strong in System Verilog, UVM Sound experience in testbench (stimulus, agent, monitor, checker) development. Failure debugging with Verdi & log file. Worked in the verification having c based reference model inside the testbench Experience with assertion development. Familiar with the EDA tools IUS, VCS, Verdi etc. Exposure in scripting(perl, Python). Good team player. Need to interact with the designers and other verification engineers proactively. Prior experience with video pipeline is added advantage. Knowledge of tensilica Worked with sub-system verification with tensilica Experience in C based system modelling. Debug with C based reference model. Have exposure to the other verification tasks gate level simulation, Power aware simulation, formal verification, sub-system verification and emulation. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary: Position for 5-8 years of experience in design verification of complex Qualcomm propriety DSP/NPU IP DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more. Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property. Job Responsibilities: Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams. Implement and improve System Verilog/UVM Testbench Architecture. Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency. Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals. Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs. Complete all required verification activities at IP level and ensure high quality commercial success of our products. Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis. Responsible gate level simulation bring-up, gate level verification with timing simulations. Responsible for power aware RTL verification and gate level simulation. Skillset/Experience: 5-8 years experience in processor/ASIC design verification Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification. Expertise in System Verilog Testbench Architecture and implementation. Experience in writing C based and assembly level testcases is preferred. Exposure to power aware implementation and verification using UPF is a plus. Experience with advanced verification techniques such as formal and assertions is a plus. Gate-Level Simulation and Debug — 0-delay, timing annotated and power aware. Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence . Scripting/Automation Skills — Perl, Python, Shell, Make file TCI . Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts. Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred. Experience in verification of Processor subsystems is preferred. Experience in creating validation suite and building automation. Should have excellent inter-personal and communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Additional o BE/BTech degree in CS/EE with 3+ years’ experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred : o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologiesJTAG, IEEE1500, MBIST, scan dump, memory dump is a plus Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas: Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Excellent Design verification domain expertise. Develop test strategy, TB architecture and test plan for new IP’s/new features Develop strategies for re-useable, scalable and enhance Sub system level verification environment Excellent C/System Verilog/Verilog skills to handle C based TB environment Strong skills in debug, post silicon debug-failure re-creation and root cause analysis Scripting proficiency - PERL, Python, for developing applicable automation AMBA, AXI bus protocols Power intent verification, GLS etc. Capable of communicating effectively with all stakeholders across the globe Capable of seeding a new team for new IPs, able to hire and expand the team in expertise and efficiency Capable of mentoring the team members for their career growth, maintaining diversity in the team, collaborating with other leads and managing multiple parallel projects Take initiatives to enable various ideas for improving efficiencies. Good to have Image Processing, DSI/DP/HDMI Protocols Good knowledge of new methodologies, flows and tools to be incorporated. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Software Principal Engineer The Software Engineering team delivers next-generation application enhancements and new products for a changing world. Working at the cutting edge, we design and develop software for platforms, peripherals, applications and diagnostics all with the most advanced technologies, tools, software engineering methodologies and the collaboration of internal and external partners. Join us to do the best work of your career and make a profound social impact as a Software Principal Engineer on our 5G RAN FPGA Verification Team in Bangalore . What you ll achieve As a Software Principal Engineer, you will be responsible for developing sophisticated systems and software based on the customer s business goals, needs and general business environment creating software solutions. You will: Contribute to the design and architecture of high-quality, complex systems and software/storage environments Prepare, review and evaluate software/storage specifications for products and systems Contribute to the development and implementation of test strategies for complex software products and systems/for storage products and systems Take the first step towards your dream career Every Dell Technologies team member brings something unique to the table. Here s what we are looking for with this role: Essential Requirements Experience in FPGA systems design and verification with Verilog coding, System Verilog, and VHDL coding practices. Experience in UVM Verification framework, Assertion based Verification, Code coverage, Unit level simulations. Experience in E2E bench setup and HW validation. Very strong debugging skills Experience in RTL Design Digital Design Principles and peripheral protocol. Strong fundamentals in both analog and digital design practices with a desire to share knowledge and mentor others Experience and deep knowledge of hardware and software interactions, and ability to apply this understanding to resolve issues. Desirable Requirements 8-12 years of relevant experience or equivalent combination of education and work experience Experience in MATLAB and Simulink modelling for 5G flow Application closing date: 20 July 2025