853 Uvm Jobs - Page 16

Roles and Responsibility PFB the JD. JD Lead: 1 or 2 or 3 based on the options we get 15+ years of experience in Design Verification Strong experience in Processor based SoC verification Strong experience in ARM Cortex M or A series designs. Must have worked on bringing up the boot code, writing ISR, exceptions and other functions Strong experience in System Verilog and UVM based design verification Experience in Tensilica xtensa designs is a big plus Must have lead at least 2 to 3 SoC DV or Processor subsystem projects with a team size of 10+ Engineers Must have strong experience in AMBA protocols Must have strong understanding of functioning of Cache controllers, DMA & memory management controllers/ techniques JD Engineer: 9 members 1. 3 to 10 years of experience in Design Verification 2. Good experience in Processor based SoC Verification is a must 3. Experience in writing C or Assembly testcases is a must 4. Strong experience in AHB or AXI protocol is a must 5. System Verilog and UVM experience is a must JD Engineer: 6 members 1. 3 to 10 years of experience in Design Verification 2. Good experience in Processor based SoC Verification is a must OR strong experience in IP verification using SV/ UVM is a must 3. Experience in writing C or Assembly testcases is a plus 4. Strong experience in AHB or AXI protocol is a must Location: 1. Pune or Noida or Bangalore 2. Each location needs a lead + team of 3 to 4 to a minimum 3. If we can set it up in one location that would be great

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Looking for candidates between 3 to 13 years of experience. Worked on coverage driven module verification. Strong in System Verilog, UVM Sound experience in testbench (stimulus, agent, monitor, checker) development. Failure debugging with Verdi & log file. Worked in the verification having c based reference model inside the testbench Experience with assertion development. Familiar with the EDA tools IUS, VCS, Verdi etc. Exposure in scripting(perl, Python). Good team player. Need to interact with the designers and other verification engineers proactively. Prior experience with video pipeline is added advantage. Knowledge of tensilica Worked with sub-system verification with tensilica Experience in C based system modelling. Debug with C based reference model. Have exposure to the other verification tasks gate level simulation, Power aware simulation, formal verification, sub-system verification and emulation. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs ( PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support. Responsibilities Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation. Minimum Qualifications Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field. 12+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications Experience with Low power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc., Experience in scripting languages (Python, or Perl). Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Verification & Validation team is currently looking for self-motivated engineers who will perform ARM or DSP based SOC Pre-Si and Post Si validation including system level validation and debug. The ideal candidate should leverage his knowledge and experience to provide leadership, technical guidance, and execution of silicon validation of ARM or DSP based multiple SOC projects and platforms Experience in SoC pre/post silicon validation. ARM based System-On-Chip Pre-Silicon emulation and Post-Silicon ASIC Validation experience related to board bring up and debug. Perform system level validation and debug Debug experience with Lauterbach Trace32 environment. Test equipment like Logic analyzer, Oscilloscope and Protocol analyzers. Embedded software development of low level hardware drivers in C language. Working experience related to one or more of the following is required. ARM/DSP Processors/USB/PCIE, Ethernet Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2-6yrs experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Looking for candidates between 3 to 13 years of experience. Worked on coverage driven module verification. Strong in System Verilog, UVM Sound experience in testbench (stimulus, agent, monitor, checker) development. Failure debugging with Verdi & log file. Worked in the verification having c based reference model inside the testbench Experience with assertion development. Familiar with the EDA tools IUS, VCS, Verdi etc. Exposure in scripting(perl, Python). Good team player. Need to interact with the designers and other verification engineers proactively. Prior experience with video pipeline is added advantage. Knowledge of tensilica Worked with sub-system verification with tensilica Experience in C based system modelling. Debug with C based reference model. Have exposure to the other verification tasks gate level simulation, Power aware simulation, formal verification, sub-system verification and emulation. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary: Position for 5-8 years of experience in design verification of complex Qualcomm propriety DSP/NPU IP DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more. Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property. Job Responsibilities: Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams. Implement and improve System Verilog/UVM Testbench Architecture. Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency. Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals. Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs. Complete all required verification activities at IP level and ensure high quality commercial success of our products. Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis. Responsible gate level simulation bring-up, gate level verification with timing simulations. Responsible for power aware RTL verification and gate level simulation. Skillset/Experience: 5-8 years experience in processor/ASIC design verification Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification. Expertise in System Verilog Testbench Architecture and implementation. Experience in writing C based and assembly level testcases is preferred. Exposure to power aware implementation and verification using UPF is a plus. Experience with advanced verification techniques such as formal and assertions is a plus. Gate-Level Simulation and Debug — 0-delay, timing annotated and power aware. Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence . Scripting/Automation Skills — Perl, Python, Shell, Make file TCI . Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts. Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred. Experience in verification of Processor subsystems is preferred. Experience in creating validation suite and building automation. Should have excellent inter-personal and communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Additional o BE/BTech degree in CS/EE with 3+ years’ experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred : o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologiesJTAG, IEEE1500, MBIST, scan dump, memory dump is a plus Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas: Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Excellent Design verification domain expertise. Develop test strategy, TB architecture and test plan for new IP’s/new features Develop strategies for re-useable, scalable and enhance Sub system level verification environment Excellent C/System Verilog/Verilog skills to handle C based TB environment Strong skills in debug, post silicon debug-failure re-creation and root cause analysis Scripting proficiency - PERL, Python, for developing applicable automation AMBA, AXI bus protocols Power intent verification, GLS etc. Capable of communicating effectively with all stakeholders across the globe Capable of seeding a new team for new IPs, able to hire and expand the team in expertise and efficiency Capable of mentoring the team members for their career growth, maintaining diversity in the team, collaborating with other leads and managing multiple parallel projects Take initiatives to enable various ideas for improving efficiencies. Good to have Image Processing, DSI/DP/HDMI Protocols Good knowledge of new methodologies, flows and tools to be incorporated. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Software Principal Engineer The Software Engineering team delivers next-generation application enhancements and new products for a changing world. Working at the cutting edge, we design and develop software for platforms, peripherals, applications and diagnostics all with the most advanced technologies, tools, software engineering methodologies and the collaboration of internal and external partners. Join us to do the best work of your career and make a profound social impact as a Software Principal Engineer on our 5G RAN FPGA Verification Team in Bangalore . What you ll achieve As a Software Principal Engineer, you will be responsible for developing sophisticated systems and software based on the customer s business goals, needs and general business environment creating software solutions. You will: Contribute to the design and architecture of high-quality, complex systems and software/storage environments Prepare, review and evaluate software/storage specifications for products and systems Contribute to the development and implementation of test strategies for complex software products and systems/for storage products and systems Take the first step towards your dream career Every Dell Technologies team member brings something unique to the table. Here s what we are looking for with this role: Essential Requirements Experience in FPGA systems design and verification with Verilog coding, System Verilog, and VHDL coding practices. Experience in UVM Verification framework, Assertion based Verification, Code coverage, Unit level simulations. Experience in E2E bench setup and HW validation. Very strong debugging skills Experience in RTL Design Digital Design Principles and peripheral protocol. Strong fundamentals in both analog and digital design practices with a desire to share knowledge and mentor others Experience and deep knowledge of hardware and software interactions, and ability to apply this understanding to resolve issues. Desirable Requirements 8-12 years of relevant experience or equivalent combination of education and work experience Experience in MATLAB and Simulink modelling for 5G flow Application closing date: 20 July 2025

Organization Details: CENTUM T&S, headquartered in France, is a business unit of Centum Electronics Group (Around 1000Cr turnover organization) offering a wide range of electronic and embedded systems design engineering services to international customers to help them realize complex products and sub systems. It includes design, development, qualification, value engineering, testbench design & manufacturing and many more services. Centum T&S has established its India operations in North Bengaluru, known as Centum T&S Pvt Ltd (CTS), formerly known as Centum Adeneo India Pvt Ltd. CTS is working with many top companies like Airbus, Thales, Hitachi Energy, GE, ABB, DANA, Alstom, etc., The ideal candidate is a self-motivated, multi-tasker, and demonstrated team-player. You will be responsible for the delivery of the items assigned to you with quality and should interact with cross functional team and resolve the problem. You should excel in working with global stakeholders and have outstanding communication and leadership skills and report to the Project Manager. What You'll Do: Lead the UVM verification team, focusing on high-performance digital designs. Manage UVM based verification strategies for FPGA designs, System Verilog, ensuring compliance with industry standards. Collaborate with cross-functional teams to achieve project milestones. Develop and execute FPGA verification plans using advanced methodologies like UVM. UVM Verification environment development Perform verification environment using UVM methodologies, create verification environments for high-speed protocols like Multi gigabit ethernet interface, AXI Stream, AXI Lite, verification IP development, Knowledge of encryption/decryption standards like AES, knowledge of PCI express, DDR4 interface on FPGAs and its verification environment creation using UVM Mentor junior engineers and oversee team deliverables. Work closely with FPGA design engineers to ensure seamless integration. Qualifications : BE/MTech in Electronics and communications engineering 6+ years of experience in UVM verification. Very strong knowledge of SystemVerilog and usage of latest FPGAs Proficiency in UVM, and scripting languages like Python or Perl. Knowledge of Siemens Questa UVM simulator, writing custom scripting for the tools (like TCL, FuseSoC, etc), analyze and debug the environment by waveforms. Familiarity with high-speed interfaces like PCIe, Multi giga bit Ethernet, and DDR4. Strong leadership and communication skills.

Handson experience of baremetal FW development in Pre Si w/ UVM TB, debugging FW using Verdi/Sim Vision along with RTL,basic signal tracing in Verilog, High-Speed Serial I/F for 2yrs : UCIe, PCIe, CXL, HBM, Qlink (Qualcomm), DigRF (MIPI)

We are looking for a highly skilled and experienced Branch Receivable Manager to join our team at Equitas Small Finance Bank. The ideal candidate will have 1-10 years of experience in the BFSI industry, preferably with a background in Assets, Inclusive Banking, SBL, Mortgages, or Receivables. Roles and Responsibility Manage and oversee branch receivables operations for efficient cash flow. Develop and implement strategies to improve receivables management. Collaborate with cross-functional teams to resolve customer issues and enhance service quality. Analyze and report on receivables performance metrics to senior management. Ensure compliance with regulatory requirements and internal policies. Lead and motivate a team of receivables professionals to achieve business objectives. Job Requirements Strong knowledge of BFSI industry trends and regulations. Experience in managing branch receivables operations and teams. Excellent communication and interpersonal skills. Ability to analyze data and make informed decisions. Strong problem-solving and leadership skills. Familiarity with financial software and systems is an advantage. Additional Info For more information, please contact us at 1388106.

We are looking for a highly skilled and experienced Branch Receivable Officer to join our team at Equitas Small Finance Bank. The ideal candidate will have 2-6 years of experience in the BFSI industry, preferably with a background in Assets, Inclusive Banking, SBL, Mortgages, or Receivables. Roles and Responsibility Manage and oversee branch receivables operations for timely and accurate payments. Develop and implement strategies to improve receivables management and reduce delinquencies. Collaborate with cross-functional teams to resolve customer complaints and issues. Analyze and report on receivables performance metrics to senior management. Ensure compliance with regulatory requirements and internal policies. Maintain accurate records and reports of receivables transactions. Job Requirements Strong knowledge of BFSI industry trends and regulations. Experience in managing branch receivables operations. Excellent communication and interpersonal skills. Ability to work in a fast-paced environment and meet deadlines. Strong analytical and problem-solving skills. Proficiency in Microsoft Office and other relevant software applications.

We are looking for a highly motivated and experienced Branch Receivable Officer to join our team at Equitas Small Finance Bank. The ideal candidate will have 1-3 years of experience in the BFSI industry, preferably with a background in Assets, Inclusive Banking, SBL, Mortgages, or Receivables. Roles and Responsibility Manage and oversee branch receivables operations for timely and accurate payments. Develop and implement strategies to improve receivables management and reduce delinquencies. Collaborate with cross-functional teams to resolve customer complaints and issues. Analyze and report on receivables performance metrics to senior management. Ensure compliance with regulatory requirements and internal policies. Maintain accurate records and reports of receivables transactions. Job Requirements Strong knowledge of BFSI industry trends and regulations. Experience in managing assets, inclusive banking, SBL, mortgages, or receivables. Excellent communication and interpersonal skills. Ability to work in a fast-paced environment and meet deadlines. Strong analytical and problem-solving skills. Proficiency in Microsoft Office and other relevant software applications.

We are looking for a highly skilled and experienced Branch Receivable Officer to join our team at Equitas Small Finance Bank. The ideal candidate will have 1-5 years of experience in the BFSI industry, preferably with a background in Assets, Inclusive Banking, SBL, Mortgages, or Receivables. Roles and Responsibility Manage and oversee branch receivables operations for timely and accurate payments. Develop and implement strategies to improve receivables management and reduce delinquencies. Collaborate with cross-functional teams to resolve customer complaints and issues. Analyze and report on receivables performance metrics to senior management. Ensure compliance with regulatory requirements and internal policies. Maintain accurate records and reports of receivables transactions. Job Requirements Strong knowledge of BFSI industry trends and regulations. Experience in managing branch receivables operations. Excellent communication and interpersonal skills. Ability to work in a fast-paced environment and meet deadlines. Strong analytical and problem-solving skills. Proficiency in Microsoft Office and other relevant software applications.

We are looking for a highly skilled and experienced Branch Receivable Officer to join our team at Equitas Small Finance Bank. The ideal candidate will have 1 to 6 years of experience in the BFSI industry, preferably with a background in Assets, Inclusive Banking, SBL, Mortgages, or Receivables. Roles and Responsibility Manage and oversee branch receivables operations for timely and accurate payments. Develop and implement strategies to improve receivables management and reduce delinquencies. Collaborate with cross-functional teams to resolve customer complaints and issues. Analyze and report on receivables performance metrics to senior management. Ensure compliance with regulatory requirements and internal policies. Maintain accurate records and reports of receivables transactions. Job Requirements Strong knowledge of BFSI industry trends and regulations. Experience in managing branch receivables operations. Excellent communication and interpersonal skills. Ability to work in a fast-paced environment and meet deadlines. Strong analytical and problem-solving skills. Proficiency in Microsoft Office and other relevant software applications.

Responsibilities 6 to 12 years of complete hands-on experience in RTL Verification at both SoC/IP level. Should be proficient in building New or maintain existing SV/UVM/C based testbenches. Experienced in SV-UVM/OVM/VMM Methodologies. Specman hands-on can be a plus. Should have handled Complex Blocks/Hard Macro Level Functional Verification at both RTL and Gate Level. Should have experience dealing with Coverage Models and metrics issue and closure based on specification. Able to develop and track Test Plan & Validation Plans based on Specification. Able to setup Regression environments based on Test Plans. Experience in dealing GPIO, Clock Controller, DFTMUX, System controller such as PMU/CMU/TMU and power issues at SoC level will be an advantage. Knowledge on Power-Aware -CPF/UPF Simulation at both RTL and Timing Simulations at Gate Level. Able to Work closely with the Architecture, Design, Synthesis and Physical Design team teams to resolve the RTL/GLS level issues. Should have knowledge on any of the Bus interface - PCIe/USB/I2C/SPI/UART. Should have worked on AMBS protocols. Technologies: 28nm and below. Experience in Tcl/Tk, PERL, Makefile is a definite Plus. Qualifications Education: B.Tech/BE/ME/M.Tech

Job Description : - Expertise in the verification of IP or SOC cores. - Must have proven experience in developing HVL (System Verilog/UVM) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage and Code coverage. - Experience in CXL / DDR / MIPI / PCIe Protocol - Understanding of BIST would be an added advantage. - Familiarity with HDL's such as Verilog and scripting languages such as shell/Perl/Python etc.is highly desirable - Good communication skills, debug and problem solving skills. - Be a technical contributor in the Verification Tasks - System Verilog/Verilog coding of test benches, Test cases, performing verification tasks such as coverage, debug, regressions using the latest methodologies such as UVM. - Work closely with team members to deliver quality products. - Be able to study the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/ product specs - Works in a project and team oriented environment - Preferred GCC / USC or candidates with valid H1B

Ability to lead MSV and/or DV verifications. Involved in verification for IPs . Handling project dynamics on scope, schedule and effort - coming up with alternative verification plans, Mentoring Junior engineer. Test plan preparation as per the dynamics of product specifications. Behavioral modeling: Verilog, real or SV-RNM . Dealing challenges with AMS methodologies of Cadence : irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS. Testcase Debug & proposing new scenarios. Ability to strategize optimization of simulation bench for simulation time. Your Profile You are best equipped for this task if you have: Bachelors with 9+ years or Masters with 8+ years of experience. Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage. HDL/HVL : Verilog / Verilog-ams , SV/UVM added advantage. Tools: Cadence Xceliumspectre / Synopsys XA-VCS / Mentor Eldo ADMS . Automation: Perl/python/shell. Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements. Ability to drive projects and debug independently

Behavioral modeling: Verilog, Wreal or SV-RNM -Full AMS Verification for SoC or IPs -Full Test plan preparation as per the dynamics of product specifications - Full Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -Partial Testcase Debug & proposing new scenarios - Partial Handling project dynamics on scope, schedule and effort - coming up with alternative verification plans- Full Self-motivated to drive new scope expansion proposals mapping to business value Mentoring junior engineers in creating problem solving mindset Establishing cross collaboration with other domains and coming up with proposals in enhancing product development working approaches You are best equipped for this task if you have: Bachelors with 5+ years of experience Mentoring: Technical mentoring for junior engineers. Instigate thought-provoking culture. Analog: Functional spec understanding of standard power management blocks, clock circuits, and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements

- Expertise in the verification of IP or SOC cores. - Must have proven experience in developing HVL (System Verilog/UVM) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage and Code coverage. - Experience in CXL / DDR / MIPI / PCIe Protocol - Understanding of BIST would be an added advantage. - Familiarity with HDL's such as Verilog and scripting languages such as shell/Perl/Python etc.is highly desirable - Good communication skills, debug and problem solving skills. - Be a technical contributor in the Verification Tasks - System Verilog/Verilog coding of test benches, Test cases, performing verification tasks such as coverage, debug, regressions using the latest methodologies such as UVM. - Work closely with team members to deliver quality products. - Be able to study the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/ product specs - Works in a project and team oriented environment - Preferred GCC / USC or candidates with valid H1B

Experience in construction, foundations, and maintenance work Project execution and quality checks Bill checking, rate analysis, BOQ preparation Bar chart preparation and coordination with team KeyResponsibilities: Handle industrial construction projects Execute and inspect work as per project requirements Assist in bill verification and BOQ tasks Support maintenance and ongoing project work Prepare progress reports and ensure team coordination

We are looking for a highly skilled and experienced Branch Receivable Manager to join our team at Equitas Small Finance Bank. The ideal candidate will have 7-10 years of experience in the BFSI industry, with expertise in Assets, Inclusive Banking, SBL, Mortgages, and Receivables. Roles and Responsibility Manage and oversee branch receivables operations for efficient cash flow. Develop and implement strategies to improve receivables management. Collaborate with cross-functional teams to resolve customer issues and enhance service quality. Analyze and report on receivables performance metrics to senior management. Ensure compliance with regulatory requirements and internal policies. Lead and motivate a team of receivables professionals to achieve business objectives. Job Requirements Strong knowledge of BFSI industry trends and regulations. Experience in managing assets, inclusive banking, SBL, mortgages, and receivables. Excellent leadership and communication skills. Ability to analyze data and make informed decisions. Strong problem-solving and customer service skills. Proficiency in financial software and systems.

Role : Design Verification Engineer Location: Hitech city ,Hyderabad Qualification: Bachelor's Degree Experience : 2-6 years of professional experience. Work Mode : Work from office, 5 days a week. Job Description Strong Familiarity with System Verilog and OVM/UVM Verification Methodology. Knowledge of system-level architecture including buses like AXI/AHB/APB/ACE5 Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, Model Sim . Proficiency in developing the TB environment Good Knowledge on writing coverage and assertions Good knowledge in scripting(Perl/Tcl/Python) and automation of verification flows/process Knowledge on the PCIE is required. Knowledge of mipi, video Ips like ISP/Encoder/Decoder would be useful. Functional Skills Ability to work with cross-functional teams