Posted:1 week ago|
Platform:
Work from Office
Full Time
Expertise in ASIC verification, Expertise in System Verilog and UVM, Verilog. Experience in technical lead , leading a team of 2-5 engineers. Expertise in IP level verification, testbench architecture development, Testbench component developments. Expertise in coverage closer, code coverage, functional coverage Experience in Gate level simulations. The candidate should be able to define verification plan, create testbenches, testcases,gate level simulations etc independently. Knowledge on serial protocols PCIe, USB, UFS Knowledge on scripting languages like Python, Perl etc. Keen on continuous process improvement to improve Quality and time
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