548 Uvm Jobs - Page 15

Expertise in UVM and System Verilog. Experience in verification IP modeling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol. Job Responsibilities: Able to contribute to the development of the VIP. Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology

Working on Functional Verification of High-Speed PHY IPs for DDRxx, LPDDRxx, PCIex, Display, and HDMI protocol standards. Studying IP/design blocks/Firmware Specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Developing DV/Firmware test benches, test plans, and test cases. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs). Performing simulation, random and focused stimulus generation, and coverage analysis. Collaborating closely with digital designers for debugging and achieving desired coverage. Developing architecture and micro-architecture knowledge of complex digital design blocks under test. The Impact You Will Have: Ensuring the high quality and reliability of our High-Speed PHY IPs. Contributing to the successful delivery of cutting-edge technology solutions. Enhancing the performance and functionality of our products through rigorous verification. Driving innovation and excellence in our verification processes. Supporting the rapid integration of capabilities into SoC designs. Enabling our customers to bring differentiated products to market quickly with reduced risk. What You'll Need: B. Tech/M. Tech in EC/CS with 3-6 years of relevant experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs. Understanding of functional verification flow with experience on industry-standard development and verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in System Verilog Assertions, code and functional coverage implementation, and review. Excellent debug and diagnostic skills. Experience with scripting and automation using TCL, PERL, or Python.

What You ll Need: MSEE or BSEE with 10+ years of digital design and verification experience. Strong understanding of verification methodologies like System Verilog and UVM. Familiarity with RTL coding and design principles. Proficiency in scripting languages like Perl and Python for automation. Excellent debugging and troubleshooting abilities. Experience with test chip and full chip knowledge is an advantage. Proven leadership and team-building skills.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a highly skilled and experienced SoC Verification Lead with a passion for pushing the boundaries of technology With a minimum of 12 years of experience in the SoC/IP/Subsystems verification domain, you possess deep technical expertise in various aspects of pre-silicon verification, including UVM, coverage analysis, verification plan creation, and debugging You have a strong understanding of design concepts and ASIC flows, and you are adept at leading teams to perform verification on complex SoC/IP/Subsystems Your knowledge of protocols such as PCIe, Ethernet, USB, and DDR, along with your hands-on experience with verification tools like VCS, waveform analyzers, and third-party VIP integration, makes you an invaluable asset Excellent communication skills and the ability to mentor and guide your team are key aspects of your profile You are proactive, able to anticipate and mitigate risks, and committed to adhering to high-quality standards, What Youll Be Doing: Working with Synopsys customers to understand their needs and define verification scope and activities, Understanding the complexity and requirements of verification and proposing resource requirements to complete the activities, Leading a team of engineers to perform various pre-silicon verification activities on IPs/Subsystems, Anticipating problems and risks and working towards a resolution and risk mitigation plan, Assisting and mentoring the team in day-to-day activities and growing the capabilities of the verification team for future assignments, Reviewing various results and reports to provide continuous feedback to the team and improve the quality of deliverables, Reporting status to management and providing suggestions to resolve any issues that may impact execution, Collaborating with architects, designers, and pre and post-silicon verification teams to accomplish your tasks, Adhering to quality standards and good test and verification practices, Ramping up on new Verification tools and methodologies using Synopsys Products to enable customers, Working with other Synopsys teams including BU AEs and Sales to develop, broaden, and deploy Tool and IP solutions, The Impact You Will Have: Driving the success of customer projects by ensuring robust and thorough verification of SoC designs, Enhancing Synopsys reputation as a leader in verification through high-quality deliverables and customer satisfaction, Mentoring and growing the verification team, building a strong foundation for future projects, Identifying and mitigating risks early, ensuring smooth project execution and delivery, Improving verification methodologies and practices, contributing to the overall efficiency and effectiveness of the team, Collaborating with cross-functional teams to achieve seamless integration and execution of verification activities, Providing valuable feedback and insights that drive continuous improvement in verification processes and tools, What Youll Need: E/B Technical expertise in various aspects of pre-silicon Verification (UVM, Coverage Analysis, Verification plan creation, debugging, etc), Good knowledge of various protocols (PCIe, Ethernet, USB, DDR, etc) and/or processor/interconnect/debug architecture, Hands-on experience with verification tools such as VCS, waveform analyzers, and third-party VIP integration (such as Synopsys VIPs), Ability to lead a team to perform verification on complex SoC/IP/Subsystems, Experience with planning and managing verification activities for SoC/Subsystems/IPs, Strong understanding of design concepts, ASIC flows, and stakeholders, Good communication skills, Who You Are: A proactive and detail-oriented leader who can guide and mentor a team, An excellent communicator who can collaborate effectively with cross-functional teams, A problem-solver who can anticipate challenges and develop effective mitigation strategies, A continuous learner who stays updated with the latest verification tools and methodologies, A team player who values quality and strives for excellence in deliverables, The Team Youll Be A Part Of: The System Solutions Group (SSG) at Synopsys delivers tool, methodology, architecture, design creation, design verification, and physical implementation expertise to enable leading-edge customers to complete their most challenging SoC design projects Our work spans from sub-blocks to full turnkey end-to-end SoCs Our customers range from start-ups to industry leaders, commercial companies, and government agencies Our customers develop SoCs for high-performance computing, automotive, aerospace & defense, and more, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a skilled Emulation R&D Engineer with over 8 years of experience and a strong academic background in Electronic & Communication or Computer Science Engineering Your expertise in C/C++, OOPS, and HDL languages like System Verilog and Verilog, along with your scripting skills in Perl or TCL, make you a valuable team member You possess knowledge of protocols such as ENET, HDMI, MIPI, AMBA, and UART, and have experience with UVM and Functional Verification You are a resourceful problem-solver, a team player, and have excellent communication skills, What Youll Be Doing: Designing and developing emulation models, Implementing and verifying digital designs using System Verilog and Verilog, Developing scripts in Perl, TCL, or other languages, Collaborating with cross-functional teams, Conducting protocol verification for various standards, Utilizing UVM for design validation, The Impact You Will Have: Enhancing emulation model efficiency, Contributing to high-performance silicon chips, Improving design reliability through verification, Streamlining workflows with automation, Ensuring protocol compliance, Driving technological advancements, What Youll Need: E / M Proficiency in C/C++ and OOPS, Knowledge of digital design and HDL languages, Experience with scripting languages, Familiarity with multiple protocols like ethernet, pcie, cxl, CSI, DSI, UFS AMBA, CHI and UVM, Who You Are: Effective communicator, Team player, Resourceful and detail-oriented, Innovative problem-solver, Adaptable learner, The Team Youll Be A Part Of: Join a dynamic team dedicated to developing and verifying advanced emulation models for high-performance silicon chips Collaborate with cross-functional teams to ensure seamless integration and adherence to industry standards, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits Your recruiter will provide more details about the salary range and benefits during the hiring process, Inclusion and Diversity: Synopsys considers all applicants for employment without regard to race, color, religion, sex, gender preference, national origin, age, disability, or status as a Covered Veteran in accordance with federal law,

Key Qualifications Proven desire to learn and explore new state of the art technologies Demonstrate good written and spoken English communication skills Demonstrate good review and problem-solving skills Knowledgeable with Verilog, VHDL and/or SystemVerilog Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus Understanding of verification methodology such as UVM . Good organization and communication skills Be a solution provider. 8+ years of relevant experience

You are an experienced ASIC Digital Design Engineer with a deep understanding of interface protocols such as USB2/3/3.1, PCIe Gen1/2/3/4/5/6, Ethernet, and JESD204B. With a solid background in SERDES/PHY/Controller IP specification and compliance validation, you thrive in dynamic environments where your expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM) is highly valued. You are passionate about delivering high-quality RTL and simulation models, and you excel in developing and reviewing verification plans and environments. Your proactive approach to problem-solving, coupled with your ability to support customers during silicon bring-up and debug phases, makes you an invaluable asset to any team. Your technical prowess is matched by your excellent communication skills, enabling you to effectively collaborate and influence across departments and with external partners. What You'll Be Doing: Developing and reviewing verification plans for SERDES/PHY/Controller IPs. Creating and maintaining verification environments, with a preference for UVM. Conducting RTL, GLS, and co-simulations to ensure comprehensive coverage closure. Delivering high-quality RTL and simulation models to customers. Using third-party VIP for protocol verification and simulation bring-up of protocol subsystems. Supporting customers with IP integration, silicon bring-up, and debugging issues. Demonstrating Testchip+FPGA system demos to customers and at conferences. The Impact You Will Have: Ensuring the compliance and functionality of our interface IPs with industry protocols. Enhancing the quality and reliability of our silicon solutions for customers. Facilitating smooth customer adoption and integration of our IPs. Contributing to successful silicon bring-up and debugging efforts. Showcasing our technological advancements at industry events. Driving innovation and excellence in digital design and verification processes. What You'll Need: Expertise in one or more interface protocols (e.g., USB, PCIe, Ethernet, JESD204B). Proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM). Experience with SERDES/PHY/Controller IP specification and compliance validation. Strong background in developing and reviewing verification plans and environments. Ability to deliver high-quality RTL and simulation models to customers.

You are a seasoned digital verification engineer with a passion for innovation and problem-solving With a BE/b-tech degree in electronics or a related engineering field, you bring 3-5 years of hands-on experience in digital verification Your proficiency in system verilog, UVM, coupled with a strong understanding of formal verification techniques, sets you apart You thrive in UNIX/Linux OS environment and have a keen interest in exploring new technologies Your ability to build UVM based testbenches , along with your prior knowledge of EDA tools and simulators, makes you an ideal candidate Excellent English communication skills and the ability to compile verification plans and strategies are essential for this role, What Youll Be Doing: Creation of test plans Development of testbenches Creation of tests both directed and random Functional coverage modelling and review, Code coverage review Debugging and resolving mismatches between design and C-model Integration of third party and internal verification IP Review and improvement of verification test suites and testbench Mentor junior team members Creation of Test plan, test strategy Coverage databases (Fully traceable from test plan and specification) The Impact You Will Have: Driving innovation in processor verification techniques Enhancing the efficiency and effectiveness of our verification mechanisms Contributing to the development of cutting-edge technology that sets Synopsys apart in the industry Ensuring high-quality IP delivery through rigorous verification Supporting the continuous improvement of our hardware verification processes What Youll Need: Bachelors degree in engineering from a reputed college Minimum 3+ years of relevant experience Microprocessor verification experience is an advantage Hands-on experience with SystemVerilog and Verilog Proficiency with Verification methodologies: UVM/OVM Programming skills: C, assembly, Perl, makefile generation Experience with latest verification techniques like formal, low-power, safety etc is an added advantage Who You Are: Innovative thinker with a passion for technology Excellent communicator and collaborator Detail-oriented and highly organized Adept at problem-solving and critical thinking Proactive and self-motivated The Team Youll Be A Part Of: You will be part of a dynamic and innovative team focused on developing and verifying ARC processor IPs Our team values collaboration, creativity, and continuous improvement, and we are dedicated to pushing the boundaries of technology to deliver exceptional products,

Responsibilities : - Develop and execute comprehensive verification plans for complex IP blocks and SoCs, including microarchitecture, functional, and performance verification.- Design and implement high-quality testbenches using industry-standard methodologies (e.g., UVM, OVM).- Develop and maintain test suites, including directed tests, constrained random tests, and coverage-driven tests.- Debug and troubleshoot complex verification issues, analyze simulation results, and identify root causes of failures.- Collaborate closely with design engineers, architects, and other verification engineers to ensure timely and successful chip delivery.- Participate in design reviews and contribute to the design process.- Stay abreast of the latest verification methodologies, tools, and industry trends.- Document and report on verification progress, issues, and risks. Qualifications : - 4-7 years of professional experience in functional verification of complex digital designs (IP/SoC).- Strong understanding of digital design fundamentals and verification methodologies.- Expertise in developing and executing testbenches using industry-standard methodologies (e.g., UVM, OVM).- Experience with SystemVerilog, C/C++, and scripting languages (e.g., Perl, Python).- Good understanding of cache coherency protocols.- Experience with high-speed protocols (e.g., PCIe, DDR, Ethernet) is a plus.- Experience with UPF (Unified Power Format) and low-power simulation is a plus.- Excellent problem-solving, analytical, and debugging skills.- Strong communication and interpersonal skills.- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.

Greeting with HCL Tech! We were looking somebody who is having experience in Design Verification Experience: 4 to 10 Years Location: Kochi Job Description: General verification expertise System Verilog. UVM Understanding of ARM processor based SOCs, AXI / AHB Good knowledge of Processor based C tests for SOC verification (test coding, compilation, loading in TB, failure debug) Strong hands on work experience of test development, simulation along with usage of popular EDA tools Good debug skills – Check that engineer has done reasonable amount of debug in past projects Has logical and methodical approach to debug issues /failures Has used standard tools for debugging, as applicable

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Functional Verification of Processors or ASICs. Minimum 3+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Preferred technical and professional experience Verify the different functions/components in a PCI Express Controller & high speed SERDES (PHY). Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug Formal verification experience

Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We craft the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by crafting, developing and testing some of the most sophisticated ASICs being developed in the industry. You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle. Your Impact You will contribute to developing Ciscos progressive data center solutions by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include: Architect block, cluster and top-level DV environment infrastructure. Develop DV infrastructure from scratch. Maintain and improve existing DV environments. Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus. Ensure complete verification coverage through implementation and review of code and functional coverage. Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist. Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and efficient performance. Support testing of design in emulation. Lead all aspects of and manage the ASIC bring-up process. Minimum Qualifications Bachelors Degree or equivalent experience in EE, CE, or other related field. 7+ years of related ASIC design verification experience. Proficient in ASIC verification using UVM/System Verilog. Proficient in verifying sophisticated blocks, clusters and top level for ASIC. Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes. Scripting experience with Perl and/or Python. Preferred Qualifications Masters Degree in EE or CE with 5+ years of relevant work experience. Experience with Forwarding logic/Parsers/P4. Experience with Veloce/Palladium/Zebu/HAPS. Formal verification (iev/vc formal) knowledge. Demonstrated ability on one or more protocols (PCIe, Ethernet, RDMA, TCP).

Role & responsibilities Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment

ASIC Design Verification Engineer || UVM/System Verilog || Test benches || Exp 4 to 7 years Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Who You'll Work With You will engage in dynamic collaboration with verification engineers, designers, and cross-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle. Your Impact You will contribute to developing Ciscos revolutionary data center solutions by designing industry-leading complex chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include: Architect block, cluster and top-level DV environment infrastructure. Develop DV infrastructure from scratch for block and cluster level environments. Maintain and enhance existing DV environments. Develop test plans and tests for qualifying design at block, and cluster level environments with mix of constraint random and directed stimulus. Ensure complete verification coverage through implementation and review of code and functional coverage. Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist. Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and optimal performance. Support testing of design in emulation. Minimum Qualifications Bachelors Degree in EE, CE, or other related fi eld. 5+ years of related ASIC design verification experience. Proficient in ASIC verification using UVM/System Verilog. Proficient in verifying complex blocks and/or clusters for ASIC. Experience building test benches from scratch, hands on experience with SystemVerilog constraints, structures and classes. Scripting experience with Perl and/or Python. Preferred Qualifications Experience with Forwarding logic/Parsers/P4. Experience with Veloce/Palladium/Zebu/HAPS. Formal verification (iev/vc formal) knowledge. Domain experience on one or more protocols (PCIe, Ethernet, RDMA, TCP).

Key Responsibilities: Good understanding of verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM. Experience and knowledge in Verification of IPs related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Should be able to understand the Full-chip Verification requirements as well and good knowledge in industry standard protocols. Verification for complex IPs and close the Verification to the challenging milestones. Strong knowledge of AXI4/AXI5 protocol Strong understanding of Coherency rules in ACE and ACE5 Experience with architecting BFMs/VIPs Should be able to handle a team of 3-4 engineers (for senior position). IP Verification: VR creation as per the chip requirements and UVM/OVM Test benches creation Support in building verification infrastructure at the chip level as per the requirements Capable of handling multiple areas of IP Verification: RTL, Power Aware and Gate Level Verification Strong in SV and UVM. PCIe Gen5 Tetsbench development experience is required. CXL2.0/3.0 protocol working experience will be added advantage Skills and Qualifications: Education: B.Tech/B.E. or M.Tech/M.S. in Electronics, Electrical Engineering, or a related field. Experience: 3-14 years of hands-on experience in ASIC design verification. Tools & Technologies: Proficiency in hardware description languages (Verilog, VHDL, System Verilog). Familiarity with UVM (Universal Verification Methodology) and other verification methodologies. Experience with simulation and debugging tools (ModelSim, VCS, Questa). Knowledge of scripting languages (Python, Tcl, Perl) for test automation. Experience with version control tools such as Git or SVN. Familiarity with formal verification tools and techniques is a plus. Desired Skills: Strong understanding of digital logic design, state machines, and timing analysis. Ability to work independently and collaboratively within a team environment. Strong problem-solving and analytical skills. Good communication skills to effectively report verification results and progress. Preferred Qualifications: Experience with high-level synthesis tools. Knowledge of low-power design techniques. Familiarity with performance verification and hardware-software co-verification.

Lead the unit level pre-silicon functional & performance verification the Instruction Sequencing Unit for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for ISU which covers the Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of Instruction Dispatch verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing Issue Queues, Register renaming and forwarding, Reordering Buffer and Pipeline flush/exception handling etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic units. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Strong knowledge in SV,UVM Skills: SOC/IP Verification Protocol: Ethernet/PCIe Experience: 4+ Years Should have Scripting knowledge Need experience in 2 tape outs projects

Deliver comprehensive training on VLSI Design and Verification, covering topics like Digital Design, Verilog/System Verilog, RTL Design, and UVM. Prepare, update, and structure course materials and assignments as per industry standards.

Education: Bachelor's Degree (BE / BTech) or Master's Degree (ME / MTech) Job Description ASIC Verification Lead Summary of the offer: Integrating ASIC functional verification team. ASIC developed include network controller, router and cache coherence controller targeting Bull high-end servers and Bull high-performance ("big data" and "exascale" servers). Using Constraint-Random, Coverage Driven functional verification methodologies underlying UVM verification framework to ensure full and effective verification of complex ASIC. Main responsibilities: Acquire knowledge of the architecture and microarchitecture of the ASIC by studying specifications and interacting with the architecture and logical design teams. Participate in defining overall verification strategies and methodologies, and the required simulation environments. Develop, maintain and publish verification specifications. Write and perform closely test plans with the logical design team. Develop coverage models and verification environments using UVM-SystemVerilog / C ++ Monitor, analyze and debug simulation errors. Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time. Submit recommendations on tools and methodologies to develop to improve productivity. Mentor junior engineers on how to produce a maintainable and reusable code across projects. Skills: Participated in the successful verification of a complex SoC or ASIC. Mastering UVM or equivalent verification methodology. Proficient developer of Constraint-Random / Coverage-Driven verification environments in SystemVerilog / C ++ (drivers / monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp / SVA) Strong knowledge of simulation tools and coverage database visualization tools Developed test plans that helped identifying sharp functional defects. efficiency in problem solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints Experienced in improving processes and methodologies Experience in managing tasks for a small team. Required minimum experience: 7 years Required minimum studies: Master/Engineer in Electronics and Communication Engineering.

Designation: Technical Support Engineer - VLSI Experience : 0-1 Years Education : B.tech/ BE- or M.Tech VLSI. ECE/ Diploma in Mechatronics/ECE Industry Type: Education / E-Learning / Semiconductor Category: Technical Job Description Responsible for development and support of Projects. Responsible for debugging the source codes in Verilog, SV, and UVM. Responsible for Monitoring the trainee's progress. Will be a point of contact for trainees to query on Technical concepts. Desired Candidate Profile Sound Knowledge on Verilog, SV, Digital ,UVM / Back-end design Good communication skill. Should be good in Digital Electronics. For more details, kindly contact 7406043555, fiza@maven-silicon.com

1.Must Have: SoC or IP 2.Experience Languages : System Verilog (must) 3.Methodologies: OVM/UVM/VMM 4.Protocols:DDR/USB/Ethernet/PCIE/Video/HDMI/MIPI/DSI/CSI 5.Processor/ARM Based SoC Verification experience 6.Candidate must have expertise in System Verilog. 7.Experience in ARM base SoC Verification 8.Strong Analytical skills desirable if having worked.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: DV Engineers DDR (either IP or SoC level experience) Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Define and implement verification strategies and test plans for DDR memory interface designs. Develop UVM/SystemVerilog-based testbenches and reusable verification components. Perform protocol-level verification for DDR memory interfaces and validate compliance. Collaborate with architecture, RTL, and system teams to understand design intent and corner cases. Own functional coverage, regression setup, and closure. Integrate DDR models, controllers, PHYs, and validate their interactions. Debug and resolve simulation failures and functional issues. Drive code and functional coverage improvements to ensure thorough verification. Lead or participate in technical reviews and mentor junior engineers. Required Skills & Experience: 10+ years of hands-on experience in ASIC/IP/SoC verification. Strong expertise in SystemVerilog, UVM, and functional coverage methodology. In-depth understanding and working experience with DDR3/DDR4/DDR5/LPDDR protocols. Experience with DDR controllers, PHY integration, and JEDEC standards. Proficient in simulation and debug tools such as Synopsys VCS, Cadence Xcelium, QuestaSim, etc. Good scripting skills in Python, Perl, or Shell for automation and regression management. Excellent debugging and problem-solving skills. Familiarity with AXI/AHB protocols and interconnects is a plus. Experience working with memory models and timing analysis. Preferred Qualifications: Experience with post-silicon validation or DDR hardware bring-up. Knowledge of formal verification tools and techniques. Experience with low power verification and timing closure tools. TekWissen Group is an equal opportunity employer supporting workforce diversity.

Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices. In your new role you will: Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices. Responsible for: Designing self-checking test benches using modern verification techniques Implementing functional coverage and assertions using System Verilog and UVM. Developing TB environment using SV and UVM. Developing test and functional coverage plans based on device specifications. Analyzing and debugging simulation failures, as we'll as analyzing functional coverage results to guarantee zero defect outcomes. You are best equipped for this task if you have: Engineering in Electrical/electronic streams , or equivalent experience. 2+ years experience in constrained-random, coverage driven verification environments. Experience in RAL Experience in developing the test bench from scratch using System Verilog (SV) HDVL and UVM (Universal Verification Methodology). Expertise in Gate Level simulations (GLS) and have debugged, root caused real netlist issues. A solid understanding of verification concepts and experience designing class-based test benches. C coding, Formal verification methods and Power aware simulation will be an advantage Excellent written and oral communication skills Strong debugging skills, functional simulations and GLS simulations.

Summary Established in 2001, EnSilica is a publicly listed company (LON:ENSI), designing industry leading, application specific integrated circuit chips (ASIC), for customers ranging from start-ups to blue chip companies, in industries including: automotive, medical, space and mobile technology companies. With its head office on Milton Park, Oxfordshire, and other offices in Bristol, Sheffield, Brazil (Porto Alegre) and India (Bangalore), EnSilica currently employs more than 160 people. We are looking for a very experienced verification engineer who can not only strengthen the team through their technical expertise but also bring leadership and grow the verification business within EnSilica. You will have a good understanding of different methodologies, but particularly SystemVerilog and UVM. Faced with a new project, you will have the ability to quickly assimilate the verification challenge and help define an effective and pragmatic verification strategy and gain the support of the end-customer for the chosen approach. You will need to understand the importance of monitoring key metrics to assess progress and predict the end-point for the verification process. Responsibilities Verification specialist working on customer and internal projects often as the verification lead. Provide high-class verification support to a wide range of projects using a range of advanced verification techniques including constrained random, coverage driven, assertion-based and formal methods. You would also be responsible for the development of a comprehensive verification strategy and plan, along with the architecting and development of the complete test environment. Active participation in the verification community to drive the introduction of new and effective techniques within our business to help solve the verification challenges faced by our customers. Close working with our customers to build a strong relationship that results in repeat business. Education / Key Skills / Experience BE/ME in Electronics /Computer Science 1 group University. 15+ years experience in industry working on a variety of verification projects. Extensive knowledge of verification methodologies particularly UVM and SystemVerilog. Strong experience in the specification and implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog. Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests. Strong VHDL/Verilog RTL. Very good understanding of modern verification flows and methodologies and able to influence the EnSilica one toward continuous improvement Ideally you will be familiar with both Mentor Questa and Cadence Incisive tool and ideally some exposure to low power verification using UPF based flows A good understanding of functional safety and quality processes, to achieve ISO26262 or similar standards compliances will be considered as a strong plus Personality Excellent communication and interpersonal skills. Strong and effective presentation skills, able to operate at multiple levels including senior management. Self-motivated achiever who gains satisfaction from providing excellent customer service and has a can-do attitude. Happy to take ownership of problems and provide suitable solutions. Creative problem solving. Team player. Ability to work in a dynamic environment.