500 System Verilog Jobs

We are looking for a highly skilled and experienced Branch Receivable Officer to join our team at Equitas Small Finance Bank. The ideal candidate will have 1-4 years of experience in the BFSI industry, preferably with a background in Assets, Inclusive Banking, SBL, Mortgages, or Receivables. Roles and Responsibility Manage and oversee branch receivables operations for timely and accurate payments. Develop and implement strategies to improve receivables management and reduce delinquencies. Collaborate with cross-functional teams to resolve customer complaints and issues. Analyze and report on receivables performance metrics to senior management. Ensure compliance with regulatory requirements and internal policies. Maintain accurate records and reports of receivables transactions. Job Requirements Strong knowledge of BFSI industry trends and regulations. Experience in managing assets, inclusive banking, SBL, mortgages, or receivables. Excellent communication and interpersonal skills. Ability to work in a fast-paced environment and meet deadlines. Strong analytical and problem-solving skills. Proficiency in Microsoft Office and other relevant software applications.

We are looking for a highly skilled and experienced Branch Receivable Officer to join our team at Equitas Small Finance Bank. The ideal candidate will have 1-4 years of experience in the BFSI industry, preferably with a background in Assets, Inclusive Banking, SBL, Mortgages, or Receivables. Roles and Responsibility Manage and oversee branch receivables operations for timely and accurate payments. Develop and implement strategies to improve receivables management and reduce delinquencies. Collaborate with cross-functional teams to resolve customer complaints and issues. Analyze and report on receivables performance metrics to senior management. Ensure compliance with regulatory requirements and internal policies. Maintain accurate records and reports of receivables transactions. Job Requirements Strong knowledge of BFSI industry trends and regulations. Experience in managing assets, inclusive banking, SBL, mortgages, or receivables. Excellent communication and interpersonal skills. Ability to work in a fast-paced environment and meet deadlines. Strong analytical and problem-solving skills. Proficiency in Microsoft Office and other relevant software applications.

We are looking for a highly skilled and experienced Branch Receivable Officer to join our team at Equitas Small Finance Bank. The ideal candidate will have 1-4 years of experience in the BFSI industry, preferably with a background in Assets, Inclusive Banking, SBL, Mortgages, or Receivables. Roles and Responsibility Manage and oversee branch receivables operations for timely and accurate payments. Develop and implement strategies to improve receivables management and reduce delinquencies. Collaborate with cross-functional teams to resolve customer complaints and issues. Analyze and report on receivables performance metrics to senior management. Ensure compliance with regulatory requirements and internal policies. Maintain accurate records and reports of receivables transactions. Job Requirements Strong knowledge of BFSI industry trends and regulations. Experience in managing assets, inclusive banking, SBL, mortgages, or receivables. Excellent communication and interpersonal skills. Ability to work in a fast-paced environment and meet deadlines. Strong analytical and problem-solving skills. Proficiency in Microsoft Office and other relevant software applications. Location: Mayiladuthurai,Chidambaram,Cuddalore,Tittakudi

We are looking for a highly skilled and experienced Branch Receivable Officer to join our team at Equitas Small Finance Bank. The ideal candidate will have 1-4 years of experience in the BFSI industry, preferably with a background in Assets, Inclusive Banking, SBL, Mortgages, or Receivables. Roles and Responsibility Manage and oversee branch receivables operations for timely and accurate payments. Develop and implement strategies to improve receivables management and reduce delinquencies. Collaborate with cross-functional teams to resolve customer complaints and issues. Analyze and report on receivables performance metrics to senior management. Ensure compliance with regulatory requirements and internal policies. Maintain accurate records and reports of receivables transactions. Job Requirements Strong knowledge of BFSI industry trends and regulations. Experience in managing assets, inclusive banking, SBL, mortgages, or receivables. Excellent communication and interpersonal skills. Ability to work in a fast-paced environment and meet deadlines. Strong analytical and problem-solving skills. Proficiency in Microsoft Office and other relevant software applications.

Job Specs : We are seeking a highly skilled and motivated ASIC SOC & GLS Verification Engineer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Verification IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Remote, Work From Anywhere Work Expertise: 7 Years 10 Years Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering. Expertise in ASIC SOC verification. Expertise in UVM, System Verilog and constrained random testing. Expertise in Gate Level Simulation tools (GLS) or verification related to display port or memory controller Expertise in testbench architecture and SOC-level verification strategies. Knowledge of scripting languages (Python, Perl, TCL) for automation. Good understanding of SoC architecture, including CPU subsystems, memory hierarchy, and peripherals. Preferred immediate hires only Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Summary: We are seeking a highly skilled and motivated Senior Design Verification Engineer to join our growing team. You will be responsible for planning and executing the verification strategy for complex ASIC/SoC designs. You will work closely with design, architecture, and software teams to ensure functional correctness of RTL through rigorous verification methodologies. Key Responsibilities: Develop and execute comprehensive test plans based on design specifications and architectural documents. Build and maintain constrained-random verification environments using SystemVerilog UVM . Write testbenches, test cases , and functional coverage to ensure design quality. Debug RTL and testbench issues using industry-standard tools (e.g., VCS, ModelSim, Verdi, DVE). Develop and track coverage metrics (code, functional, and assertion coverage). Contribute to the automation of the verification process (e.g., regression tools, continuous integration). Participate in design and verification reviews and provide technical guidance to junior engineers. Required Skills & Experience: Bachelors or Masters degree in Electronics, Electrical Engineering, or Computer Engineering . 3Years to 25 Years of experience in RTL verification of complex digital designs. Proficiency in SystemVerilog , UVM methodology , assertions, and functional coverage. Strong debugging and problem-solving skills. Experience with simulation tools (Synopsys VCS, Cadence Incisive/Xcelium, ModelSim, etc.). Solid understanding of SoC architecture, AMBA protocols (AXI, AHB, APB). Hands-on experience with scripting (Python, Perl, Tcl, or Shell). Familiarity with version control systems (e.g., Git, Perforce). Preferred Qualifications: Exposure to PCIe, Ethernet, USB, DDR , Jtag or other high-speed interfaces. Why Join Us: Work on cutting-edge technology with top-tier semiconductor clients. Opportunity to lead verification activities and mentor junior team members. Competitive compensation and flexible work culture.

Sr Staff Engineer Design Verification [ Location: NOIDA] Job Description We are seeking a diligent Verification leader to join our team at leading semiconductor company. The Verification engineer will be responsible for performing various verification tasks including Test Plan creation, Testcase creation, Coverage closure, Requirements traceability and Gate Level Simulation. They will also review system requirements and track quality assurance metrics. Ultimately, the role of the Verification Engineer is to ensure that our products, applications, and systems work correctly, safely & securely. Responsibilities: Drive Verification R&D team driving technical execution and best in class methodologies used in the design of advanced microcontrollers andmicroprocessors. Work closely with system architects to understand high level specifications to be able to verify them. Work with various EDA vendors to deploy next generation tools Build strong collaboration with other R&D teams such as RTL, DFT, digital IP, PD, Design Enablement, Emulation, and Validation to achieve project milestones Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence overall design improvements and verification methodologies Responsible for developing detailed Technical SoC verification execution plans, progress reports and tracking milestones, managing technical risks, and providing mitigations to meet schedule quality and costs commitments. Communicate across technical teas as well as provide executive level presentations Complete ownership for SoC verification quality sign-offs ensuring all deliverables for team hand-offs. Drive best in class verification methodologies collaborating with global internal and external SME’s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI Qualifications Degree in Electrical/Electronic Engineering, Computer Engineering or Computer Science At least 12 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits. Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC. Experience in Microcontroller and Microprocessor architecture & Interconnect Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR5/5x) and memory controllers. Advanced knowledge of Verilog, System Verilog, C/C++, Shell. Good knowledge in scripting like Perl, TCL or Python is a plus High proficiency in Metric Driven Verification concepts, functional and code coverage. Expertise in directed and constrained random methodologies. Good knowledge of formal verification methodologies and assertions. Experience with debugging of designs pre- and post-silicon, in simulation and on the bench. Excellent written and verbal communication skill. Must have worked on complex, multi-core SoC’s with extensive interconnects and a large range of peripherals. Fair domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must. Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, UCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems.

Job Description. Arm’s CE-Systems DFT team implements DFT for test chips and hard macros to prove out Arm soft IP power, performance, area, and functionality within the context of an SoC using the latest DFT and process technologies. The DFT team works closely with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE.. Responsibilities. Architect, implement, and validate innovative DFT techniques on test chips as well as hard macros. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.. Required Skills And Experience. This role is for a Senior Principal DFT Engineer with 15+ years of experience in Design for Test. Experience coding Verilog RTL, TCL and/or Perl. Proficient in Unix/Linux environments. Core DFT skills considered for this position should include some of the following Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics. Bachelors or Master’s degree or equivalent experience in Electronic Engineering, Computer Engineering, or a related field. “Nice To Have” Skills and Experience. Familiarity with IEEE 1149, 1500, 1687, 1838. Synthesis & Static Timing Analysis. Familiarity with SoC style architectures including multi-clock domain and low power design practices.. Validated understanding of Siemens DFT tools. Familiarity with Arm IP like the following Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug. Experience with 2.5D and 3D test. Ability to work both collaboratively on a team and independently. Hard-working and excellent time management skills with an ability to multi-task. An upbeat demeanor to working on exciting projects on the cutting edge of technology. Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools. In Return. We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding!. Partner and customer focus. Teamwork and communication. Creativity and innovation. Team and personal development. Impact and influence. Deliver on your promises. Accommodations at Arm. At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.. Hybrid Working at Arm. Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.. Equal Opportunities at Arm. Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.. Show more Show less

In your new role you will:. Manage a Digital Verification Team working in R&D projects in a complex technical area. Resource pipeline balancing, allocate projects and co-ordinate the team. Building up and developing competencies and methodologies for IP/SoC Verification. Be the technical interface to internal development groups, project management and external development partners. Drive innovation in the form of new advancements (state-of-the-art verification methods, tool integration and flow automation). Envisage, implement, institutionalize and maintain the verification methods and infrastructure (e-g. automation to improve quality/efficiency in terms of cost and time). Accountable together with the PJM & CoC Head in meeting Quality, Cost, Deliverables, Represent your group in cross site methodology exchange. You are best equipped for this task if you have:. A degree in Electrical Engineering, Computer Science or similar technical field. At least 10 years of experience in the semiconductor industry inrelevant R&D departments and people management experience is must. Experience in Product Development, Digital Verification or Digital Design. Profound and proven problem-solving capabilities as well as strong communication skills to manage global and multi-cultural stakeholders and networks successfully. Good knowledge in your own technical area but a focus on management and coordination role. Excellent presentation skills which enable you to master the alignment across internal and external contacts in a multi-cultural environment. Highly motivated with ability to prioritize and perform under pressure. Proven ability to achieve results in a very dynamic and multi-site environment. Strong analytical and communication skills. #WeAreIn for driving decarbonization and digitalization, As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener, Are you in?. We are on a journey to create the best Infineon for everyone, This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicants experience and skills, Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process, Click here for more information about Diversity & Inclusion at Infineon, Show more Show less

Waymo is an autonomous driving technology company with the mission to be the most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo One, a fully autonomous ride-hailing service, and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over one million rider-only trips, enabled by its experience autonomously driving tens of millions of miles on public roads and tens of billions in simulation across 13+ U.S. states.. Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle's software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world's highest performance automotive compute platforms.. In this hybrid role, you will report to an ASIC Design Manager.. You Will. Manage a new team of engineers developing advanced silicon for our self-driving cars. Grow the team by hiring top talent at our new site in Bangalore. Hands on technical leadership and contributions to architecture, design, and verification of IP blocks. Work and coordinate cross-functionally with our U.S. and Taiwan silicon and partner teams. Develop methodologies and best practices to ensure on-time, high performance, and high-quality silicon. You Have. 6+ years experience managing ASIC or SoC development teams. Strong technical experience with the full digital design and verification cycle -from spec through bring-up. 5+ years of industry experience with high performance digital design in Verilog/SystemVerilog. Experience prioritizing resources across multiple projects on tight timelines. We Prefer. Industry experience with constrained random verification and UVM. Fluency in at least one high level programming language such as Python, C++. Experience with performance and power validation, and formal verification. Experience with prototyping systems on FPGA platforms or emulators. Experience with automotive silicon and standards. The expected base salary range for this full-time position is listed below. Actual starting pay will be based on job-related factors, including exact work location, experience, relevant training and education, and skill level. Waymo employees are also eligible to participate in Waymo’s discretionary annual bonus program, equity incentive plan, and generous Company benefits program, subject to eligibility requirements.. Salary Range. ?8,400,000—?10,200,000 INR. Show more Show less

Minimum qualifications:. Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.. 15 years of experience in ASIC RTL design.. Experience with RTL design using Verilog/System Verilog and microarchitecture.. Experience with ARM-based SoCs, interconnects and ASIC methodology.. Preferred qualifications:. Master’s degree in Electrical Engineering or Computer Engineering.. Experience driving multi-generational roadmap for IP development.. Experience leading interconnect IP design team for low power SoCs.. About The Job. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.. Responsibilities. Lead a team of people to deliver fabric interconnect design.. Develop and refine RTL design to aim power, performance, area, and timing goals.. Define details such as interface protocol, block diagram, data flow, pipelines, etc.. Oversee RTL development, debug functional/performance simulations.. Communicate and work with multi-disciplined and multi-site teams.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

Minimum qualifications:. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.. 3 years of experience with verification methodologies and languages such as UVM and SystemVerilog.. Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog at Subsystem or Full chip level.. Experience in performance and latency architecture for an Anycast Redirector Maglev (ARM) based SOC.. Experience in mobile SOC performance model development, performance analysis, and workload characterization.. Experience performance measurement and debugging in an emulation environment.. Preferred qualifications:. Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.. Experience in low-power design verification.. Experience in microarchitecture innovation.. Knowledge of CPU, GPU benchmark characterization.. Knowledge in system software components, such as Linux, drivers, and runtime.. Knowledge of performance analysis tools.. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.. Responsibilities. Develop simulators and architectural models of Google's Tensor System on a Chip (SOC).. Collaborate with system architects, SoC and CPU/GPU/TPU architects/designers, and software and application experts to understand current and future requirements.. Participate in architectural and design evaluation of Tensor SOC features studies.. Perform pre-silicon performance simulation and correlate with pre and post-silicon measurements.. Communicate analysis results qualitatively and quantitatively.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

Minimum qualifications:. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.. 5 years of experience in architecture, hardware, digital design, and software co-design. 3 years of experience in Verilog/SystemVerilog.. Experience in computer architecture and digital design or Internet Protocol (IP) integration (e.g., Peripheral Component Interconnect Express (PCIe), Double Data Rate (DDR) memory).. Preferred qualifications:. Master's degree in Electrical Engineering, Computer Science, or a related field.. 4 years of experience working on Field Programmable Gate Array (FPGA) platforms or Emulation platforms with Internet Protocols (IPs) (e.g., Peripheral Component Interconnect Express (PCIe), Double Data Rate (DDR) memory, Gigabit Ethernet, Flash).. Experience in developing architectures for Machine Learning Accelerators.. Experience in writing or debugging Verilog/Register-Transfer Level (RTL) code for ASIC/FPGA designs, waveform debug skills with knowledge of chip design flows.. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.. In this role, you will integrate hardware and software stacks and operate them on emulation platforms for pre-silicon validation of our Google Cloud Tensor Processing Unit (TPU) projects. You will create software-based custom test cases, workloads, test generators, infrastructure, analysis tools, and debugging tools. You will be responsible for silicon bring-up, validation, characterization and qualification, and sustaining programs and their quality. You will help ensure our fleet runs at maximum efficiency, and help debug and root when causing issues. You will collaborate with Product Firmware, System Software and Application-Specific Integrated Circuit (ASIC) Design in the development of tools, validation firmware, functional and performance tests, and testing infrastructure for our platforms and Google Cloud data center systems.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.. We prioritize security, efficiency, and reliability across everything we do from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.. Responsibilities. Enable bring-up of chip features through firmware and driver stack. Integrate and validate hardware and software designs in pre-silicon.. Architect and design Application-Specific Integrated Circuit (ASIC) models for Emulation/Field Programmable Gate Array (FPGA) Prototypes. Design Register-Transfer Level (RTL) transformations to optimize mapping to Emulation/FPGA platforms and design solutions to improve Internet Protocol (IP) modeling.. Design solutions to improve hardware modeling accuracy and scale to various system configurations and enable serving of ASIC models for software and validation teams.. Bringup chip features on software reference models and hardware prototypes (e.g., Emulation/FPGA) and drive debug discussions with design/design validation/physical design/software/architecture teams and help root-cause failures.. Develop the integration plan with software and system partners, coordinate hardware and software delivery and benchmark performance.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING. We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.. AMD together we advance_. PMTS SILICON DESIGN ENGINEER. As a SerDes Verification Architect, you will be responsible for the verification and validation of high-speed SerDes interfaces, including testing data integrity, performance, and protocol compliance. You will work closely with hardware and design teams to ensure that SerDes designs meet the required specifications, operating parameters, and quality standards.. Key Responsibilities. Verification of SerDes Designs: Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements.. Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL).. Simulation and Debugging: Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks.. Performance Evaluation: Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics.. Protocol Compliance Testing: Verify adherence to relevant SerDes protocols such as UCIe, PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols.. Automated Testing: Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations.. Collaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes.. Documentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing.. Verification methodology: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies.. Experience:. 16+ years of experience in SerDes verification or high-speed communication verification.. Strong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools.. Knowledge of high-speed serial protocols such as UCIe, PCIe, Ethernet, USB, DDR, or custom protocols.. Experience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams.. Skills:. Solid understanding of SerDes architectures, link training, and equalization.. Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance).. Familiarity with hardware description languages (HDL) like VHDL or Verilog.. Strong analytical, problem-solving, and communication skills.. Experience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification.. Understanding of UCIe protocol and its role in chiplet-to-chiplet communication.. Preferred Skills. Experience with Python, Perl, or similar scripting languages for automation.. Exposure to high-speed memory interface design and verification, including DDR controller IP verification.. Functional coverage, assertions knowledge in SV/UVM.. Ability to work in a fast-paced environment and manage multiple verification tasks.. Strong team player with good interpersonal and communication skills.. Benefits offered are described: AMD benefits at a glance.. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.. Show more Show less

Date 29 May 2025 Location: Bangalore, KA, IN Company Alstom At Alstom, we understand transport networks and what moves people. From high-speed trains, metros, monorails, and trams, to turnkey systems, services, infrastructure, signalling and digital mobility, we offer our diverse customers the broadest portfolio in the industry. Every day, 80,000 colleagues lead the way to greener and smarter mobility worldwide, connecting cities as we reduce carbon and replace cars. Could you be the full-time Studio Engineer in our Advanced & Creative Design Global (A&CD) team were looking for Studio Engineer is responsible to build a crucial relationship between A&CD Design Vertical and Engineering counterparts for better Integration of Exterior and Interior Components, Engineering Parameters, while also be equally involved for Data Preparation work on Visualization Activities. Organization VerticalAdvanced & Creative Design Global (A&CD) Reports directly toDigital Design Team Leader - A&CD Asia Studio collaborationDigital Design, Mobility Design, Visualization Design and CMF Design Teams InternalA&CD Team, RSC engineering organization (TD, COE, TSS, R&D), Procurement, Intellectual properties Organization. ExternalDesign Organizations, Design Agencies and Data Management Partners. Eligibility & Work Experience Bachelors or masters program in Mechanical Engineering, Automobile Engineering or related streams With a minimum professional experience of 2 years or more in handling Studio Engineering Responsibilities. Drive and Passion for sustainable future / mobility ecosystem and related solutions. Excellent level / Mastery on Digital Design tools (Alias, Catia, VRED). Workload Management Experience with strong skills in Microsoft Office Tools (PowerPoint, Excel) + Data Presentation Techniques. Professional experience of Production Design, DFQ, DFM, DPQ Processes. Good Interpersonal and Communication skills with internal and external stakeholders. Understanding of Mobility Design and Production Processes. Knowledge of industrial environment and associated technical and economic issues. Flexibility, ability to work on multiple projects with varied workscope. Experience of ensuring design deliverables that meet required quality standards. A portfolio / work samples demonstrating Studio Engineering Experience is essential to apply for this position. Ability to work independently and as part of a team. DesirablePrior Experience in Automobile, Mobility or Rail / Transportation Industry. Role & Responsibility Be the Key link between Design Vertical and Engineering counterparts for better Integration of Exterior and Interior Components. Build strong understanding of Engineering Parameters, Regulatory Specifications and Global Standards related to Rail Industry. Support A&CD -Mobility Design Team, Visualization Design Team and CMF Design Team in delivering Advanced Creative Design (A&CD) objectives. Data Preparation - for Visualization Design Team with regards to improved workflow from Design, Engineering and Final Visualization Deliveries / Renderings. Create Studio Engineering solutions that are compliant with applicable technical, contractual, legal and standards requirements. Timely delivery of A&CD deliverables to achieve Design Reviews / Project milestones. Ensure the consistency of the data deliveries for Internal & External Schedules. Improve relations and information exchanges with related projects teams. Promote the Importance of A&CD Design Vertical to all stakeholders inside and outside of the organization. Be able to organize and plan workload according to Tenders and Projects in progress. Manage workhours and timelines in accordance with the project budget. Ensuring the archival of completed projects and managing ongoing project / resource files on secured Database. Collaborate with the team to develop design proposals and ensure timely and efficient delivery. Stay up-to-date and introduce newer AI tools and integration techniques and keep innovating design approaches and methods. Fluent English communication is essential for the Role. Contribute to an engaging, collaborative and a thriving studio culture. Competencies (Proficiency progressionfrom A being the lowest to E being the highest level.) Developing Oneself - D Communication -D Drive for Results -E Building Partnerships -E Developing Others - B Initiative -D Team Leadership - B Strategic Outlook -E Technical skills (Proficiency progressionfrom A being the lowest to E being the highest level.) Determining and Managing Stakeholder -E Modelling and Simulation-E Concept Generation -D Systems Integration and Verification -E Integration of Design Deliveries -E You dont need to be a train enthusiast to thrive with us. We guarantee that when you step onto one of our trains with your friends or family, youll be proud. If youre up for the challenge, wed love to hear from you! As a global business, were an equal-opportunity employer that celebrates diversity across the 63 countries we operate in. Were committed to creating an inclusive workplace for everyone .

Roles and Responsibilities Design verification using System Verilog, UVM, and SV/UVM methodologies. Experience with PrimeSim XA, WREAL, RNM, Verilog-A, and MIPI protocols. Proficiency in PCIe and USB 3 interfaces. Strong understanding of digital logic design principles and SoC architecture. Excellent problem-solving skills with attention to detail.

Key Skills: Architect, System Verilog, Verilog, PCI Roles and Responsibilities: Architecture Design: Develop and optimize PCIe architectures for high-performance SoC designs, including switches, interconnects, and communication protocols. Protocol Expertise: Design and implement PCIe solutions that support various communication protocols such as PCIe, CXL, and AMBA/AXI. System Understanding: Contribute to overall SoC design by ensuring seamless communication between various IP blocks and subsystems. Performance Analysis: Conduct detailed performance analysis and benchmarking of PCIe designs to identify bottlenecks and improvement areas. Collaboration: Work closely with hardware, software, and verification teams to meet system and performance requirements. Troubleshooting: Identify and resolve complex PCIe design and simulation issues. Research and Development: Stay updated on PCIe specifications; contribute to new standards, methodologies, and tools. Engage in research projects to explore new PCIe programs and protocols. Skills Required: Primary Skills: Proficient in PCIe design and optimization techniques Strong understanding of digital design principles and SoC architecture Experience with Verilog and SystemVerilog Knowledge of RTL simulation tools and verification environments (e.g., Cadence, Synopsys, UVM) Expertise in PCIe, CXL, and AMBA/AXI protocols Soft Skills: Excellent problem-solving and analytical abilities Strong communication and collaboration skills Ability to work independently and within a team High attention to detail and quality focus Passion for research and innovation Preferred Skills: Experience with PCIe Gen-4/5/6 protocols Knowledge of ASIC design flows Familiarity with scripting languages (e.g., Python, Perl) Experience with version control systems (e.g., DesignSync, Git) Background in PCIe architecture, SerDes concepts, and low-power design Experience with synthesis tools (DC/DC-NXT, Fusion Compiler) Understanding of synthesis constraints and timing (STA) Experience with Spyglass (Lint, DFT, PM, CLK/RST, CDC/RDC) Formal verification using tools like Formality or Conformal LEC Publication history in technical journals or IEEE conferences is a plus Education: Bachelor's or Master's degree in Engineering or a related field

Key Skills: Asic Verification, System Verilog, Verilog, PCI, Ethernet Roles and Responsibilities: Verify a block or a functional feature and lead it to closure. Write and architect scalable and reusable testbenches from scratch, using the framework of the verification methodology. Create test cases, functional coverage models, and bring the verification to closure. Think differently and out-of-the-box to stress the DUT and verify it in an efficient way. Be involved in documenting the verification strategy including test plans, verification micro-architecture, coverage objects, etc. Participate in and own verification strategic decisions that will help in the long run. Skills Required: Deep understanding of the full ASIC cycle, from conceptualization to TapeOut. Strong experience writing and debugging test benches. Proficiency in constrained random verification methodologies like UVM, VMM, or OVM. Strong knowledge of SystemVerilog. Solid command over object-oriented programming (OOP) principles. Open to learning and applying innovative verification methodologies and strategies. Motivated, self-driven, and able to work independently. Education: Bachelor's or BE degree in Engineering.

Design Verification Engineer (3-8 years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 3-8 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment

We are looking for a highly skilled and experienced Legal Officer to join our team at Equitas Small Finance Bank. Roles and Responsibility Manage and oversee legal matters related to mortgages and other financial products. Draft and review contracts, agreements, and other legal documents. Provide legal advice and guidance on various banking-related matters. Conduct legal research and analysis to support business decisions. Collaborate with cross-functional teams to ensure compliance with regulatory requirements. Develop and implement strategies to mitigate legal risks and minimize losses. Job Requirements Strong knowledge of legal principles and practices applicable to the BFSI industry. Experience working with SBL or similar institutions is preferred. Excellent analytical, communication, and problem-solving skills. Ability to work independently and as part of a team. Strong attention to detail and organizational skills. Familiarity with mortgage laws and regulations is desirable.

We are looking for a skilled Regional Receivables Manager to join our team at Equitas Small Finance Bank. Roles and Responsibility Manage and oversee regional receivables operations to ensure timely recovery of outstanding amounts. Develop and implement strategies to improve collection efficiency and reduce delinquencies. Collaborate with internal stakeholders to resolve customer complaints and disputes. Analyze and report on key performance indicators to identify areas for improvement. Ensure compliance with regulatory requirements and company policies. Lead and motivate a team of collection professionals to achieve targets. Job Requirements Strong knowledge of Inclusive Banking, SBL, and Mortgages concepts. Excellent communication and interpersonal skills. Ability to work in a fast-paced environment and meet deadlines. Strong analytical and problem-solving skills. Experience in managing teams and leading by example. Familiarity with financial software and systems is desirable.

We are looking for a highly skilled and experienced Relationship Manager to join our team at Equitas Small Finance Bank. Roles and Responsibility Manage and maintain strong relationships with existing clients to increase business growth. Identify new business opportunities and develop strategies to expand the client base. Provide excellent customer service and support to ensure high levels of client satisfaction. Collaborate with internal teams to achieve sales targets and improve overall performance. Develop and implement effective relationship management plans to drive business results. Analyze market trends and competitor activity to stay ahead in the industry. Job Requirements Strong knowledge of Assets, Inclusive Banking, SBL, Mortgages, Standalone Merchant OD, and Relationship Management. Excellent communication and interpersonal skills are required to build strong relationships with clients and colleagues. Ability to work in a fast-paced environment and meet sales targets. Strong analytical and problem-solving skills to analyze market trends and competitor activity. Experience working in the BFSI industry with a focus on relationship management and business growth. Ability to work collaboratively as part of a team to achieve business objectives.

raja.a@honeybeetechsolutions.com resume to SoC NoC Verification Lead with 10+ years of experience, the role typically expands to include leadership, strategic planning, and advanced debugging. This role involves developing test plans, writing verification code, debugging issues, and collaborating with design teams to validate complex interconnect systems. Key Responsibilities Lead verification projects for complex SoC and NoC architectures. Develop advanced verification methodologies using SystemVerilog/UVM. Guide teams in debugging and resolving intricate design issues. Optimize performance, power, and coverage metrics. Work with high-speed interconnect protocols (AXI, CHI, PCIe, Ethernet, CXL, UCIe). Manage testbench architecture and automation frameworks.

raja.a@honeybeetechsolutions.com resume to SoC NoC Verification Lead with 10+ years of experience, the role typically expands to include leadership, strategic planning, and advanced debugging. This role involves developing test plans, writing verification code, debugging issues, and collaborating with design teams to validate complex interconnect systems. Key Responsibilities Lead verification projects for complex SoC and NoC architectures. Develop advanced verification methodologies using SystemVerilog/UVM. Guide teams in debugging and resolving intricate design issues. Optimize performance, power, and coverage metrics. Work with high-speed interconnect protocols (AXI, CHI, PCIe, Ethernet, CXL, UCIe). Manage testbench architecture and automation frameworks.

Lead and manage a team of verification engineers, providing guidance, mentorship, and performance feedback. (20%) Ensure the definition and implementation of test and verification plans. (20%) Collaborate with design, architecture, and other cross-functional teams to ensure alignment on project goals and requirements.(10%) Monitor and analyse coverage reports to ensure thorough verification. (10%) Identify and resolve verification issues and bugs, ensuring timely project delivery. (10%) Continuously improve verification processes, methodologies, and tools. (10%) Manage project schedules, resources, and deliverables to meet deadlines. (10%) Oversee the writing and debugging of System Verilog assertion.(10%) Minimum Qualifications: 8+ years of relevant experience in SOC verification. bachelors or masters degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in RTL design verification and team management. Proficiency in System Verilog and assertion-based verification. Strong understanding of test and verification plan definition and implementation. Experience with coverage-driven verification and coverage report generation. Familiarity with industry-standard verification tools (eg, VCS, Questa Sim). Experience with SoC design verification. Knowledge of HVL methodology (UVM/OVM) with the most recent experience in UVM. Experience with formal verification. Experience taping out large SoC systems with embedded processor cores. Hands-on verification experience of Bus Fabric, NOC, AMBA-AHB/AXI based bus architecture in a UVM environment. Knowledge of Low Power Verification. Excellent problem-solving skills and attention to detail. Desired Qualifications Experience in wireless SoC design and verification. Knowledge of scripting languages (eg, TCL, Python, Perl) for automation. Familiarity with version control systems (eg, Git).