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Senior Logic Design Engineer

Senior Logic Design Engineer

IBM

3 - 5 years

4 - 8 Lacs

Bengaluru

Posted:3 days ago| Platform:

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Skills Required

rtl design protocols cache rtl dft physical design c++ atpg digital design vhdl java fpga rtl coding perl system verilog xilinx ise asic sta asic verification c uvm verilog asic design fpga design vlsi logic design

Work Mode

Work from Office

Job Type

Full Time

Job Description

Design and development of processor L2 , L3, Non cacheable units and LLC (Last Level Cache) for high-performance IBM Systems.- Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements.- Develop the features, present the proposed architecture in theHigh level design discussions- Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature- Signoff the Pre-silicon Design that meets all the functional, area and timing goals- Participate in silicon bring-up and validation of the hardware- Lead a team of engineers, guide and mentor team members,represent as Logic Design Lead in global forums.- Estimate the overall effort to develop the feature.- Estimate silicon area and wire usage for the feature.. Required education Master's Degree Preferred education High School Diploma/GED Required technical and professional expertise

8 to 15 years of relevant experience
- At least 1 generation of processor L2 cache or LLC designdelivery leadership.- Expertise in cache coherence protocols for symmetricmultiprocessors (SMP), covering both chip SMP and multi-socketSMP.- Experience with NuCA / NuMA (Non-uniform Cache / Memoryarchitecture) architectures and implementations.- Working knowledge of memory consistency, store ordering,weakly and strongly ordered memory.- Experience in logical and physical design of caches includingdirectories (tags, set associative memories), data SRAM, designfor low latency, multiple parallel finite state machine design,

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Senior Logic Design Engineer