Notice Period : Immediate Joiner Mode : Onsite work This Job emphasizes the engineer's focus on testing modem technologies, specifically for 5G and LTE, and their responsibility for maintaining test content and stability. Required Skills: Modem Technologies: 2-4 years of experience in testing 5G and LTE technologies Testing Concepts: Strong understanding of sanity, regression, functional, and stress testing Test Plan Development: Ability to design, develop, and execute test plans and cases Bug Tracking: Experience in identifying, documenting, and tracking bugs and issues Collaboration: Strong collaboration skills with development teams to understand requirements Programming Languages: Knowledge of programming languages such as Java, Python, or C Qualifications: Bachelor's Degree in Electrical Engineering or related field Strong problem-solving and analytical skills Excellent communication and teamwork skills.

Notice Period : 0-15 Days We are seeking a Software Developer - Testing with 1-3 years of experience to focus on TBS regression testing. The role involves executing regression tests with specialized tools, documenting system-level defects, and using a bug tracking system for reporting. The candidate will also work closely with developers to support and validate fixes. Strong knowledge of 5G and LTE, along with solid debugging and testing skills, is essential. Familiarity with Qualcomm tools and Python scripting is a plus. Key Responsibilities: 1. Execute regression tests using specialized tools for TBS regression testing. 2. Document system-level defects and report them using a bug tracking system. 3. Collaborate with developers to support and validate bug fixes. 4. Apply 5G and LTE technology knowledge for effective debugging and testing. 5. Utilize Qualcomm tools where applicable. 6. Implement basic Python scripting for automation purposes. Requirements: 1. 1-3 years of experience in testing and debugging. 2. Strong knowledge of 5G and LTE technologies. 3. Good debugging and testing skills. 4. Familiarity with bug tracking systems. 5. Basic understanding of Python scripting for test automation. 6. Experience with Qualcomm tools is an advantage.

Company : Silcosys Solutions Pvt. Ltd. Experience: 3 -5 Years Location : Hyderabad Notice Period : 0- 15 Days Job Description: We are looking for an experienced Software Developer with 3-5 years of expertise in C++ or Core Java and 2-3 years of experience in Android Telephony, RIL, or Modem. The role requires a strong background in object-oriented design, embedded systems, and Linux OS skills. The candidate will be responsible for designing, implementing, and debugging telephony-related software solutions in an embedded environment. Key Responsibilities: 1. Develop and optimize telephony-related software using C++ or Core Java. 2. Work on Android Telephony, RIL, or Modem modules. 3. Implement object-oriented design principles in software development. 4. Debug and troubleshoot telephony and modem-related issues. 5. Collaborate with cross-functional teams to integrate software solutions. Requirements: 1. 3-5 years of experience in C++ or Core Java programming. 2. 2-3 years of experience in Android Telephony, RIL, or Modem. 3. Strong understanding of Object-Oriented Design and implementation. 4. Good experience in Linux/Embedded environments. 5. Strong analytical and debugging skills. 6. Experience in telecommunication systems is a plus. Share your resumes at

Notice Period : Immediate Joiner Mode : Onsite work We are seeking an experienced Optimization Engineer with a strong background in data structures, algorithms, and performance optimization. If you're passionate about improving software performance and have expertise in C/C++ on x86 platforms, we'd love to hear from you! Preferred Experience: Proficient in data structures and algorithms with a proven ability to identify and resolve performance bottlenecks. Strong expertise in software development using C/C++, including debugging in multicore systems. Experience in performance analysis for data centers, HPC (High Performance Computing), and MPI (Message Passing Interface) applications. Hands-on experience with x86 architecture optimizations or similar platforms. In-depth understanding of Cache sub-systems, Instruction Set Architecture (ISA), and CPU pipeline. Bonus Skills: Familiarity with Intel MKL libraries, Linear Algebra, Core Math, and x86 assembly programming. Knowledge of CPU Profiling tools. Qualifications: Bachelor's or Master's degree in Computer Engineering or a related field.

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: Are you an Analog Design Engineer with hands-on experience designing components like Bandgap references, High-Speed IO circuits, Low Dropout Regulators (LDOs), and Phase-Locked Loops (PLLs)? If you have a minimum of 2 years in the semiconductor industry, this role offers exciting challenges and opportunities to contribute to groundbreaking projects. Responsibilities: 1. Collaborate with multidisciplinary teams to ensure seamless integration of analog blocks into semiconductor products. 2. Design, simulate, and validate analog circuits, focusing on PLLs, LDOs, Bandgap references, and High-Speed IO circuits. 3. Perform detailed analysis, optimization, and troubleshooting to meet performance, efficiency, and reliability targets. 4. Stay informed about emerging trends and advancements in analog design and apply innovative solutions. 5. Develop and maintain comprehensive documentation to support design processes and product development. Requirements: 1. A Bachelors degree or higher in Electrical Engineering or a related field. 2. At least 2 years of experience in analog circuit design within the semiconductor industry. 3. Expertise in designing analog components such as Bandgap references, PLLs, LDOs, and High-Speed IO circuits. 4. Proficiency with industry-standard Electronic Design Automation (EDA) tools for design and simulation. 5. Strong analytical, troubleshooting, and problem-solving skills. 6. A solid understanding of semiconductor fabrication processes and technologies. 7. Excellent communication and collaboration skills. Preferred Qualifications: 1. Experience in mixed-signal circuit design and low-power techniques. 2. Familiarity with high-speed data communication interfaces. 3. Contributions to published research or patents in analog design. 4. A strong understanding of innovative methods to optimize performance and efficiency. Why Join Us? Work on industry-leading projects that make a global impact. Collaborate with a team of experts in a supportive and innovative work environment. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of analog design!

As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, while employing state-of-the-art techniques to optimize coverage, cost, and performance. Responsibilities: 1. Develop and implement DFT architectures and strategies for complex SoC designs. 2. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). 3. Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure high fault coverage. 4. Collaborate with RTL designers to ensure seamless integration of DFT features into the design. 5. Debug and resolve test-related issues in simulation, silicon validation, and production. 6. Work closely with the physical design team to implement scan and clock constraints for timing closure. 7. Optimize test time, power, and cost without compromising coverage and quality. Participate in silicon bring-up and post-silicon validation activities. 8. Generate and maintain DFT documentation, including test plans, methodologies, and results. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 210 years of experience in DFT for VLSI designs. Strong knowledge of DFT methodologies, including scan insertion, BIST, and ATPG. 3. Experience with EDA tools such as Synopsys Tetramax/DFTMax, Cadence Modus, or Mentor Tessent. Proficiency in 4. Verilog/SystemVerilog and scripting languages (Python, TCL, Perl). 5. Solid understanding of STA concepts and constraints related to DFT. 6. Experience in debugging silicon and ATE test patterns. Knowledge of test standards like IEEE 1149.x (JTAG) and 1500. 7. Excellent problem-solving skills and ability to work in a collaborative environment. Preferred Qualifications: 1. Experience with low-power DFT techniques. 2. Familiarity with fault diagnosis and yield improvement methodologies. 3. Exposure to advanced nodes (7nm, 5nm, or below) and FinFET technologies. 4. Knowledge of machine learning or AI techniques for test optimization. 5. Hands-on experience with multi-core and hierarchical DFT architectures.

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL design, verification, and DFT teams to ensure seamless integration and sign-off. 4. Debug and resolve issues related to timing, signal integrity, and power. 5. Drive closure of physical verification issues such as DRC, LVS, and ERC. 6. Implement low-power design techniques, including power gating, multi-Vt optimization, and dynamic voltage scaling. 7. Work closely with EDA tool vendors to improve design flows and methodologies. 8. Generate and maintain comprehensive documentation for physical design flows and guidelines. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 2. 3-10 years of experience in physical design for VLSI systems. 3. Proficiency in physical design tools such as Cadence Innovus, Synopsys ICC2, or Mentor Calibre. 4. Strong knowledge of STA tools like PrimeTime, Tempus, or equivalent. 5. Experience with advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 6. Expertise in low-power design techniques and methodologies. Solid understanding of DRC/LVS and parasitic extraction. 7. Familiarity with scripting languages (Python, TCL, Perl) for flow automation. 8. Excellent problem-solving skills with the ability to debug and resolve complex physical design challenges. 9. Strong communication and collaboration skills to work effectively in cross-functional teams. Preferred Qualifications: 1. Hands-on experience with hierarchical design flows and methodologies. 2. Knowledge of 3D IC and advanced packaging technologies. 3. Familiarity with machine learning or AI applications in physical design optimization. 4. Exposure to hardware security aspects in physical design.

As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: 1. Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. 2. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. 3. Perform design optimizations for area, power, and performance. 4. Conduct design reviews and ensure compliance with coding standards and best practices. 5. Work closely with verification teams to develop test plans and ensure 100% functional coverage. 6. Debug and resolve design and integration issues during simulation and post-silicon validation. 7. Participate in timing analysis and closure in collaboration with the physical design team. 8. Document design specifications, test cases, and user guides for IP and SoC designs. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 210 years of experience in RTL design and implementation for VLSI systems. 3. Strong expertise in Verilog, SystemVerilog, and RTL design methodologies. 4. Solid understanding of digital design concepts such as pipelining, clock domain crossing, and low-power design techniques. 5. Experience with EDA tools like Synopsys Design Compiler, Cadence Genus, or equivalent. Proficiency in scripting languages (Python, Perl, TCL) for design automation. 6. Familiarity with SoC interfaces and protocols like AXI, AHB, PCIe, USB, or DDR. 7. Experience in static timing analysis (STA) and timing closure workflows. 8. Strong problem-solving skills and the ability to debug complex design issues. 9. Excellent communication and collaboration skills to work effectively in a team environment. Preferred Qualifications: 1. Experience with low-power design and multi-clock domain systems. 2. Knowledge of advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 3. Exposure to formal verification methodologies. Experience in hardware-software co-design and FPGA prototyping. 4. Familiarity with machine learning or AI-based RTL optimizations. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future.

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: As a Design Verification Engineer, you will be responsible for verifying complex SoC designs, working closely with design teams to ensure robust and high-quality products. You will employ advanced verification methodologies and tools to identify and resolve issues, ensuring that our SoC designs meet industry standards and customer requirements. Responsibilities: 1. Develop and execute comprehensive test plans to verify the functionality of SoC designs. 2. Create and maintain verification environments using advanced verification techniques, such as UVM, SystemVerilog, and assertion-based methodologies. 3. Collaborate with design teams to debug and resolve functional issues in RTL and gate-level simulations. 4. Ensure thorough verification coverage by analyzing and improving functional coverage metrics. 5. Perform regression testing to ensure consistent performance and reliability across design iterations. 6. Work closely with architects and designers to understand design specifications and refine verification strategies. 7. Develop reusable verification components and ensure alignment with project timelines and quality standards. 8. Document verification results, generate detailed reports, and present findings to stakeholders. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 3+ years of experience in SoC design verification within the VLSI domain. 3. Expertise in advanced verification methodologies, including UVM and SystemVerilog. 4. Strong understanding of SoC architectures, protocols, and interfaces (e.g., AXI, PCIe, USB, DDR). 5. Proficiency with simulation tools such as VCS, ModelSim, or Questa. 6. Experience with scripting languages (Python, Perl, TCL) for automation. 7. Familiarity with version control systems like Git. Excellent debugging and problem-solving skills, with a focus on delivering high-quality results. 8. Strong communication and collaboration skills to work effectively with cross-functional teams. Preferred Qualifications: 1. Experience with formal verification tools and techniques. 2. Familiarity with low-power verification strategies. Knowledge of hardware-software co-verification. 3. Exposure to machine learning or AI-based approaches in verification. Why Join Us? 1. Work on state-of-the-art SoC designs in a collaborative and innovative environment. 2. Opportunity to be part of a fast-growing company shaping the future of VLSI solutions. 3. Competitive compensation, professional growth opportunities, and a supportive work culture. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future !

About the Role: We are seeking a talented and experienced Analog Layout Engineer to join our team in Bangalore. The ideal candidate will have a strong background in analog layout design and will contribute to the development of cutting-edge semiconductor products. If you are passionate about VLSI design and eager to work in a collaborative, innovation-driven environment, this opportunity is for you! Location: Bangalore Experience: 3 to 10 Years Employment Type: Full-Time Notice Period: 90 Days Key Responsibilities: 1. Design and implementation of custom analog and mixed-signal layouts for circuits such as amplifiers, ADC/DACs, PLLs, and more. 2. Perform layout verification tasks, including DRC, LVS, and parasitic extraction using industry-standard tools. 3. Optimize layout designs for performance, area, and power while ensuring compliance with design rules and process constraints. 4. Collaborate closely with circuit design engineers to interpret specifications and requirements. 5. Participate in design reviews and contribute to the enhancement of layout methodologies. 6. Work on advanced nodes, ensuring high-quality layouts for high-performance, low-power designs. Required Skills and Qualifications: 1. Experience: 3 to 10 years in analog layout design, with expertise in full-custom IC design. 2. Proficiency in layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or equivalent. 3. Strong knowledge of semiconductor process technologies, including FinFETs and advanced nodes (e.g., 7nm, 5nm). 4. Hands-on experience with parasitic-aware design, matching, and signal integrity. 5. Familiarity with EDA tools for verification, such as Calibre or Assura. 6. Excellent analytical and problem-solving skills with attention to detail. 7. Strong communication and interpersonal skills to work effectively in a team environment. What We Offer: 1. Competitive compensation package and benefits. 2. Opportunity to work on innovative and challenging projects. 3. Dynamic and collaborative work environment. 4. Career growth and learning opportunities.