92 Cmos Jobs

Job description Drives and develops testability and manufacturability of integrated circuits from the component feasibility stage through production ramp. Contributes to design, development, and validation of testability circuits, test flows, and methodologies for new products through evaluation, development, and debug of complex test methods. Interfaces with process development, fab, factory, assembly, quality and reliability, and manufacturing groups to enable postsilicon HVM ramp. Evaluates new designs on automatic test equipment (ATE) and works with the design, DFx, and product development teams to debug functionality and performance issues to root cause. Performs ATE device characterization, utilizes that data to define datasheet specifications and performs yield analysis. Collaborates with designers to drive design for test/debug/manufacturing (DFT/DFD/DFM) features enabling efficient production testing of new products. Develops and debugs complex software programs to convert design validation vectors and drive complex test equipment. Creates and tests validation and production test hardware solutions. Tests, validates, modifies, and redesigns circuits to guarantee component margin to specification. Analyzes and evaluates component specification versus performance to ensure optimal match of component requirements with production equipment capability with specific emphasis on yield analysis and bin split capability. Ensures manufacturability over process and product design through thorough analysis of process and spec corners and works with design to resolve yield issues before manufacturing ramp. Drives test time reduction through analysis of fallout data versus test time for various IPs to balance and drive overall product cost optimizations. Analyzes early customer returns with emphasis on driving test hole closure activities. Creates and applies concepts for optimizing component production relative to both quality and cost constraints. Leads and drives manufacturing readiness from fab, assembly, and test factory to support engineering sample and customer sample generation (ES milestones), wafer start planning, product qual execution strategy and capacity analysis, and assembly and test site certification activities. Works with fab, assembly, and test factory partners and planners to support production ramp. May also manage execution of new product introductions in the fab, fab process targeting, product/process optimizations, and participate in factory task forces to bring product perspective and respond to product issues. Optimizes product supply through data analysis of postsilicon binsplit, die level cherry pick (DLCP), and optimize sort/test content and yield downstream through data analysis. Qualifications Candidate should possess a Bachelors or Master degree in Computer/ Electrical/Electronic Engineering with about 10-15 years of experience. Strong Experience of ATE Test Engineering, Technical Program management is a must. Strong knowledge of Sort, Class, Platform manufacturing, good understanding of design, methodologies and tools is desired. A very good team player with good interpersonal, strong planning and excellent communication skills is a must. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group Manufacturing and Product Engineering (MPE) is responsible for test development across product segments, supporting 95% of Intel's revenue. We deliver comprehensive pre-production test suites and component/physical debug capabilities to enable high quality, high volume manufacturing. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Job description Responsibilities may be quite diverse of a technical nature. Need to understand VLSI testing and vectors for ATE . Vectors/Content stabilization, implementation and validation of various DFT features. Understand the system level testing and work towards meeting DPM requirements. Need to work towards automation. Qualifications Pursuing Master Degree in Electronics or Computer Engineering and available for 1 year internship program to work Intel's chipsets. Need to have good understanding of CMOS, VLSI design and Test. Knowledge of Scripting in Perl, shell, Python . A very good team player with good interpersonal, planning and excellent communication skills. Preferred colleges Any IIT, Any NIT, MIT, VIT, Thapar Eng College, Delhi College of Engineering , PES, Punjab Eng College ,RVCE.

As a skilled professional in third party IP design and integration across multiple technology nodes such as 28nm, 65nm, and 130nm, you will play a crucial role in silicon realization of LC resonance-based energy recycling patented IP. You will be responsible for DSM Library development, including Fin FETs, tailored for adoption by customers into future System on Chip (SoC) solutions. Your expertise will be instrumental in the successful tape out of benchmark test chips and subsequent characterization to secure customer design wins. You are expected to deliver results within specified timelines aligned with Management By Objectives (MBOs) and contribute to the development of first silicon success methodologies. Your proactive approach will aid in achieving aggressive objectives outlined by the organization. Additionally, you will support global teams with flexibility in terms of working times and locations, as required. Your core responsibilities will involve designing, simulating, and verifying cutting-edge CMOS digital and analog circuits. You will provide hands-on supervision to IC circuit and mask designers, offering valuable insights into floorplan and layout guidelines. Furthermore, you will actively support technology transfer to product development teams and engage in the debugging and characterization of designs. To excel in this role, you should possess a minimum of 5 years of experience in CMOS Analog/Mixed Signal Circuit Design. A strong fundamental understanding of transistor devices and analog transistor-level design is essential. Your hands-on experience with Giga-bit circuits and subsystems, such as oscillators, biasing circuits, bandgap references, regulators, op-amps, and high-speed clocking circuits, will be highly beneficial. Familiarity with PLL, DLL, transmitters, receivers, and equalization techniques is advantageous. Proficiency in utilizing IC design tools like Synopsys/Cadence for Analog Circuit Design, along with expertise in circuit simulation, system simulation, layout design, physical design, physical verification, parasitic extraction, and full chip verification is expected. Additionally, scripting skills in Perl and proficiency in Verilog/Verilog AMS modeling and design are valuable assets for this role. Key Skills: Transistor Level Design, Circuit Simulation, Circuit Design, CMOS Analog/Mixed Signal Circuit Design, Physical Design, Scripting Skills (Perl), IC Design Tools like Synopsys/Cadence, Design, Layout Design, Verilog/Verilog AMS, System Simulation,

We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a seasoned professional with a deep understanding of Analog and Mixed Signal Circuit Layout With a minimum of 9 years of experience, you bring a strong background in transistor-level analog and mixed-signal layout design You possess extensive knowledge in CMOS and FINFET technologies, and your expertise in semiconductor device physics sets you apart Your problem-solving skills are top-notch, and you are detail-oriented, self-directed, and passionate about learning new techniques You are adept at communicating effectively with cross-functional teams to ensure successful project execution You thrive in a dynamic environment and are excited about the opportunity to contribute to cutting-edge technology that drives the future, What Youll Be Doing: Plan, estimate area/time, schedule, delegate, and execute tasks to meet project milestones in a multi-project environment, Collaborate with cross-functional teams to ensure successful project execution, Create and review layout documents to ensure they meet quality standards and are delivered on time, Support the team in troubleshoot physical verification issues to achieve clean and desired results Device level floorplan, placement, routing, and physical verification of all critical high-speed blocks Design and development of transistor-level Analog and mixed-signal layout as per project needs The Impact You Will Have: You will drive the Layout design of the project from Floorplan, design and development till the project release, You will drive the Layout design of the project from Floorplan till the project release and lead the project throughout the entire design and development phase, Strong Knowledge and experience in layout design of high-speed blocks in latest Tech Nodes (2nm, 3nm, 5nm) You will drive the design and development of high-quality analog and mixed-signal layouts, Your expertise will ensure the successful implementation of CMOS and FINFET technologies, Through effective troubleshooting, you will contribute to achieving clean physical verification results, Your attention to detail will ensure that layout documents meet quality standards and deadlines, By managing project schedules and milestones, you will help deliver projects on time, Your collaboration with cross-functional teams will enhance project success and innovation What Youll Need: Bachelor's or Master's degree in Electrical Engineering or a related field, Minimum 9+ years of experience in Analog and Mixed Signal Circuit Layout, Proficiency in Analog Layout Flow from device placement to GDS release, Strong knowledge of CMOS and FINFET technologies and semiconductor device physics, Experience with EDA tools for custom mixed-signal layout flows, Understanding of CMOS fabrication technology and deep sub-micron effects on layout, Knowledge of electro-migration, reliability concepts, and ESD/LUP concepts as applied to layout, Passion for learning and exploring new techniques, Who You Are: A proactive leader with excellent communication and mentoring skills, Detail-oriented and committed to delivering high-quality results, Innovative and capable of driving technological advancements, Collaborative and able to work effectively with cross-functional teams, A problem-solver with strong analytical skills, The Team Youll Be A Part Of: You will be part of a dynamic and innovative layout design team focused on creating high-performance analog and mixed signal layouts The team is dedicated to excellence and continuous improvement, working collaboratively to achieve the organization's goals, Show

Job Opportunity: Technical Editor We are currently seeking a highly skilled and detail-oriented Technical Editor to join our team. The ideal candidate will meet the following qualifications: Education: Must hold a degree. Experience: A minimum of 2 years of experience as a technical editor, with expertise in both journals and books, preferably with a focus on books. Expertise in Style Manuals: In-depth knowledge of style manuals such as AMA (American Medical Association), APA (American Psychological Association), and CMoS (Chicago Manual of Style). Endnote Editing: Proven experience in editing endnotes in accordance with CMoS style. Proficient in MS Office: Strong working knowledge of MS Office Suite. Skills: Strong analytical and problem-solving abilities, with a keen eye for detail. If you have a passion for precision and enjoy working with the complex technical content, we would love to hear from you! We are seeking a highly motivated and enthusiastic Entry-Level Trainee/Shadow Salesperson with a strong digital marketing and social media background to join our growing team. This role will provide an excellent opportunity to learn the ropes of sales within the publishing and IT training sectors by shadowing experienced sales professionals, while also contributing to lead generation through digital channels. The ideal candidate will be a quick learner, possess excellent communication skills, and have a passion for building relationships. Responsibilities: Lead Generation (Digital Focus): Develop and execute digital marketing strategies to generate qualified leads. This includes: o Managing and optimizing social media platforms (LinkedIn, Twitter, etc.) o Creating engaging content for social media and other online channels. o Utilizing SEO best practices to improve online visibility. o Running targeted online advertising campaigns. o Tracking and analysing campaign performance and making data-driven adjustments. Market Research: Conduct market research to identify potential clients and understand their needs. CRM Management: Maintain accurate records of leads and client interactions within the company's CRM system. Sales Support: Assist the sales team with administrative tasks, such as preparing proposals, presentations, and other sales materials. Networking: Attend industry events and networking opportunities to build relationships with potential clients. Reporting: Regularly report on lead generation activities and sales progress. Qualifications: Bachelor's degree in Marketing, Business, or a related field preferred. Proven experience in digital marketing and social media marketing (portfolio or examples required). Strong understanding of social media platforms, analytics, and advertising. Excellent written and verbal communication skills. Ability to learn quickly and adapt to new situations. Strong organizational and time-management skills. Proficiency in Microsoft Office Suite (Word, Excel, PowerPoint). Experience with CRM software is a plus. Interest in the publishing and/or IT training industries is a plus.

Alternate Job Titles: Senior R&D Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a passionate and driven engineering professional with a strong foundation in VLSI concepts, CMOS circuit design, and EDA tools With2-3 years of hands-on experience in the semiconductor industry, you thrive in dynamic environments where innovation, collaboration, and continuous learning are valued Your curiosity drives you to explore emerging technologies such as AI/ML, and you have developed proficiency in scripting languages like TCL and Python to solve complex engineering challenges You have a keen eye for detail and a solid grasp of timing, power, and noise analysis, enabling you to deliver robust and reliable design solutions Your exposure to industry-standard tools such as VCS, Design Compiler, Primetime, and HSPICE/Primesim has honed your technical expertise, and you are comfortable navigating various stages of the design flow, from synthesis to signoff As a team player, you communicate effectively, share knowledge openly, and support your peers in achieving shared goals You value diversity, equity, and inclusion, and are eager to contribute to a culture that fosters creativity and personal growth If you are ready to challenge yourself, make an impact, and be part of a world-class engineering team, Synopsys is the place for you, What Youll Be Doing: Developing and maintaining scripts and automation flows using TCL, Python, and Make to streamline EDA tool operations and design processes, Performing advanced timing, power, and noise analysis on CMOS circuits, leveraging your understanding of setup/hold constraints and leakage concepts, Contributing to the characterization of standard cell libraries, including NLDM/CCSN and LVF methodologies, and ensuring accurate modeling for signoff, Collaborating with design, verification, and methodology teams to optimize PPA (Power, Performance, Area) and address STA (Static Timing Analysis) challenges, Utilizing tools such as VCS, Design Compiler, Primetime, and HSPICE/Primesim to support verification, synthesis, and signoff activities, Participating in root cause analysis of timing and power issues, implementing innovative solutions, and documenting best practices for future projects, Staying abreast of the latest trends in AI/ML and exploring their application in EDA tool flows and design optimization, The Impact You Will Have: Accelerate the delivery and quality of Synopsys' IP and design solutions through automation and process innovation, Enhance product reliability by ensuring precise timing and power characterization, directly influencing customer satisfaction, Drive cross-functional collaboration, sharing insights and solutions that elevate team performance and project outcomes, Contribute to the adoption of cutting-edge AI/ML techniques, positioning Synopsys as a leader in intelligent EDA workflows, Reduce design cycle times and resource bottlenecks through effective scripting and workflow optimization, Mentor and support junior engineers, fostering a culture of knowledge sharing and continuous improvement, What Youll Need: 2-3 years of experience in VLSI design, EDA tool flows, or related semiconductor engineering roles, Proficiency in TCL, Python, and Make for scripting and automation, Strong understanding of CMOS circuit fundamentals, including timing (setup/hold), power (leakage/dynamic), and noise analysis, Experience with cell library characterization methodologies (NLDM/CCSN, LVF) and familiarity with library constructs and syntax, Working knowledge of STA analysis, PPA trends, and basic understanding of PNR (Place & Route), Hands-on experience with EDA tools: VCS, Design Compiler, Primetime, HSPICE/Primesim, Who You Are: Analytical thinker with strong problem-solving skills and a passion for innovation, Effective communicator, able to collaborate across disciplines and share complex ideas clearly, Self-motivated and adaptable, eager to learn new technologies and methods, Detail-oriented with a commitment to delivering high-quality results under tight deadlines, Team player who values diversity, equity, and inclusion in the workplace, The Team Youll Be A Part Of: You will join a vibrant team of R&D engineers focused on advancing the state of the art in chip characterization, timing, and power analysis Our team collaborates closely with cross-functional partners in design, verification, and methodology to deliver next-generation semiconductor solutions We foster a culture of innovation, mentorship, and continuous improvement, ensuring every member has an opportunity to grow and make a meaningful impact, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process, Show

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Overview: This position centers on floor-planning expertise at both block and top levels for industry-leading CPU core designs, with a strong emphasis on scalability and achieving aggressive Power, Performance, and Area (PPA) targets. The role involves working on cutting-edge technology nodes and applying advanced physical design techniques to push the boundaries of CPU performance and efficiency. Preferred Qualifications: Masters degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience In depth end to end experience from RTL2GDS, taping out at least 5 complex designs Direct hands-on experience with bus/pin/repeater planning for entire IP Key responsibilities include: Driving floorplan architecture and optimization in collaboration with PD/RTL teams to maximize PPA Engaging in cross-functional collaboration with Physical design, timing, power, and packaging teams to ensure holistic design convergence Partnering with EDA tool vendors and internal CAD teams to develop and enhance automation flows and methodologies for improved design efficiency Making strategic trade-offs in design decisions to achieve optimal PPA outcomes while maintaining schedule and quality targets End to End Physical verification closure for subsystem. The ideal candidate will have/demonstrate the following: Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, big and high speed designs Experience with physical synthesis and implementation tools - Cadence Innovus/Genus and Synopsys Fusion Compiler. Must have good knowledge of static timing analysis, reliability, and power analysis Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks Strong understanding of CPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance Solid working knowledge of scripting skills including tcl, perl or python Excellent communication skills and collaborating in a team environment is a must Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues. (Mostly Working on Calibre tool) Experience in IO, Bump planning and RDL routing Strategy. Preferred Skills: Clock implementation, power delivery network design choices, process technology, prior experience in flow and methodology development, block closure Close interaction with design and architecture teams to influence scalable floor-plans and optimal bus/pin/repeater planning for entire IP and its sub-blocks Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff Hands on experience working with very complex designs that push the envelope of Power, Performance and Area Hands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageous Hands on experience on Innovus/FC tool based scripting & python/TCL scripting. Prior experience in flow and methodology development is an advantage Excellent debug and analytical skills and demonstrated successes in floor-planning large IP and high frequency designs Ability to drive Physical Implementation teams in Floor-planning and work well in a collaborative environment with multi-disciplined teams Minimum Qualifications: Bachelors degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience which includes bus/pin/repeater planning at the top level Strong background in VLSI design, physical implementation and scripting Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools Hands on experience taping out designs in sub-micron technology node design Expect strong self-motivation and time management skills Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm's toll-free number found . Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact .

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: We know our employees ideas change the world. For more than three decades, weve been a global leader in mobile technology, continually pushing the boundaries of whats possible. Working with customers across industries "” from automotive to health care, from smart cities to robotics"” we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. Qualcomm is looking for an energetic, creative and self-driven engineer to work in Modem , Multimedia , Connectivity , Computer Vision and Image Processing , software implementation and hardware acceleration. The work will directly influence the various subsystems within the SoC. The ideal candidate would have very strong problem solving and analytical skills combined with creativity and a passion for innovation. They would be able to carry forward that new idea, concept, and/or application that will propel systems to new levels of effectiveness and efficiency. At Qualcomm you will perform detailed technical analysis, translate ideas into models, SW and/or HW and work closely with other teams to help deliver real products. At Qualcomm, the sky's the limit. College Graduates play important roles everywhere in the company. Many of our 27,000+ employees join us right out of school because we're working on the cutting edge in wireless. Complex wireless devices are only as powerful as the software that runs them. As a software engineer, you will develop, implement and maintain multimedia, gaming and application software for the world's leading-edge mobile devices. We know our employees ideas change the world. For more than three decades, weve been a global leader in mobile technology, continually pushing the boundaries of whats possible. Working with customers across industries "” from automotive to health care, from smart cities to robotics"” we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design\ Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU Design Minimum Qualifications: Associate's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field. Must have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skill Preferred Qualifications: Bachelor's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: We know our employees ideas change the world. For more than three decades, weve been a global leader in mobile technology, continually pushing the boundaries of whats possible. Working with customers across industries "” from automotive to health care, from smart cities to robotics"” we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. Qualcomm is looking for an energetic, creative and self-driven engineer to work in Modem , Multimedia , Connectivity , Computer Vision and Image Processing , software implementation and hardware acceleration. The work will directly influence the various subsystems within the SoC. The ideal candidate would have very strong problem solving and analytical skills combined with creativity and a passion for innovation. They would be able to carry forward that new idea, concept, and/or application that will propel systems to new levels of effectiveness and efficiency. At Qualcomm you will perform detailed technical analysis, translate ideas into models, SW and/or HW and work closely with other teams to help deliver real products. At Qualcomm, the sky's the limit. College Graduates play important roles everywhere in the company. Many of our 27,000+ employees join us right out of school because we're working on the cutting edge in wireless. Complex wireless devices are only as powerful as the software that runs them. As a software engineer, you will develop, implement and maintain multimedia, gaming and application software for the world's leading-edge mobile devices. We know our employees ideas change the world. For more than three decades, weve been a global leader in mobile technology, continually pushing the boundaries of whats possible. Working with customers across industries "” from automotive to health care, from smart cities to robotics"” we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design\ Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU Design Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Educational Background:Masters, BachelorsElectrical Engineering , VLSI , Embedded and VLSI , ECE Must have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skill Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Interns Group, Interns Group > Interim Engineering Intern - HW Qualcomm Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. General Summary: We know our employees ideas change the world. For more than three decades, weve been a global leader in mobile technology, continually pushing the boundaries of whats possible. Working with customers across industries "” from automotive to health care, from smart cities to robotics"” we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU Design Must have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skill Educational Background:Masters, BachelorsElectrical Engineering , VLSI , Embedded and VLSI , ECE Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail myhr.support@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

You are a highly motivated and experienced professional with a deep understanding of VLSI design and a strong background in high-speed protocols Analog Circuit Design CMOS circuit design and layout methodology & flow Familiarity with ASIC design flow Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus What Youll Be Doing: DDR/HBM Memory Interface I/O Circuit and layout design including GPIO and Special IOs Work with DDR/HBM PHY team, package engineers and system engineers to meet design specifications What Youll Need: Bachelor's and/or Master's Degree in Electrical Engineering or similar with a focus on VLSI design Who You Are: Creative and results-oriented, capable of managing multiple tasks concurrently Strong verbal and written communication skills in English Ability to work collaboratively across teams to deliver solutions to customers Strong analytical, reasoning, and problem-solving skills Willingness to travel occasionally to support customer engagements The Team Youll Be A Part Of: The team focuses on enabling our Interface IP customers to integrate the IP into their SoC and assist them through their design flows, debugging critical issues, and supporting silicon bring-up This collaborative team works closely with customers to ensure the successful deployment of Synopsys' leading Interface IP products in various market segments

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical design and execution issues related to physical verificationand sign-off. Own physical verification and sign-off flows, methodologies and execution of SoC/cores. Good hands on Calibre, Virtuoso etc. Requirements : Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Expertise in physical verification of Block/Partition/ Full-chip-level DRC, Experience and understanding of all phases of the IC design process from RTL-GDS2. LVS, ERC, DFM Tape out process on cutting edge nodes, Preferably worked on 3nm/5nm/7nm/12nm/14nm/16nm nodes at the major foundries Experience in debugging LVS issues at chip-level/block level with complex analog-mixed signal IPs Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.) Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up etc. Experience with ERC rules and ESD rules has an added advantage Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to Engineer and mentor junior engineers, fostering their professional growth and development. Preferred qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Proven track record with multiple successful final production tape-outs Proven ability to independently deliver results and be able to work hands-on as and guide/help peers to deliver their tasks Be able to work under limited supervision and take complete accountability. Excellent written and verbal communication skills Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration and Physical verification challenges.

We are seeking a highly skilled Senior Analog Design Engineer with 6+ years of experience in designing, simulating, and validating analog and mixed-signal circuits. The ideal candidate should have hands-on expertise across the full custom design flow, from specification to silicon validation. Key Responsibilities: Design and develop analog/mixed-signal IPs such as ADCs, DACs, LDOs, Bandgaps, PLLs, Op-Amps, etc. Perform schematic entry, simulations (pre-layout/post-layout), and layout supervision. Drive transistor-level design using industry-standard tools (Cadence/Synopsys). Lead block-level design reviews, documentation, and verification. Collaborate with layout, digital, and validation teams across the project lifecycle. Support silicon bring-up, debug, and characterization. Requirements: 6+ years of hands-on analog IC design experience in CMOS processes (28nm/65nm/180nm, etc.) Strong knowledge of analog fundamentals and design trade-offs. Experience with simulation tools like Spectre, HSPICE, and Monte Carlo analysis. Proven tape-out and silicon success experience. Good communication and team leadership skills. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of analog design!

We are looking for an experienced Analog Layout Engineer with 8+ years of hands-on experience in full custom layout of analog and mixed-signal blocks. The ideal candidate should have expertise in advanced CMOS technologies and be capable of delivering high-quality layout from specifications to tape-out. Key Responsibilities: Execute full custom layout for analog/mixed-signal blocks (OpAmps, Bandgaps, LDOs, ADCs, etc.) Floorplanning, device matching, parasitic optimization, and electromigration compliance Perform DRC/LVS/ERC checks and work closely with verification teams Collaborate with circuit designers to optimize performance and area Ensure quality layout delivery in accordance with tape-out schedules Support post-layout simulation and debug efforts Requirements: 8+ years of experience in analog/custom layout Strong understanding of matching, shielding, and analog layout best practices Hands-on experience with layout tools (Virtuoso, IC Compiler, Calibre, etc.) Knowledge of various technology nodes (180nm to FinFET) Good communication, teamwork, and problem-solving skills Apply Now! If you meet the above qualifications and are ready to take on this exciting challenge, we would love to hear from you. Share your resumes at info@silcosys.com

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers.Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLLAdditional responsibilities:logic (RTL) design, timing closure, CDC analysis etc.Understand and Design Power efficient logic.Agile project planning and execution.RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 8+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog

Analog IP development including circuit design, layout, AMS verification, and characterization. Analog IP development Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs,

Your future role Take on a new challenge and apply your engineering expertise in a dynamic and innovative field. Youll work alongside collaborative, forward-thinking, and solution-oriented teammates. You'll play a pivotal role in ensuring the successful introduction of Alstom products during the Product Introduction (PI) period, as well as during commissioning and warranty phases. Day-to-day, youll work closely with teams across the business (such as Quality, Engineering, and Maintenance teams), support technical reviews with suppliers and customers, and much more. Youll specifically take care of diagnosing technical malfunctions and defining troubleshooting methodologies, but also supporting field modifications and ensuring compliance with EHS (Environmental Health and Safety) standards. Well look to you for: Providing technical leadership, guidance, and support to the PI team Investigating and resolving technical and quality issues Driving reliability growth through event investigation and reliability forecasts Ensuring the completeness and quality of failure/event data for RAMS (Reliability, Availability, Maintainability, Safety) exploitation Supporting technical reviews with internal and external stakeholders Facilitating information flow within the PI Customer Site and project teams All about you We value passion and attitude over experience. Thats why we dont expect you to have every single skill. Instead, weve listed some that we think will help you succeed and grow in this role: Graduate degree in Engineering or Industrial fields Experience or understanding of mechanical or electrical/electronic engineering Knowledge of railway safety and RAM methodologies Familiarity with EHS standards and practices A strong proficiency in English Problem-solving and data analytics skills Customer-focused mindset and ability to collaborate effectively Things youll enjoy Join us on a life-long transformative journey the rail industry is here to stay, so you can grow and develop new skills and experiences throughout your career. Youll also: Enjoy stability, challenges, and a long-term career free from boring daily routines Work on cutting-edge projects that shape the future of mobility Collaborate with transverse teams and supportive colleagues Contribute to innovative and sustainable transport solutions Utilise our inclusive and flexible working environment Steer your career in whatever direction you choose across functions and countries Benefit from our investment in your development, through award-winning learning programs Progress towards leadership or technical expert roles Benefit from a fair and dynamic reward package that recognises your performance and potential, plus comprehensive and competitive social coverage (life, medical, pension) You dont need to be a train enthusiast to thrive with us. We guarantee that when you step onto one of our trains with your friends or family, youll be proud. If youre up for the challenge, wed love to hear from you!

As a skilled professional in Standard Cell Library Development, you will leverage your hands-on experience and expertise to contribute effectively to the characterization processes. Your solid understanding of CMOS and FinFET technologies will be key in ensuring the success of the projects at hand. Additionally, exposure to Verilog modeling will be advantageous in this role, although it is not mandatory. Your role will require strong debugging and problem-solving skills specifically related to cell design, SPICE simulation, and characterization. This will enable you to address challenges effectively and ensure the quality of the developed libraries. Proficiency in EDA tools is essential for this position. Experience with tools such as Cadence Virtuoso, Calibre, HSPICE, and other industry-standard simulation and characterization tools will be beneficial in carrying out your responsibilities efficiently. Overall, your role will be crucial in contributing to the development of Standard Cell Libraries, and your expertise will play a vital part in the success of the projects.,

You will be working as a Semiconductor Domain Consultant for a reputable multinational corporation. Your primary responsibilities will include leveraging your expertise in semiconductor manufacturing processes, chip design, and testing methodologies. You should have a strong understanding of semiconductor technologies such as CMOS, memory devices, RF, power semiconductors, and sensors. Additionally, you will be expected to have experience in semiconductor supply chain management and market analysis. In this role, it is essential to possess excellent communication, presentation, and client relationship management skills. You should be capable of working both independently and collaboratively within a team environment. Knowledge of industry standards, regulations, and certifications is crucial for this position. Project management experience would be considered advantageous. It would be beneficial if you have experience with advanced semiconductor packaging technologies and are familiar with semiconductor EDA (Electronic Design Automation) tools and software. An understanding of semiconductor equipment and infrastructure is also desirable. Furthermore, experience in emerging fields like AI/ML hardware accelerators, quantum computing, and IoT would be an added advantage. The position is based in PAN India, and the ideal candidate will possess a strong technical skill set in semiconductor manufacturing processes. If you meet the requirements and are looking for a challenging opportunity in the semiconductor domain, we encourage you to apply promptly.,

As a Lead Memory Design Engineer, you will be responsible for driving the architecture, design, and development of advanced memory IPs including SRAMs, ROMs, CAMs, and Register Files. Your role will involve leading a team of designers, collaborating with cross-functional groups, and delivering high-performance, low-power, and silicon-proven memory solutions at advanced technology nodes. Your key responsibilities will include defining architecture and design specifications for custom memory IPs, optimizing circuits such as memory cell arrays, sense amplifiers, and decoders, leading schematic-level design and simulation, collaborating with layout and verification teams, guiding post-layout activities, ensuring designs meet requirements for DFM and reliability, contributing to methodology development, supporting silicon bring-up, and providing technical leadership to junior engineers. To be successful in this role, you should have a B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Engineering, along with 8+ years of experience in full-custom memory design. You should possess a solid understanding of CMOS analog/digital circuit design principles, expertise in circuit simulation tools, experience with advanced nodes, and hands-on experience with variation analysis, IR drop, and EM checks. Strong analytical, communication, and leadership skills are essential for this position. Preferred qualifications include experience in memory compiler design, knowledge of low-power memory design techniques, experience with ECC and redundancy strategies, familiarity with ISO 26262/Safety compliance, and scripting knowledge for automation of design and simulation flows. If you are interested in this opportunity, please share your CV with Sharmila.b@acldigital.com.,

Analog Layout Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech ESSENTIAL DUTIES AND RESPONSIBILITIES: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

Job Description • M emory layout engineer. • Experience Level 3 to 8 Years ( Mid-Level Role) Responsibilities: As Memory Layout Engineer, we will work on developing memory compilers layouts and memory Fast Cache instances layouts for our next generation Cores achieving outstanding PPA. Required Skills and Experience : We Prefer graduate or postgraduate from a University or Engineering School, in Electronic Engineering or equivalent Engineering Degree. We expect you to have basic understanding of CMOS Transistors, their behaviors. We expect some basic understanding of CMOS logic design and layout. Understanding of Power versus Performance versus Area trade-offs in typical CMOS design. You have an engineering demeanor and Passion for Circuit layouts. Expected to have good interpersonal skills. Capable of creating high quality design rule driven layout Able to review schematics with engineering and propose changes based on layout implications. Exploring possible floor planning options and proposing improvements Minimum 5Yrs of experience in SRAM / memory layouts creation and backend verifications including EMIR analysis. Nice To Have Skills and Experience : You know basic scripting languages, e.g. Perl/skill. Some Experience of working on Cadence or Synopsys flows.

You will be responsible for the layout of Analog and mixed-signal modules in CMOS and Power Technologies, with a specific focus on DC-DC converters for power management ICs. This includes designing Analog and mixed-signal system resource blocks such as POR, Bandgap, LDO, Oscillator, amplifier, and power FET. You will also be involved in chip floor-planning, pad ring layout, power busing, bonding, and tape-out activities. Your role will require a deep understanding of layout verification processes like DRC, LVS, Latch-up, and Electro-migration. Additionally, you will collaborate closely with designers to define block layout requirements, match patterns, and ensure signal integrity. To qualify for this position, you should hold a Diploma, Bachelor's, or Master's Degree in Electrical/Electronic Engineering, Physics, or a related field with 7 to 10 years of relevant experience. Your expertise should include Analog and mixed-signal layout, especially in CMOS and Power Technologies. Strong analytical skills and a comprehensive understanding of Analog Layout are essential for this role. Familiarity with power switch layout, electro-migration, and thermal analysis would be advantageous. Proficiency in computer-aided design tools and methodologies is also required to excel in this position.,

You will be joining Tata Electronics Private Limited (TEPL), a greenfield venture of the Tata Group specialized in manufacturing precision components. As a subsidiary of Tata Sons Pvt. Ltd., TEPL is at the forefront of establishing India's first AI-enabled state-of-the-art Semiconductor Foundry. This cutting-edge facility is dedicated to producing chips for various applications including power management IC, display drivers, microcontrollers (MCU), and high-performance computing logic to cater to the increasing demands in sectors such as automotive, computing, data storage, wireless communications, and artificial intelligence. Your primary responsibilities will revolve around the integration of RF-CMOS and RF-SOI technologies, enhancing existing technologies by adding features like active devices and passives, and developing new technologies to enhance performance and expand application capabilities. You may also lead projects related to Wide Band Gap RF technologies, design and layout test chips for optimization, assessment, and SPICE model extraction. Moreover, you will be involved in end-to-end project management, from the initial project justification to final qualification and yield ramp, ensuring the achievement of desired performance, quality, yield, schedule, and cost targets. Collaboration with the Design enablement team and CAD partners to create a user-friendly PDK with a well-characterized toolbox will be essential. You will also engage with universities, research labs, and commercial entities to drive a world-class roadmap and build strong customer relationships based on TEPL's technical capabilities. Essential attributes for this role include the ability to manage, mentor, and lead a team, work independently with a drive to succeed, collaborate effectively across diverse teams globally, and exhibit leadership skills to influence all levels of the organization. Additionally, you should be adaptable, inclusive, innovative, and resilient in the face of challenges, fostering a culture of learning, collaboration, and creativity. To qualify for this position, you should hold an M.S. or Ph.D. in Electrical Engineering, Physics, or equivalent, with a strong understanding of CMOS, SiGe BICMOS, RF power devices, and technology integration. Your expertise should include knowledge of RF technology parameters, competitive performance achievement, volume manufacturing delivery, integration feature impact assessment, basic circuit design and characterization, and familiarity with RF front end module trends and standards. The ideal candidate will have over 15 years of experience in the semiconductor industry, a proven track record of developing new technologies for high-volume production, problem-solving skills using design of experiments and analytical tools, and a history of publications and patents. Your ability to lead cross-functional teams, work across cultures and geographies, and maintain an innovative and competitive mindset will be key to success in this role.,