Physical Verification Professional

Responsibilities

• Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries.
• Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out.
• Work hands-on to solve critical design and execution issues related to physical verificationand sign-off.
• Own physical verification and sign-off flows, methodologies and execution of SoC/cores.
• Good hands on Calibre, Virtuoso etc.

Requirements

• Bachelors or Masters degree in Electrical Engineering or Electronics & Communications.
• Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics.
• Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.
• Expertise in physical verification of Block/Partition/ Full-chip-level DRC, Experience and understanding of all phases of the IC design process from RTL-GDS2.
• LVS, ERC, DFM Tape out process on cutting edge nodes, Preferably worked on 3nm/5nm/7nm/12nm/14nm/16nm nodes at the major foundries
• Experience in debugging LVS issues at chip-level/block level with complex analog-mixed signal IPs
• Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.)
• Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components
• Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up etc.
• Experience with ERC rules and ESD rules has an added advantage
• Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment.
• Proven ability to Engineer and mentor junior engineers, fostering their professional growth and development.

Preferred qualifications:

• Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology.
• Proven track record with multiple successful final production tape-outs
• Proven ability to independently deliver results and be able to work hands-on as and guide/help peers to deliver their tasks
• Be able to work under limited supervision and take complete accountability.
• Excellent written and verbal communication skills
• Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration and Physical verification challenges.