Responsibilities: SoC integration/scenario/performance verification including CHI, DDRx/LPDDRx, and AI accelerator blocks in RTL. Develop test plans, SystemVerilog/Verilog testbenches, and C-based embedded tests. Collaborate with cross-functional teams architecture, design, performance, silicon validation, FPGA, and board teams. Plan, track and report verification tasks to management. Skills & Experience Required: Strong knowledge of Verilog/SystemVerilog HDL. Hands-on experience in SoC verification using embedded C/C++/assembly (ARM preferred). Experience in UVM/OVM, emulation, formal verification, UPF/Power-aware verification. Expertise in GLS, DFT/DFD, CDC (Clock Domain Crossing). Familiar with ARM SoC boot flows, cache coherency, SoC verification flow & strategy. Scripting experience in Python, Perl, Tcl, Shell. Excellent debugging and problem-solving skills.

We are hiring Embedded Engineers with strong experience in C/C++ programming and ARM-based architectures. This role offers exposure to cutting-edge embedded systems within a global semiconductor leader. Roles and Responsibilities: Develop and debug low-level embedded software (C/C++/Assembly). Work on firmware and bare-metal application development. Validate ARM-based architectures and support hardware bring-up. Work in a Unix/Linux-based environment. Mandatory Key Skills: 1. C/C++ / Assembly programming (embedded systems) 2. Computer architecture & ARM basics 3. Unix/Linux environment familiarity 4. Firmware / Low-level OS development 5. Debugging & validation skills Nice to Have: UEFI & Linux bootloader exposure Verification (Test Plan/Test Case development)

We are hiring an Emulation Engineer with hands-on experience in verification and emulation for complex multi-processor systems. This is a contractual role with a global semiconductor leader. Roles and Responsibilities: Work on verification using emulator platforms. Understand and validate complex system-level architectures. Develop and execute emulation-based testbenches for system-level verification. Work on C/C++ programming for testbench and validation activities. Drive and review technical specifications related to emulation and validation. Mandatory Key Skills: 1. Emulation-based verification (2+ years) 2. System-level architecture knowledge 3. C/C++ programming (hands-on) 4. Multi-processor / Multi-chip system experience 5. Debugging & validation of hardware platforms Nice to Have: Bare-metal software development OS / Firmware validation experience

Job Description: The Architecture and Technology Group (ATG) at Arm is looking for an Architecture Verification Engineer to contribute to the development of Architecture Compliance Kits that ensure Arm implementations adhere to architectural specifications. This is an exciting opportunity to work on cutting-edge Arm architectures and apply hardware/software verification skills to develop high-quality Architecture Verification IP. Key Responsibilities: Analyze architecture definitions, conduct feasibility studies, and develop verification strategies. Design and develop test cases/scenarios using Assembly, C, HVL, and automation techniques. Collaborate with internal teams to ensure compliance with Arms architectural specifications. Develop and execute test plans and verification methodologies. Contribute to the success of the team by taking on additional responsibilities. Required Skills & Experience: 1-2 years of experience in engineering (CPU/IP verification is a plus). Strong understanding of computer architecture. Proficiency in C/C++/Assembly programming with good software engineering practices. Experience with test plan and testcase development in a verification environment. Familiarity with Unix/Linux environments. Prior experience in CPU verification is an added advantage. Why Join Us? Work on cutting-edge Arm architectures and System IPs. Be part of a highly skilled and innovative verification team. Excellent career growth opportunities in a world-class semiconductor company.

Requirements Good knowledge of Standard cell layout design Good knowledge of CMOS logic Experience in working on Std cell Layout for Bulk CMOS. FINFET experience is not a must but preferable. Expertise in using industry-standard tools like cadence Virtuoso, Calibre Experience in implementation of ESD layouts, handling Antenna/EM, etc Ability to independently debug layout issues Good team player Good in SKILL programming or other scripting languages

We are looking for a Senior HPC Engineer to join our IT Infrastructure Engineering & Application (IE&A) group. You will play a critical role in managing high-performance compute environments, automating solutions, and supporting engineering teams across Arm. If you are passionate about HPC systems and want to work on global infrastructure projects, this is the role for you! Roles & Responsibilities: Administer and support IBM Spectrum LSF clusters Develop and maintain automation scripts using Bash, Shell, Python, or Perl Work with public cloud platforms such as AWS, GCP, or Azure Handle ticket-based support and proactively resolve infrastructure issues Collaborate on key engineering projects to enhance system resilience and security Mandatory Key Skills: 1. IBM Spectrum LSF Administration 2. Linux (RedHat) System Administration 3. Bash/Shell/Python/Perl Scripting 4. Public Cloud Platform (AWS/GCP/Azure) 5. Automation & DevOps Tools (Terraform/Ansible/CI/CD)

We're Hiring Senior HPC Engineer | 3+ Years | Bangalore Are you skilled in managing High Performance Computing ( #HPC ) environments using #Slurm or #PBS job schedulers? Ready to contribute to cutting-edge semiconductor innovation? Join our global infrastructure team and help us power the future of chip design and EDA workflows through world-class #HPC solutions! --- What Youll Work On: Manage and administer #HPC clusters using #Slurm / #PBS #job_schedulers Automate system processes using Bash, Python, or Shell scripting Work on Linux (preferably RedHat) environments Support and scale infrastructure across on-prem and cloud platforms (AWS/GCP/Azure) Collaborate with engineers globally to improve performance, stability, and productivity --- What We’re Looking For: 3+ years of experience in #HPC infrastructure support/engineering Strong hands-on skills with #Slurm / #PBS / #LSF (any one or more) Linux admin (RedHat preferred), scripting (Bash, Python, Perl) Exposure to EDA tools or FlexLM license management is a plus Familiarity with cloud platforms or tools like Terraform/Ansible is a bonus --- Location: Bangalore (Hybrid/Onsite) Experience: 3 to 6 Years Competitive salary + opportunity to work on global infrastructure projects --- If you're passionate about #HPC systems, automation, and infrastructure innovation — we'd love to hear from you!

Job Description: We are hiring a talented Software Engineer with deep expertise in static code analysis and SAST tools like Coverity for one of our prestigious clients. If you're enthusiastic about code quality, automation, and secure development practices, this is a fantastic opportunity to work on cutting-edge tech stacks. Responsibilities: Manage and integrate SAST tools (Coverity) into CI/CD pipelines. Analyze and interpret Coverity/Blackduck scan reports and defect types. Review and triage violations, offer remediation advice. Automate report generation and filtering using Python, Shell, or Groovy. Tune Coverity checkers, component mapping, suppression rules. Collaborate with dev teams to resolve issues and improve code quality. Optional: Deliver training on Coverity and SAST best practices. Required Skills: Proven experience with Coverity or similar tools (SonarQube, Helix QAC). Strong scripting skills: Python, Shell/Bash. Familiarity with CI/CD tools like Jenkins, Bitbucket. Solid understanding of Git workflows and SDLC. Proficient in reading/debugging C, C++ code (Embedded domain experience is a plus). Good communication and collaboration skills. Budget: As per market standards (Based on experience) Notice Period: Immediate to 30 days preferred

Position: EDA Analog Design/Technology Porting EngineerLocation: Noida, IndiaExperience: 5+ yearsTarget Domain: Analog Design FlowClient: [Confidential / NXP] Key Skills: Virtuoso, Analog Design, Technology Porting, Linux, EDA, IC Design Job Description: As part of the Design Enablement – Analog team, the candidate will contribute to developing and supporting custom EDA design flows. The primary focus is on enabling migration of analog, mixed-signal, and RF designs across technologies/foundries. Key Responsibilities: Setup and execute design/technology porting flows using EDA tools Define migration plans with Business Line teams Work with PDK and Device teams for technology mapping Enable schematic layout porting, simulation, and validation Collaborate with PDK, Modeling, and Analog teams across geographies Drive continuous tool and flow enhancements Required Qualifications: B.E./M.E./M.Tech in EEE/ECE/Physics 5+ years in analog domain within the semiconductor industry Expertise in Cadence tools (Virtuoso) Strong understanding of analog circuit design and simulations Excellent communication, coordination, and problem-solving skills Bonus: VerilogA, C coding

Position: Design Verification Engineer Work Location: Pune, India (Hybrid) Contract Duration: 10 Months Experience: 7+ Years Job Description: 7+ years of design verification experience. MS (or higher) in EE/EC/ECC Engineering. Strong background in Pre-Silicon DV. Experience in verification of IPs and/or SoCs. Must have strong System Verilog and UVM/OVM experience. Hands-on experience with: AMBA protocols PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC Good understanding of computer architecture and verification fundamentals. Experience in low-power simulation, UPF setup, and debug. Scripting skills: Perl, Unix Shell, etc. Exposure to assembly/C language diagnostics and assertion coverage. Excellent communication skills.

Job Description: The role involves validation and coordination of QA activities for WiFi testing. Responsibilities include developing, reviewing, and modifying test plans, failure debugging, customer use-case execution, and automation scripting. Key Skills Required: Strong understanding of WiFi protocols 802.11 a/b/g/n/ac/ax/e/w Knowledge in WLAN Security (WPA2/WPA3, EAP Types, Enterprise Security) Proficient in tools: Omnipeek, Wireshark, iperf, Chariot, supplicant, hostapd, TCPdump, logcat OS: Linux, Windows, RTOS, Android Test plan execution, testbed setup Scripting: Python, TCL, Perl Knowledge on regulatory/Wi-Fi alliance certifications is an added plus

We are hiring an experienced Analog Layout Engineer to join a high-performance team working on advanced node technologies. This is a great opportunity to work with a global leader in semiconductor technology. Location: Bangalore Experience: 8 10 Years Employment Type: [Contract] Key Responsibilities: Handle block-level and top-level analog layout. Work on matching techniques, layout parasitics, and advanced layout methodologies. Work independently and collaboratively in a cross-functional team. Ensure quality layout delivery meeting DRC, LVS, and reliability checks. Required Skills: Solid understanding of analog layout fundamentals and design methodologies. Proficiency in 28nm, 22nm, and 16ff technology nodes. Strong experience with Cadence tools (Virtuoso, Assura, Calibre, etc.). Good team player with excellent communication skills.

Job Description: We are looking for a highly motivated Mixed-Signal Design Verification Engineer with 3+ years of experience in analog/mixed-signal verification. The ideal candidate should possess strong fundamentals in analog and digital design processes, along with hands-on experience in mixed-signal modeling and testbench setup. Responsibilities: Develop and maintain mixed-signal testbenches from scratch Write and manage Analog Mixed Signal models using VerilogAMS and real number modeling Debug mixed-signal simulations and analyze waveform results Utilize Synopsys tools (CustomSim/Primesim XA, Waveview) and Cadence Spectre environment Automate workflows using Unix shell scripting and Python Desired Skills: Strong knowledge of analog building blocks and top-level integration Expertise in mixed-signal simulation performance optimization Proficient in Unix/Linux environments Strong scripting and automation capabilities Excellent communication and problem-solving skills

We are hiring for a contract position with a leading client in the Wireless DSP domain. The role involves working on cutting-edge ML-based algorithms and wireless technologies. Location: Pune (Onsite) Duration: 4 Months Contract (Extendable) Experience: 3+ Years Key Responsibilities: Develop and deploy ML algorithms for wireless applications Collect training data in real-world setups (cabled/OTA) Perform model tuning and simulations Collaborate on efficient hardware implementations Required Skills: Python/MATLAB for ML model development Experience with TensorFlow/PyTorch Knowledge of wireless communication and signal processing

We are hiring a dynamic Community Manager to drive academic engagement initiatives and organize impactful events such as webinars, workshops, and hackathons. If you're passionate about community building in the tech education space, apply today! Key Responsibilities: Build and grow a vibrant community of students, faculty, and developers. Plan and execute educational events and contests. Manage customer requests and ensure smooth delivery of Arm Education offerings. Track engagement metrics and improve program delivery through feedback. Collaborate on outreach and marketing efforts. Key Skills: Community Engagement Event Management Education Program Management Public Speaking Stakeholder Communication

We are looking for a Supply Chain Planner I with strong experience in STPI documentation, Customs compliance, Import/Export operations, and logistics. Experience Required: 3 to 6 years Key Responsibilities: Import/export clearance, STPI documentation STPI inward/outward process management CHA coordination, MIS, E-way bill, CHIMS MPR, APR, FORM A reporting Audit support and policy compliance Must-Have Skills: STPI/Customs regulation knowledge SAP, Excel, Word, PowerPoint proficiency

Job Description: We are hiring Verification Engineers with expertise in SoC and IP verification for a 1-year contract role in Bangalore. Key Responsibilities: Develop C-based test cases and perform Subsystem/SoC verification Conduct IP verification using UVM methodology Handle complete verification flow planning, testbench implementation, and coverage closure – Debug and resolve issues efficiently – Work on ARM-based designs and protocols (AMBA APB, AXI, CHI) – Port peripheral driver software for SoC test cases – Perform GLS, DFT/DFD, and Power Aware verification Desired Candidate Profile: – Experience: 3–5 years (Mid-Level) / 5+ years (Senior-Level) – Contract Duration: 1 year – Location: Bangalore (Onsite) – Notice Period: Immediate to 15 days preferred

Job Description • M emory layout engineer. • Experience Level 3 to 8 Years ( Mid-Level Role) Responsibilities: As Memory Layout Engineer, we will work on developing memory compilers layouts and memory Fast Cache instances layouts for our next generation Cores achieving outstanding PPA. Required Skills and Experience : We Prefer graduate or postgraduate from a University or Engineering School, in Electronic Engineering or equivalent Engineering Degree. We expect you to have basic understanding of CMOS Transistors, their behaviors. We expect some basic understanding of CMOS logic design and layout. Understanding of Power versus Performance versus Area trade-offs in typical CMOS design. You have an engineering demeanor and Passion for Circuit layouts. Expected to have good interpersonal skills. Capable of creating high quality design rule driven layout Able to review schematics with engineering and propose changes based on layout implications. Exploring possible floor planning options and proposing improvements Minimum 5Yrs of experience in SRAM / memory layouts creation and backend verifications including EMIR analysis. Nice To Have Skills and Experience : You know basic scripting languages, e.g. Perl/skill. Some Experience of working on Cadence or Synopsys flows.

We are hiring for the position of EDA DevOps Automation & Analyst with 5+ years of experience in EDA license management, automation scripting, and support for semiconductor engineering environments. --- Key Skills: Flexlm, RLM, FlexNet Manager, Python Scripting, Linux Administration, Semiconductor, EDA Automation --- Roles & Responsibilities Manage and automate EDA license usage (FlexNet, Flexlm, RLM). Develop Python/Shell scripts for automation and monitoring. Provide tech support to global engineering teams. Work in Agile teams and ensure license asset optimization. Report generation, license trend analysis, and root cause investigation. --- Desired Candidate Profile 5+ years of relevant experience in EDA tools & licensing. Strong hands-on in Linux/Unix and scripting languages. Experience working in global R&D teams. Good communication and analytical thinking. Familiar with Agile/Scrum and ITIL is a plus.

We are looking for a Software Testing Engineer with solid experience in JavaCard applet and smart card technologies. This is a high-priority position, and candidates with deep understanding of JavaCard testing will be shortlisted on priority. Must-Have Skills: Strong experience in JavaCard Applet Testing GlobalPlatform, ISO 7816/14443 Smart card and secure element testing Hands-on with JavaCard technology Strong testing and debugging skills Educational Qualification: B.E./B.Tech or M.E./M.Tech in Computer Science / Electrical / relevant fields