Job
Description
Job Area: Engineering Group, Engineering Group > Hardware Engineering
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications:
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Job Overview:This position centers on floor-planning expertise at both block and top levels for industry-leading CPU core designs, with a strong emphasis on scalability and achieving aggressive Power, Performance, and Area (PPA) targets. The role involves working on cutting-edge technology nodes and applying advanced physical design techniques to push the boundaries of CPU performance and efficiency.Preferred Qualifications:Masters degree in Electrical/Computer Engineering8+ years of direct top level floor-planning large and high frequency IP experienceIn depth end to end experience from RTL2GDS, taping out at least 5 complex designsDirect hands-on experience with bus/pin/repeater planning for entire IPKey responsibilities include:
Driving floorplan architecture and optimization in collaboration with PD/RTL teams to maximize PPAEngaging in cross-functional collaboration with Physical design, timing, power, and packaging teams to ensure holistic design convergencePartnering with EDA tool vendors and internal CAD teams to develop and enhance automation flows and methodologies for improved design efficiencyMaking strategic trade-offs in design decisions to achieve optimal PPA outcomes while maintaining schedule and quality targetsEnd to End Physical verification closure for subsystem.The ideal candidate will have/demonstrate the following:
Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, big and high speed designsExperience with physical synthesis and implementation tools - Cadence Innovus/Genus and Synopsys Fusion Compiler.Must have good knowledge of static timing analysis, reliability, and power analysisStrong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designsAbility to think outside the box for innovative solutions to improve power and eliminate performance bottlenecksStrong understanding of CPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performanceSolid working knowledge of scripting skills including tcl, perl or pythonExcellent communication skills and collaborating in a team environment is a mustExcellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues. (Mostly Working on Calibre tool)Experience in IO, Bump planning and RDL routing Strategy.Preferred
Skills:Clock implementation, power delivery network design choices, process technology, prior experience in flow and methodology development, block closureClose interaction with design and architecture teams to influence scalable floor-plans and optimal bus/pin/repeater planning for entire IP and its sub-blocksHands on experience with Synthesis, DFT, Place and Route, Timing and Reliability SignoffHands on experience working with very complex designs that push the envelope of Power, Performance and AreaHands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageousHands on experience on Innovus/FC tool based scripting & python/TCL scripting.Prior experience in flow and methodology development is an advantageExcellent debug and analytical skills and demonstrated successes in floor-planning large IP and high frequency designsAbility to drive Physical Implementation teams in Floor-planning and work well in a collaborative environment with multi-disciplined teamsMinimum Qualifications:
Bachelors degree in Electrical/Computer Engineering8+ years of direct top level floor-planning large and high frequency IP experience which includes bus/pin/repeater planning at the top levelStrong background in VLSI design, physical implementation and scriptingStrong background and experience working with industry standard Synthesis and Place and Route tools including Signoff toolsHands on experience taping out designs in sub-micron technology node design Expect strong self-motivation and time management skillsApplicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm's toll-free number found .
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
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