180 Power Management Jobs - Page 3

1. Engineer with 5+ of experience in embedded Linux/Linux application/driver/kernel development. 2. Strong C/C++ development skills with a good understanding of object-oriented design. 3. Experience dealing with Linux community and Open Source contribution a plus 4. Experience with any one of the domain (Multi Media, Power management, Display technology, OpenGL) 5. Experience with Audio sub-system, Audio drivers s, frameworks and ALSA SOC(ASOC), Audio protocols like I2S, Proficient in yocto development. 6. Good working experience with IPC, DMA driver development. 7. Strong background in embedded systems development 8. System knowledge, System Debugging 9. Experience with kernel mode driver programming in Linux 10. Linux Device driver programming experience in Linux Kernel and Drivers. 11. Work in both an individual and team member environment 12. Excellent problem solving and debugging skills of the building blocks. 13. Kernel bug fixes and upstreaming 14. Strong written and verbal communication skills 15. Self-motivated, should be able to take lead in mastering new technologies Good to have: 16. Expertise with CAR Framework. 17. Automotive experience Note: 1. Need only BE/B Tech and Master degree profiles. 2. Pure Work from Office 3. Good Communication Skill

We believe that you are someone with genuine interest in design and development of electrical and electronic functions. You are someone that is willing to work hands -on in applying the knowledge and experimenting You will have the opportunity to collaborate cross functionally in a team to specify the behavior and develop applications that help to optimize electrical consumption, increase battery life and save fuel at vehicle. Working in a team, you build use case scenarios, develop application with System thinking risk management capability. We believe you are Creative and have the mindset to constantly learn and improve to have the best solutions for our customers. You have a positive outlook and collaborative mindset. What s in it for you Specify functions for optimizing the electrical consumption of the Vehicle which will increase the battery lifetime. Involved in the function roadmap reviews. At the truck, troubleshooting and experiencing the features. Validating the use case scenarios for the functions Talking with your colleagues around the world. Responsibilities Analyse project scope and technical needs and lead the discussion with End-User Function (EUF) Teams to review the Application Network (ANW) needs. Support in creating test cases and collaborate with different stakeholders to execute all required testing for the Application Networks. Configure ECUs for the Application Networks Added, Modified, or removed and release files (.arxml) in artifactory. Represent the Power Management Infrastructure Team in related forums and be responsible for component development in collaboration with suppliers and global counterparts. Secure cross-functional and business anchoring. Lead critical issues problem-solving in collaboration with the EUFs and within the team. Capitalize knowledge around protection and distribution components. Contribute to continuous improvement on tools, work methods and the development process. Strategy responsibility extended to deliver execute a Product Roadmap of the area for a few complex ANWs or multiple Straight Forward ANWs. Competencies BE/B.Tech., ME/M.Tech in Electrical-, Electronics Engg. (or similar) with 8 Years or more of experience in Automotive Electrical domain. Leading on complex group tasks/projects and actively developing team members. Role model of cutting edge thinking and an established contributor to lifelong learning within the TD/BA as a master trainer, coach and/or mentor. Solid T-shaped profile with definable expert knowledge within broad-based all-round toolkit. Demonstrable influencer within the Volvo Group network. Clear articulation of how he/she is creating value to the respective TD/BA beyond their part of the organization. Good understanding on AUTOSAR ECU configurations, VECTOR MICROSAR, and the software development cycle. Good exposure to with software integration, debugging, testing protocols, and configuration management. Good understanding of testing protocols, test studio, PN tool etc. Good exposure in continuous integration/continuous deployment practices.

Job Title: Android Platform Developer Location: Bangalore Experience: 3-9 Years Job Description: We are seeking a skilled Android Platform Developer with a strong background in C++ programming and hands-on experience in Power State Management . You will be responsible for developing and optimizing Android system-level components to ensure efficient power consumption across the platform. Required Skills: Strong proficiency in C/C++ and Android platform internals Solid understanding of Android Power Management Framework (PMF) Experience working with Android HAL , AOSP, and low-level system layers Familiarity with Linux kernel concepts, power drivers, and device tree Debugging tools: ADB, systrace, perf, ftrace, logcat Strong problem-solving and performance profiling skills

Lead and manage the analog and RF layout team for high-performance semiconductor products Oversee layout planning, floorplanning, and routing for RF, analog, and mixed-signal IC designs. Work closely with circuit design teams to optimize layouts for performance, area, and manufacturability. Ensure DFM (Design for Manufacturability), DRC (Design Rule Check), LVS (Layout vs. Schematic), and EM (Electromigration) compliance. Drive automation and layout methodologies to improve efficiency and quality. Collaborate with foundry partners for process design kits (PDKs), layout guidelines, and tape-out requirements. Provide technical mentorship to layout engineers and review critical blocks. Own full-chip layout integration and support post-layout simulations. Qualifications: 8+ years of experience in analog/mixed-signal/RF IC layout. Strong expertise in FinFET (e.g., 16nm, 7nm, 5nm) or advanced CMOS nodes. Hands-on experience with Cadence Virtuoso, Calibre DRC/LVS, and Mentor Graphics tools. Knowledge of high-frequency layout techniques, parasitic-aware layout design, and shielding strategies. Experience in power management, high-speed SerDes, RF front-ends, or ADC/DAC layouts is a plus. Proven ability to lead teams, review layouts, and drive tape-out schedules. Strong understanding of wafer-level packaging and chip integration. Excellent problem-solving and communication skills.

SE NIOR SILICON DESIGN ENGINEER THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the Power Delivery convergence team , you will work closely with the architecture, physical design teams, package, board, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work on full chip SoC electrical signoff convergence with physical design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Work on full chip IR/EM convergence on multiple ASICs across different technology nodes. Work closely with architecture, power management, package and floorplan team to come up with robust power delivery design. Work with RTL and PD team in coming up with the low power and UPF specification for the SoC. Work closely with CAD team to come up with new flows and methodologies in the power integrity domain. PREFERRED SKILLSET: 5+ years of professional experience in the industry in power integrity domains Good knowledge of Power delivery and power integrity flows Hands on experience on industry standard tools especially Redhawk based power integrity analysis Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

SE NIOR SILICON DESIGN ENGINEER THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the Power Delivery convergence team , you will work closely with the architecture, physical design teams, package, board, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work on full chip SoC electrical signoff convergence with physical design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Work on full chip IR/EM convergence on multiple ASICs across different technology nodes. Work closely with architecture, power management, package and floorplan team to come up with robust power delivery design. Work with RTL and PD team in coming up with the low power and UPF specification for the SoC. Work closely with CAD team to come up with new flows and methodologies in the power integrity domain. PREFERRED SKILLSET: 6+ years of professional experience in the industry in power integrity domains Good knowledge of Power delivery and power integrity flows Hands on experience on industry standard tools especially Redhawk based power integrity analysis Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

MTS SILICON DESIGN ENGINEER THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the Power Delivery convergence team , you will work closely with the architecture, physical design teams, package, board, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work on full chip SoC low power convergence and power analysis. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Work closely with architecture, RTL, PD and power management teams for coming up with the chip low power intent and UPF. Work with architecture, RTL and PD team for chip level power estimation, analysis and optimization Work closely with CAD team to come up with new flows and methodologies in the power analyisis and low power domains. PREFERRED SKILLSET: 8+ years of professional experience in the industry in low power and power estimation domains. Hands on experience on industry standard tools especially PTPX, Power Artitst, VCLP and CLP. Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

Senior Android BSP Engineer - Device Driver A highly skilled Senior Android BSP Engineer is sought to develop, port, and maintain Android Board Support Packages (BSPs) for target devices. This role involves deep dives into HAL development, Linux kernel customization, and device driver porting, with a strong focus on GPU integration and performance optimization. You'll be instrumental in conducting root cause analysis and collaborating with cross-functional teams to ensure seamless hardware-software integration. Key Responsibilities Android BSP development skills will be applied to develop, port, and maintain Android BSP for target devices. HAL module development and maintenance for various hardware components are essential. Linux kernel customization for specific hardware requirements is a key responsibility. Device driver porting for USB, I2C, and other peripherals will be performed. GPU integration capabilities , including OpenGL, Vulkan, video acceleration, and display, are required. In-depth root cause analysis for issues related to Android BSP, HAL, kernel, and GPU will be conducted. System performance and resource utilization optimization are critical. Collaboration with cross-functional teams is vital to ensure seamless integration. Clear and concise technical documentation creation is expected. Technical Skill Requirements Strong proficiency in Android framework and HAL development is mandatory. In-depth understanding of Linux kernel architecture and device driver programming is essential. Experience with device driver development for USB, I2C, and other peripherals is required. Knowledge of GPU architectures and APIs (OpenGL, Vulkan) is necessary. Experience with Android performance optimization and power management is a must. Strong problem-solving and debugging skills are critical. Excellent communication and collaboration skills are vital. Proficiency in scripting languages (e.g., Python, Bash) is required. General Requirements Employment Type: This is a Full-Time, Permanent position. Notice Period: Immediate - 15 Days.

Lattice is seeking candidates for the position of Staff Software Development Engineer in FPGA place and route. This is a full-time position located in Pune, India. The successful candidate will join a team designing and developing Lattice FPGA implementation software tools. The candidate will contribute to delivering software solution for Lattice FPGA development with emphasis on Lattice synthesis mapper tool. The candidate is expected to be an expert in FPGA synthesis core engine and technological mapping with knowledge on how to achieve optimal solution for a given architecture and be able to support next generation FPGA with best result in Fmax, Area, Runtime as we'll as memory utilization The candidate will team up with other synthesis/mapper developers and develop synthesis mapping engine for various FPGA products. The responsibility also includes customer support, new software feature support as we'll as QoR improvement. The candidate is expected to maintain existing software products and interact with other teams to facilitate a value-added solution too. Accountabilities: Develop logic synthesis/mapper tool for Lattice FPGA products. Synthesize logic designs from Verilog/VHDL RTL to structural netlist. Improve synthesis/mapper engine QoR. Create test designs with test benches to verify implementation and ensure high quality. Qualifications: BS/MS/PhD in Electrical Engineering or Computer Science or Computer Engineering. Proficient with C/C++, Verilog/VHDL, logic design, Tcl and shell scripts. Strong background and experience in data structures and algorithms. Experience of logic design and EDA software is a must. Experience of logic optimization and technology mapping development is required. Experience of FPGA tool development is preferred. Strong written and verbal communication skills, and collaboration skill. Experience of multi-processing development is a plus. Solid understanding in FPGA architectures is a plus. 10+ years of experience in logic synthesis development in FPGA or ASIC domains

Embedded Linux Kernel Developer: 1. Engineer with 5+ of experience in embedded Linux/Linux application/driver/kernel development. 2. Strong C/C++ development skills with a good understanding of object-oriented design. 3. Experience dealing with Linux community and Open Source contribution a plus 4. Experience with any one of the domain (Multi Media, Power management, Display technology, OpenGL) 5. Experience with Audio sub-system, Audio driverss, frameworks and ALSA SOC(ASOC), Audio protocols like I2S, Proficient in yocto development. 6. Good working experience with IPC, DMA driver development. 7. Strong background in embedded systems development 8. System knowledge, System Debugging 9. Experience with kernel mode driver programming in Linux 10. Linux Device driver programming experience in Linux Kernel and Drivers. 11. Work in both an individual and team member environment 12. Excellent problem solving and debugging skills of the building blocks. 13. Kernel bug fixes and upstreaming 14. Strong written and verbal communication skills 15. Self-motivated, should be able to take lead in mastering new technologies Good to have: 16. Expertise with CAR Framework. 17. Automotive experience

Experience: - 5 to 12 years experience in hands on firmware development. - Strong with C language programming - Good understanding and experience with BIOS, power management and PCIe - Strong knowledge of UEFI BIOS, ACPI. AGESA knowledge is a big plus - Strong knowledge of platform BIOS development - Good knowledge SoC power management CPU/Device power states, hot-plug etc - Firmware development & release process understanding - Prior experience working with firmware design & development - OS/ Drivers/Software stack understanding is a plus - Excellent communication and articulation skills Academic credentials: - Bachelors degree in computer science engineering from reputed college - Masters degree from reputed university is a big plus.

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: Qualcomm is building on its core strengths in wireless and compute technologies and is in the middle of the biggest technology revolution in the Automotive space. While Qualcomm has pioneered connected car technologies for over a decade, it is now playing a critical role in the evolution of Automotive Infotainment, Telematics, ADAS/Autonomous Driving & its supporting technologies. We are investing in several bleeding edge technologies such 5G, Cellular V2X, Computer Vision, AI/Deep Learning etc., and are working closely with global Automakers/Tier-1s, standards bodies, consortiums and operators on pushing the boundaries. Qualcomm Automotive Compute Platform Team is looking for senior technical lead who can make difference on many technology forefronts in Automotive space, join our growing multisite engineering organization. Responsibilities will include but not limited to: Leading multiple teams' architects, technical leads, compute hardware and software engineers in optimization efforts and driving ASPICE, ASIL Compliance. Defining strategic roadmap and delivering to the vision of best-in-class service capabilities of Qualcomms Automotive Engineering teams. Driving robust processes for requirements specifications, prioritization and solution development that supports a larger Automotive Global team. This includes active management of stakeholder alignment of capabilities, product roadmap and delivery plans. Defining and implementing Automotive use cases, driving system validation methodologies and robust release management processes Minimum Qualification: - 13+ Years of Experience in the embedded domain to design, develop and support software solutions on multi-core ARM/CPUs, Strong C/C++ programming skills. Embedded Platforms experience including low-level drivers and firmware, kernel and user-space components. Design and development of software for heterogeneous compute platforms consisting of ARMs, GPUs, DSPs, and specialized hardware accelerators in an embedded SoC systems with J-TAG or ICE debuggers; Experience in real-time SW development for embedded products. Hands on experience in leading medium to large technical teams. Hands on experience of driver development on any RTOS Handson Experience in Autosar software development Detailed understanding SoC hardware blocks - Clocks, PLLs, GPIO, Interrupt Controllers (GIC), Peripherals (SPI/I2C/PCIE/CAN/Ethernet/USB/UFS), power management Experience in Linux kernel architecture, device drivers and memory management. Preferred Qualifications: - Motivated self-starter with excellent verbal and written communication skills, demonstrated ability to work with engineers/partners/customers across different geographies. Demonstrated experience working with senior management in a corporate environment. Demonstrated experience in business process streamlining and transformation that includes disciplined approach to digitized services enabling. Hands-on technical lead who is not hesitant to dig into the details where needed to get first-hand knowledge of the issues and play an active and personal role in steering team success. Experience in ISO26262/functional safety is highly recommended. Exposure to one or more of below technology areas is a plus:- Multiprocessor Architecture, ARM processors, caching, interrupts, etc., Virtualization technologies across CPU and MM hardware accelerators Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Software Engineering or related work experience. 3+ years of work experience with Programming Language such as C, C++, Java, Python, etc.

* Lead the core level pre-silicon functional & performance verification for our next -generation IBM POWER processor core systems offering.* Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment.* Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU.* Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments.* Develop verification test plan for both functional and performance verification including the estimation for coverage closure.* Support higher level core/system simulation environment.* Participate in post silicon lab bring-up and validation of the Hardware.* Lead , guide ,mentor a team of engineers and represent them at global forums.* Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement.* Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. * Hands-on on Power Management domain Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 4 years or more experience in functional verification of processors, demonstrating a deep understanding of power management unit verification.* Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. * Experience with high frequency, instruction pipeline designs* At least 1 generation of Processor Core silicon bring up experience* In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs)* Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design* Proficiency in C++, Python scripting or similar object oriented programming languages.2:37Y Annapurna Bharathi Preferred technical and professional experience * Knowledge of instruction dispatch and Arithmetic units.* Knowledge of test generation tools and working with ISA reference model.* Experience with translating ISA specifications to testplan.* Knowledge of verification principles and coverage.* Understanding of Agile development processes. * Experience with DevOps design methodologies and tools.

Skills SOC Physical Design Experience 3 to 15 years Job Location Bangalore, Hyderabad, Noida, and Coimbatore. Job Description: Location: Bangalore, Hyderabad, Noida, and Coimbatore. Skills: Soc level floorplanning, partitioning, timing budget generations, power planning, SOC PnR, CTS, block integration Handling timing closure of high frequency blocks. Expertise in signoff closure Timing with SI and OCV, Power, IR and physical verification at both block and chip level. Understanding constraints and fixing techniques. Experience in physical verification Understanding SI prevention, fixing methodology and implementation. Proficient in Synopsys ICC or Cadence or Mentor Olympus and Atoptech tool set. Experience in Design Automation and UNIX system. Experience in Tcl/ PERL is a plus. Primary Skills: Able to handle Soc PNR activities , SOC timing closure and SOC physical verification Secondary Skills: Able to handle SOC Synthesis, SOC IR drop, SOC Lec, SOC CLP

Job Summary An accomplished engineering leader responsible for owning the architecture and high-level design of subsystems within embedded Linux platforms. Brings over 8 years of experience in kernel internals, driver development, and post-silicon bring-up across ARM/x86 architectures. Plays a strategic role in solution formulation, customer engagement, test strategy creation, and trade-off decisions. Acts as a domain authority in system performance, power management, connectivity, and Android integration across carrier-grade platforms. Key Responsibilities Architect subsystems to meet both functional and non-functional requirements (performance, scalability, security, power efficiency). Lead design reviews, define test strategies, and review implementation against system objectives. Evaluate and recommend the best tools, test languages, and validation methodologies for post-silicon workflows. Participate in RFPs, estimation, and solution building for new proposals and existing account expansions. Serve as the technical interface with customers for change requests, roadmap discussions, and performance tuning. Own documentation and guide development from design documents through delivery. Contribute to technical reviews, customer presentations, and strategic engineering decisions. Support team capability building by sharing expertise, mentoring, and driving innovation across the organization. Maintain deep awareness of emerging trends, tools, and advancements in embedded platforms and silicon validation. Education & Experience Qualification: B.E./B.Tech/MCA or equivalent Experience: 8+ years in embedded Linux kernel/device driver design, test architecture, and system integration Technical Competencies Kernel & Driver Development: Linux kernel configuration, board bring-up, device tree, interrupt handling, memory management Driver porting/customization for USB, Ethernet, Media, Connectivity, and Android HALs Post-Silicon Expertise: System validation, test automation, performance tuning, and test coverage strategy Debug tools: Lauterbach, JTAG, trace analyzers Programming & Tools: Languages: C (mandatory), Bash, basic Python scripting (optional) Tools: Git, Gerrit, Makefile-based build systems Target Platforms: Embedded Linux on ARM, Intel Atom/x86 Specializations: Power Management, Security, Data Protocols, Carrier-grade optimization, Android integration

Job Summary An accomplished engineering leader responsible for owning the architecture and high-level design of subsystems within embedded Linux platforms. Brings over 8 years of experience in kernel internals, driver development, and post-silicon bring-up across ARM/x86 architectures. Plays a strategic role in solution formulation, customer engagement, test strategy creation, and trade-off decisions. Acts as a domain authority in system performance, power management, connectivity, and Android integration across carrier-grade platforms. Key Responsibilities Architect subsystems to meet both functional and non-functional requirements (performance, scalability, security, power efficiency). Lead design reviews, define test strategies, and review implementation against system objectives. Evaluate and recommend the best tools, test languages, and validation methodologies for post-silicon workflows. Participate in RFPs, estimation, and solution building for new proposals and existing account expansions. Serve as the technical interface with customers for change requests, roadmap discussions, and performance tuning. Own documentation and guide development from design documents through delivery. Contribute to technical reviews, customer presentations, and strategic engineering decisions. Support team capability building by sharing expertise, mentoring, and driving innovation across the organization. Maintain deep awareness of emerging trends, tools, and advancements in embedded platforms and silicon validation. Education & Experience Qualification: B.E./B.Tech/MCA or equivalent Experience: 8+ years in embedded Linux kernel/device driver design, test architecture, and system integration Technical Competencies Kernel & Driver Development: Linux kernel configuration, board bring-up, device tree, interrupt handling, memory management Driver porting/customization for USB, Ethernet, Media, Connectivity, and Android HALs Post-Silicon Expertise: System validation, test automation, performance tuning, and test coverage strategy Debug tools: Lauterbach, JTAG, trace analyzers Programming & Tools: Languages: C (mandatory), Bash, basic Python scripting (optional) Tools: Git, Gerrit, Makefile-based build systems Target Platforms: Embedded Linux on ARM, Intel Atom/x86 Specializations: Power Management, Security, Data Protocols, Carrier-grade optimization, Android integration

Job Summary An accomplished engineering leader responsible for owning the architecture and high-level design of subsystems within embedded Linux platforms. Brings over 8 years of experience in kernel internals, driver development, and post-silicon bring-up across ARM/x86 architectures. Plays a strategic role in solution formulation, customer engagement, test strategy creation, and trade-off decisions. Acts as a domain authority in system performance, power management, connectivity, and Android integration across carrier-grade platforms. Key Responsibilities Architect subsystems to meet both functional and non-functional requirements (performance, scalability, security, power efficiency). Lead design reviews, define test strategies, and review implementation against system objectives. Evaluate and recommend the best tools, test languages, and validation methodologies for post-silicon workflows. Participate in RFPs, estimation, and solution building for new proposals and existing account expansions. Serve as the technical interface with customers for change requests, roadmap discussions, and performance tuning. Own documentation and guide development from design documents through delivery. Contribute to technical reviews, customer presentations, and strategic engineering decisions. Support team capability building by sharing expertise, mentoring, and driving innovation across the organization. Maintain deep awareness of emerging trends, tools, and advancements in embedded platforms and silicon validation. Education & Experience Qualification: B.E./B.Tech/MCA or equivalent Experience: 8+ years in embedded Linux kernel/device driver design, test architecture, and system integration Technical Competencies Kernel & Driver Development: Linux kernel configuration, board bring-up, device tree, interrupt handling, memory management Driver porting/customization for USB, Ethernet, Media, Connectivity, and Android HALs Post-Silicon Expertise: System validation, test automation, performance tuning, and test coverage strategy Debug tools: Lauterbach, JTAG, trace analyzers Programming & Tools: Languages: C (mandatory), Bash, basic Python scripting (optional) Tools: Git, Gerrit, Makefile-based build systems Target Platforms: Embedded Linux on ARM, Intel Atom/x86 Specializations: Power Management, Security, Data Protocols, Carrier-grade optimization, Android integration

MSCI Services is looking for a Climate Data Specialist to join our Climate Data and Content Services team. This team is responsible for the research and assessment of carbon footprint and business initiatives related to climate change for approximately 14,000 companies globally. Our research focuses on climate-related metrics, including carbon emissions, energy performance, climate change targets and commitments, and other relevant sector-specific data, utilizing diverse sources like annual reports, sustainability reports, quantitative data feeds, and news publications. Your primary responsibility will be to contribute to the sector expertise of the team and support all our climate data integration efforts . You will support the quality of our climate dataset within your assigned sector and engage with internal and external stakeholders for a better understanding of methodology and data. Responsibilities: Procure and process information about globally listed companies, utilizing multiple sources such as lengthy annual reports, CSR reports, websites, quantitative data feeds, and web crawlers. Work with various types of information, including quantitative data and key performance indicators , covering topics like traditional financial risk, corporate governance, and sustainability. Perform different types of analysis, including rules-based, subjective analysis, and written summaries . Review and validate climate data provided by vendors and issuers . Address queries from internal and external users pertaining to Climate data , reconciling data challenges, training users on methodologies and processes, and maintaining process documentation. Work with a global team of researchers, data and IT specialists, and vendors to enhance and improve our research and assessment of companies carbon footprint, climate change targets and commitments, and climate change mitigation practices. Capture and transform climate data metrics into meaningful information/ratings/scores. Drive coverage and content expansion projects defined by the business. Update and refine industry assessment guides for data collectors and internal analysts. Design and implement process improvements and QA checks to ensure consistent data quality and efficiency. Contribute to working committees, projects, or perform other tasks as deemed necessary by the business. Qualifications: Bachelor's/Master's degree in finance, statistics, sustainability, environmental science, oil and gas engineering, or Power management . Knowledge of climate change issues and regulations , including carbon offsets, climate reporting standards (e.g., TCFD, ISSB), and frameworks (e.g., IPCC, UNFCCC). Background in GHG assessments, GRI reporting, or environmental impact assessments , and/or working experience in Energy (Oil & Gas), Power, Industrials, or Transport sectors. Experience in data visualization tools is desirable (Power BI/Tableau/Python/SQL). Ability to articulate and communicate complex concepts with ease. Fast learner and strong logical thinker. Ability to work under minimal supervision. Anticipate problems and opportunities, and adapt to new challenges. Ability to work with multiple stakeholders in a collaborative global team environment. What we offer you: Transparent compensation schemes and comprehensive employee benefits , tailored to your needs, ensuring your financial security, health, and overall well-being. Flexible working arrangements , advanced technology, and collaborative workspaces. A culture of high performance and innovation where we experiment with new ideas and take responsibility for achieving results. A global network of talented colleagues who inspire, support, and share their expertise to innovate and deliver for our clients. Global Orientation program to kickstart your journey, followed by access to our Learning@MSCI platform, LinkedIn Learning Pro, and tailored learning opportunities for ongoing skills development. Multi-directional career paths that offer professional growth and development through new challenges, internal mobility, and expanded roles. We actively nurture an environment that builds a sense of inclusion, belonging, and connection , including eight Employee Resource Groups: All Abilities, Asian Support Network, Black Leadership Network, Climate Action Network, Hola! MSCI, Pride & Allies, Women in Tech, and Women's Leadership Forum.

Kafka, IBM APIC & Data Power Administration : Job Summary: We are seeking a highly skilled Middleware Support Engineer to join our dynamic team. The ideal candidate will have extensive experience in supporting and managing middleware technologies including Kafka, IBM API Connect (APIC), IBM Data Power management. The role involves ensuring the smooth operation, maintenance, and troubleshooting of these systems to support our business operations. Key Responsibilities: Provide technical support and administration for Kafka, IBM API Connect (APIC), IBM Data Power management. Monitor system performance, identify issues, and implement solutions to ensure optimal performance and reliability. Collaborate with development teams to support integration and deployment of middleware solutions. Perform regular system maintenance, upgrades, and patches. Develop and maintain documentation for system configurations, processes, and procedures. Troubleshoot and resolve technical issues related to middleware technologies. Ensure compliance with security policies and procedures. Provide on-call support as needed to address critical issues.Ensure adherence to integration best practices and standards. Document integration processes and solutions for future reference. Good to have knowledge on python.

Description & Requirements Min 5 Years of Experience in Python ; Strong background in developing application and related Frameworks [PyQt ,Tkinter ,Pytest] . Adv Python for Data Analysis is advantage : Skilled resource for Trouble shoots ,Debug ,Optimize the code. Should be aware of the project life cycle (SDLC & STLC) Should be aware of the defect flow and defect management Should have scripting knowledge - in both test development and execution using any automation tool. Should be aware of integration and system testing concepts and methods and tools Automotive Infotainment knowledge in features like Vehicle, CAN, Diagnostics, Power management. Should have managed a small team of atleast 4-5 members. Early onboarding Important Notice: Recruitment Scams Please be aware that HARMAN recruiters will always communicate with you from an @harman.com email address. We will never ask for payments, banking, credit card, personal financial information or access to your LinkedIn/email account during the screening, interview, or recruitment process. If you are asked for . HARMAN is proud to be an Equal Opportunity / Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, religion, color, national origin, gender (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. Apply

THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the Power Delivery convergence team , you will work closely with the architecture, physical design teams, package, board, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work on full chip SoC electrical signoff convergence with physical design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Drive full chip IR/EM convergence on multiple ASICs across different technology nodes. Work closely with architecture, power management, package and floorplan team to come up with robust power delivery design. Work with RTL and PD team in coming up with the low power and UPF specification for the SoC. Work closely with CAD team to come up with new flows and methodologies in the power integrity domain. PREFERRED SKILLSET: 18+ years of professional experience in the industry with a proven track record of successfully delivering complex SoCs Sound knowledge of Power delivery and power integrity domains Hands on experience on industry standard tools especially Redhawk based power integrity analysis Should have lead IR/EM convergence on multiple full chip SoCs Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Dear All, Looking for a Power System Reliability Manager/Sr Manager for a Metals & Mining organization in Navi Mumbai. Any candidate with 12-15 yrs of experience with relevant expertise can apply for this position.

About the Company : MIKO is an advanced consumer robotics innovation lab focused on the mission of Bringing Robotics and AI to every consumer home. Founded by young and dynamic entrepreneurs from IIT Bombay, Miko is a global deep tech company with offices in US, UK, and India, and a customer base across 140+ countries. Focused on taking Robotics and AI to every consumer home, Miko is the first of its kind & content on subscription& hardware platform for kids powered by patented technology. Website: https://in.miko.ai/ Key responsibilities: To Analyze domain specific technical or low level requirement and modification as per end customer or system requirement. Perform software testing including unit, functional and system level requirement including manual and automated Write firmware for the specific System module. Write integration Code and make push requests to the git repository. Performs code peer-review following coding guidelines and static code analysis Troubleshoots software problems of limited difficulty. Documenting technical deliverables like software specifications, design document, code commenting, test cases and test report, * Release note etc. throughout the project life cycle. Follow defined process for software Development life cycle Provide technical support to Team and contribute towards their Growth Generate Reusable Code that can be contributed towards Code bank. Get hands on with new Technologies and Skill to keep yourself updated. Expertise / Skills : Excellent programming skills in C/C++ Experience 1+ years Working experience in bare metal, RTOS, and device driver development Linux board bring up and kernel level programming skills, device driver development End to end design and architecture level experience in Embedded and IoT based products Porting open source porting experience. Knowledge of ARM based various processors and microcontrollers Excellent analytical and problem-solving skills Excellent debugging skills and hands on with the coding Object oriented fundamentals and design Reading schematics, datasheets, technical reference manual and Silicon revision sheets Using tools like Logic Analyzer, DSO/CRO, Spectrum Analyzer. Used Confluence, JIRA, GIT, SVN, bit-bucket, etc. Experience of team leadership and/or project management in multi-cultural multi-disciplined team Good to have: Understanding of Android architecture and elements like AIDL, Binder, Lifecycle, System Services, Android Framework, and AOSP Knowledge of Cloud Platforms like AWS, AZURE or Google cloud Power Management for Low Power devices

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Function Qualcomm seeks candidates to help design reference designs and solutions for customers using Qualcomm hardware and software. The role involves working with the Customer Engineering team on product designs, supporting Qualcomm's platforms and applications, and collaborating with internal stakeholders. Responsibilities include creating reference designs, supporting hardware design sign-offs, system/PCB/chip-level debugging, and managing design collaterals to accelerate product development for customers. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Preferred Qualifications A strong understanding of Digital/baseband HW design and PCB design is required. Good troubleshooting skills with the ability to analyze and debug during board bring up (boot-up) are essential. An understanding of LDO/SMPS is essential, along with experience in power management for portable devices being advantageous. Solid knowledge in High-Speed digital interfaces, such as memory Bus I/F (UFS, eMMC, LPDDR, NAND), Display interfaces (parallel and serial, preferably MIPI DSI), Camera interfaces (parallel and serial, preferably MIPI CSI), High Speed peripherals (USB, SDC, PCIe, Ethernet), and Standard Peripheral interfaces (UART, SPI, I2C, JTAG, HDMI) are necessary. Experience with Digital HW/baseband systems and board-level design, as well as familiarity with Digital ASICs and system design, is important. Understanding of system-level clocking schemes, interface-level handshakes are necessary A strong understanding of mobile and consumer electronics products is needed. Hands-on experience with oscilloscopes, logic analyzers, test and measurement tools are required. Basic knowledge of ARM processors and experience with JTAG emulators, display drivers, and memory is preferable. Knowledge of multi-core system/inter-chip system design is advantageous. A strong understanding of PCB signal/power integrity is necessary Reviewing schematics and suggesting improvements is required. Experience with schematic entry is necessary; must have knowledge to review PCB layout in various CAD tools like Cadence Allegro, Siemens Mentor Graphics suite. Hands-on with PCB layout edit tools is advantageous Knowledge of multi-layer PCB designs, vias, and stack-up configuration is essential. The ability to interact with multi-geography customers and stakeholders is desired. Knowledge of prototyping platforms like Arduino and Raspberry Pi is beneficial. Coding skills with Python or C is advantageous. As a member of Qualcomm's Customer Engineering team, responsibilities include creating reference designs, chip and chipset documentation, reference schematics, and training materials for global customer support. Candidate will assist with hardware design reviews, respond to technical queries, and troubleshoot designs at the system, SoC, and PCB levels. A minimum of 3 years' relevant experience is required, along with skills in hardware, digital/high speed/power management, and Silicon validation. Keywords Board Design, Board bring up, UFS, LPDDR, NAND, eMMC, MIPI, USB, UART, SPI, I2C, Logic Analyzer, PADS, Allegro, LDO, SMPS, Clocks, Crystal, ARM processor, JTAG Job Function Qualcomm seeks candidates to help design reference designs and solutions for customers using Qualcomm hardware and software. The role involves working with the Customer Engineering team on product designs, supporting Qualcomm's platforms and applications, and collaborating with internal stakeholders. Responsibilities include creating reference designs, supporting hardware design sign-offs, system/PCB/chip-level debugging, and managing design collaterals to accelerate product development for customers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Title: PMIC Reference Board Design Engineer Location: Bangalore, India : The QCT PMIC Systems group has an opening for a PMIC Reference Board Design Engineer. This group owns PMIC PCB design guidelines for Qualcomm chipset-based phone design. This includes design and optimization of PMIC PCB Floorplan, Schematic, Layout, phone thermal solution and eBOM selection for test platforms and customer reference design and evaluation kits. Qualcomm PMIC hardware design typically consists of modules such as switch-mode power supplies and linear voltage regulators for a variety of cores and peripherals, battery chargers, low noise clocks, ADCs, user interfaces such as display, camera flash and haptics, Power-on and Reset hardware. Responsibilities: ** NOT A LAYOUT POSITION** Job responsibilities for this position include design of Qualcomm PMIC Reference Board design and evaluation kits and working closely with PMIC IC designers and Test HW platform teams for optimizing performance and cost on test hardware platforms. The engineer will develop PMIC PCB reference design consisting of schematics, PCB layout, eBOM selection, layout guidelines and specs (by working closely with CAD engineer) based on interaction with chipset architecture, chip design and test teams. Experience in Mentor PADs Logic and PADs Layout, DxDesigner and Expedition is desirable but not essential. The engineer is required to perform the required board level simulations (based on Power Integrity and Signal Integrity tools) to review and sign off on hardware designs developed by various test teams. The engineer will be responsible for characterizing and publishing performance and cost optimized reference BOM lists (power inductors, capacitors, third party components etc) based on component characterization and BOM reduction and optimization tests in lab. Skills/Experience: ** NOT A LAYOUT POSITION** Understanding and ability to apply electrical engineering concepts and circuit solving skills. Able to work with common lab test equipments (oscilloscope, spectrum analyzer, logic analyzer, network and impedance analyzer, etc.). Experience in Power Management (SMPS, LDO, battery chargers, Clocks, ADC) PCB design and component selection including CAD interface. Experience in high layer count multilayer boards (6/8/10 layers) preferred. Good understanding of common Signal and Power Integrity issues on test hardware and ability to identify and provide alternate solutions using Signal and Power Integrity simulators (eg. powerSI, SIWave, Ansys) is also a plus. It is important the candidate has ability to communicate technical understandings and project status clearly. Also important is the ability to organize effectively and document work thoroughly and follow required procedures and methodologies . Ability to contribute seamlessly as a member of the reference HW design team across multiple chipsets. Education: RequiredB.E/ M.Tech /MS with 1 to 7 years of relevant experience. Keywords PMIC Reference Board Design, Power Electronics, PCB Design, Power Delivery, Power Integrity