Design and develop RF and analog circuits such as LNAs, mixers, power amplifiers, VCOs, PLLs, and ADC/DACs. Perform system-level analysis to optimize RF performance parameters like gain, noise figure, linearity, and phase noise. Conduct circuit simulations using tools like Cadence Spectre, ADS, HFSS, Momentum, and EMX. Collaborate with layout engineers to ensure optimal floorplanning, parasitic extraction, and RF routing. Conduct post-layout verification and EM simulations for high-frequency designs. Participate in lab validation and characterization of fabricated ICs, debugging issues, and improving performance. Work closely with system architects and digital design teams for mixed-signal integration. Support product engineering and test development for production ramp-up. Qualifications: 2 to 5 years of experience in RF/analog IC design. Strong understanding of RF circuit design principles, including impedance matching, S-parameters, and nonlinearity analysis. Hands-on experience with Cadence Virtuoso, Spectre RF, ADS, HFSS, or similar EDA tools. Knowledge of CMOS/BiCMOS process technologies and parasitic-aware design methodologies. Experience in EM simulation and modeling of on-chip passives (inductors, transmission lines, baluns). Familiarity with RF lab equipment (network analyzers, spectrum analyzers, signal generators). Strong problem-solving skills and ability to work in a fast-paced startup environment. Excellent communication and teamwork skills.

Lead the design, development, and verification of RF and analog IC blocks, including LNAs, mixers, power amplifiers, PLLs, VCOs, and ADC/DACs. Drive system architecture decisions for RF front-end and transceiver designs. Guide and mentor junior engineers, ensuring high-quality design practices. Perform top-level integration, ensuring seamless connectivity and performance of RF, analog, and mixed-signal circuits. Oversee simulation, layout reviews, and post-layout verification, optimizing for performance and manufacturability. Collaborate with layout, test, and product engineering teams for silicon validation and characterization. Define and execute design methodologies for efficiency, robustness, and first-pass success. Work closely with customers and cross-functional teams to define product specifications and roadmaps. Provide technical leadership in tape-out planning, foundry interactions, and process node selection. Requirements: 7+ years of experience in RF/analog IC design, with a track record of silicon success. Strong understanding of RF system design principles, including impedance matching, noise figure optimization, and linearity. Expertise in Cadence Virtuoso, Spectre RF, ADS, HFSS, and EMX. Deep knowledge of CMOS/BiCMOS technologies and layout-aware design methodologies. Experience in full-chip integration and packaging considerations for RF ICs. Hands-on experience with RF lab characterization and debugging. Strong leadership, mentorship, and project management skills. Excellent communication and ability to work in a fast-paced startup environment.

Lead and manage the analog and RF layout team for high-performance semiconductor products Oversee layout planning, floorplanning, and routing for RF, analog, and mixed-signal IC designs. Work closely with circuit design teams to optimize layouts for performance, area, and manufacturability. Ensure DFM (Design for Manufacturability), DRC (Design Rule Check), LVS (Layout vs. Schematic), and EM (Electromigration) compliance. Drive automation and layout methodologies to improve efficiency and quality. Collaborate with foundry partners for process design kits (PDKs), layout guidelines, and tape-out requirements. Provide technical mentorship to layout engineers and review critical blocks. Own full-chip layout integration and support post-layout simulations. Qualifications: 8+ years of experience in analog/mixed-signal/RF IC layout. Strong expertise in FinFET (e.g., 16nm, 7nm, 5nm) or advanced CMOS nodes. Hands-on experience with Cadence Virtuoso, Calibre DRC/LVS, and Mentor Graphics tools. Knowledge of high-frequency layout techniques, parasitic-aware layout design, and shielding strategies. Experience in power management, high-speed SerDes, RF front-ends, or ADC/DAC layouts is a plus. Proven ability to lead teams, review layouts, and drive tape-out schedules. Strong understanding of wafer-level packaging and chip integration. Excellent problem-solving and communication skills.