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3.0 - 8.0 years

3 - 7 Lacs

Bengaluru

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As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6. Estimate the overall effort to develop the feature and close design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of work experience of one or more areas Power management Architecture/ microarchitecture/ Logic design – Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques. 1. Experience of working on Power Management designs handling Power/Performance States, Stop states of Core and Cache, Chip and System thermal management and power supply current over-limit management 2. Experience in working with research, architecture/ FW/ OS teams 3. Experience in low power logic design 4. Experience in working with verification, validation for design closure including test plan reviews, verification coverage 5. Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high- performance design and timing closure of high frequency designs 6. Experience in silicon bring-up

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3.0 - 8.0 years

3 - 7 Lacs

Bengaluru

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As a Hardware at , you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today s market. Your role and responsibilities As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6. Estimate the overall effort to develop the feature and close design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of work experience of one or more areas Power management Architecture/ microarchitecture/ Logic design - Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques. 1. Experience of working on Power Management designs handling Power/Performance States, Stop states of Core and Cache, Chip and System thermal management and power supply current over-limit management 2. Experience in working with research, architecture/ FW/ OS teams 3. Experience in low power logic design 4. Experience in working with verification, validation for design closure including test plan reviews, verification coverage 5. Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high- performance design and timing closure of high frequency designs 6. Experience in silicon bring-up ABOUT BUSINESS UNIT

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3.0 - 7.0 years

9 - 13 Lacs

Bengaluru

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Full PE product lifecycle ownership from concept to end of life with a focus on ensuring the delivery of the highest quality products to our end customers Definition of ATE test, qualification and manufacturing plans Product release into manufacturing with adherence to stringent tier 1-customer requirements Datasheet and automotive compliance reports Real time customer support for design, product and quality related issues Temperature/Voltage/Process characterization and production limit setting Product new product introduction and yield ownership Product BOM release and maintenance Excursion management for both suppliers and customers Use commercially available yield tools for yield improvement and monitoring, generate weekly reports and review with PE teams KPI achievement in product related deliverables including NPI execution and velocity, product cost (Gross margin improvements), product quality performance and failure analysis cycle times PAT, SYL, SBL, SPC limit and disposition optimizations to protect quality without excessive waste REQUIREMENTS: 7+ years experience in product engineering. A strong analog circuit background is a must. Familiarity with power management IC testing would be a plus Familiarity with ATE tester platforms (eg. Teradyne J750, Advantest 93K) Knowledge of analog and mix-signal circuitry and the common building blocks, device physics, test methodology and DFT knowledge Experience with common lab test equipment (DC power supply, oscilloscope, multi-meters etc). Bench characterization experience is a plus Familiarity with JEDEC/AEC qualification standards and stress test conditions. Experience with qual hardware/software development would be preferred Experience in yield management tools such as PDF Exensio, JMP. Apply statistical analysis to isolate the issue and make data-driven decisions Ability to managing supplier excursions and customer escalations through problem solving Knowledge of Semiconductor Failure Analysis is preferable Strong verbal and written communication skills A good team player. Effective in fast paced, dynamic work environment Qualifications BS in Electrical/Electronic Engineering MS in Electrical/Electronic Engineering is preferred Company Description Renesas is a global semiconductor company providing hardware and software solutions for a range of cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas is a global, multi-billion dollar, publicly traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multi-cultural technology company where employees learn, mentor, innovate and thrive. Renesas is extending our share in fast-growing data economy-related markets such as infrastructure and data center and strengthening our presence in the industrial/IOT and automotive segments. Our solutions drive products developed by major innovators around the world. Join us and build your future by being part of what s next in electronics.

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6.0 - 11.0 years

11 - 15 Lacs

Bengaluru

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Technical Manager role requiring 15+ years of experience of Digital design in Analog Mixed signal ICs for developing Power Management ICs as part of 2. 6B$ Power Business Unit at Renesas. Primary responsibilities include leading team which will fully own defining the microarchitecture to developing all Digital components of power management ICs, starting from System requirements. Due to the complex nature of Chips and significant Analog as well as Digital contents, collaboration with cross-functional teams to ensure successful integration of Digital and Analog components in ICs, is a must. The candidate will work on a wide range of exciting and cutting edge PMICs, including Linear and Switching DC-DC converters powering the next generation of most sought-after phones and handheld devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas s massive Power product portfolio. Essential Functions: Manage the Digital Design team in terms of costs, methods and staffing to support device/silicon design requirements and to meet design deadlines as set by the program schedule. Mentor direct reports, giving appropriate guidance and support, and reviewing technical and behavioural performance regularly Must have experience of defining Dig-Ana boundary and Digital design scope for Power Management ICs/Analog intensive ICs Must have experience of defining the micro-architectures and sub-blocks for the ICs to ensure optimized Digital design, RTL design and Gate level netlist etc. Must be aware of Power Sensitive digital design and doing Power estimation for the Digital I/Ps Must be able to handle Clock Domain Crossing across multiple clock domains seamlessly and in a glitch free manner. Should be able to lead/collaborate for Logic Synthesis, Formal verification, Power estimation and STA. Should have experience of OTP, MTP, Efuse read/writes, controller design and data bus handling, Register read/write, Trimming of Analog parts/functions, DFT architecture and integration. Should be able to create Sequences (including Power UP/Down) and State Machines and Transitions to/from any state to another based on the IC requirements. Should be an expert of one or more Power Chip Communication I/Ps and protocols e. g. I2C, PMBUS, SVI3, SVID etc. Should be able to implement and analyse filters feedback loops in Digital, conversant with Z-domain analysis. Must have done multiple silicon debugs, root cause analysis of issues, design to silicon correlation etc. Should understand commonly used control loop architectures (Constant Freq, Constant ON/OFF Time, Current mode etc) and pros/limitations of each. Must be able to bring in innovative ideas to improve designs to meet challenging specifications and achieve better system performance. Should be able to setup Digital design flows and methodologies including checklists, reviews to ensure quality designs and take them all the way to Silicon success. Qualifications Bachelor s or master s degree in electrical engineering 15+ years in Digital Design and experience of working on Mixed Signal ICs, especially PMICs. Solid understanding and design experience of complex AMS designs. Chip design, Verification, Silicon validation, debugs, Qual support and taking ICs to production. Must be a technical leader, people manager team player, mentor and should strive towards fostering a highly creative and productive working environment Collaboration with Senior leadership to develop team objectives in accordance with wider company strategy. Ability to work with Senior Management to develop and work to budget. Cross cultural awareness and sensitivity. Results-oriented and able to deliver on-time under tight schedule pressure. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

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3.0 - 10.0 years

30 - 35 Lacs

Bengaluru

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Join the Wireless Technologies and Ecosystems (WTE) team and be part of a best-in-class team of engineers, working with multi-functional teams to drive innovation and develop products used by millions worldwide. We are looking for a highly reciprocal individual who can excel in a high-paced environment. Be ready to make something extraordinary when you come here. Dynamic, encouraging people and innovative, industry-defining technologies are the norm at Apple. The people who work here have reinvented and defined entire industries with our products and services. The same real passion for innovation also applies to our business practices - strengthening our dedication to leave the world better than we found it. You should join Apple if you want to help deliver the next amazing Apple product. Description Apple s Cellular Software team is seeking talented, highly motivated and disciplined engineers to work across layers on groundbreaking cellular technologies. The position involves identifying and/or developing core cellular technologies that solves everyday problems for customers using iPhone, iPad, Watch and other wireless product lines. We are passionate about keeping our users connected 24/7 wherever they go. This team takes pride in not just coming up with proven software designs but also in disrupting traditional models of the cellular ecosystem. We do whatever it takes to bring user experience to the next level. Our members enjoy the flexibility to work on all aspects of Cellular Protocol software - SIM, NAS, AS and iOS interfaces, to come up with the best possible solution for any given problem. Cellular Power Team is responsible for developing platform power management SW across all the Apple Cellular Modem chips. Team is responsible to verify and enable all the platform as well as RAT power features with the end goal of delivering the best power KPIAre you equally passionate about cellular technologies and have the dream to work on groundbreaking cellular technologies? Then we are looking for you. As part of this team you will impact iPhone user experience worldwide. 3-10 years of experience in wireless product development Experienced in doing low level driver development for cellular modem products Expertise in the area of modem power management system & power flows Strong expertise in design and implementation of modem power management drivers Strong Software Engineering skills including design, programming (using C, C++), scripting (Python preferred, Perl) and debugging Preferred Qualifications Experience in trouble shooting complex race conditions between SW and HW power management flows Hands-on experience in debugging of modem products. Highly motivated and self-directed Excellent debugging skills. Hands-on experience in debugging of modem products. Thrive in a collaborative environment and can clearly communicate while confidently driving multiple projects across many teams. Obsessively passionate and inquisitive, and seek to solve everyday problems in innovative ways. Laser-focused on the smallest details that are meaningful to our customers.

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3.0 - 7.0 years

5 - 9 Lacs

Pune

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Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for. Responsibilities & Skills Lattice is seeking candidates for the position of Senior Staff Software Development Engineer. This is a full-time position located in Pune, India. Accountabilities: Develop and deliver state-of-art database and software infrastructure for world-class ease-of-use FPGA software tool for small, mid-range and large FPGA products. Develop software capabilities for next generation of FPGA products. Support and maintain existing FPGA design tools. Contribute to Spec and Plan process - review marketing requirement documents, generate functional specifications and developer unit test plans to ensure quality software. Improve development methodologies and processes. Qualifications: BS/MS/PhD Electrical Engineering or Computer Science 12+ years of experience in large-scale software development for engineering application domains preferably in FPGA/ASIC EDA domains. Must be proficient with C++. Modern C++ proficiency is a plus. Strong background in object-oriented programming, data structures and algorithms, and graph theory Experience of working on multiple platforms - at least Linux and Windows - is required. Knowledge of shell, TCL or Python scripting is a plus. Familiarity with commercial FPGA software tools and design flow is a plus. Knowledge in FPGA logic design is a plus. Must be detail oriented and possess independent problem-solving skills. Must be able to drive projects and lead a discussion. Strong written and verbal communication skills, and collaboration skill with the ability to work with multiple groups. Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA , CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com . You can also follow us via Twitter , Facebook , or RSS . At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates. Lattice Feel the energy.

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5.0 - 10.0 years

7 - 12 Lacs

Gurugram

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Not Applicable Specialism Managed Services & Summary . In climate and energy at PwC, you will focus on providing consulting services related to climate change mitigation and adaptation, as well as energy efficiency and renewable energy solutions. You will analyse client needs, develop strategies to reduce greenhouse gas emissions, and offer guidance and support to help clients transition to a lowcarbon economy. Why PWC At PwC, you will be part of a vibrant community of solvers that leads with trust and creates distinctive outcomes for our clients and communities. This purposeled and valuesdriven work, powered by technology in an environment that drives innovation, will enable you to make a tangible impact in the real world. We reward your contributions, support your wellbeing, and offer inclusive benefits, flexibility programmes and mentorship that will help you thrive in work and life. Together, we grow, learn, care, collaborate, and create a future of infinite experiences for each other. Learn more about us . A career within General Consulting services, will provide you with the opportunity to help clients seize essential advantages by working alongside business leaders to solve their toughest problems and capture their greatest opportunities. We work with some of the world s largest and most complex companies to understand their unique business issues and opportunities in an everchanging environment. We help create sustainable change by stimulating innovation, unlocking data possibilities, navigating risk and regulatory complexity, optimizing deals, and aligning costs with business strategy to create a competitive advantage. s As a Manager, youll work as part of a team of problem solvers, helping to solve complex business issues from strategy to execution. PwC Professional skills and responsibilities for this management level include but are not limited to You will be working across functional teams (internal and client), across the business and Renewable Energy sector value chain, supporting the team in developing and delivering operations strategies in the Renewable sector. Develop yourself personally, taking a keen interest in trends in energy and other sectors and the impact on our clients so you can help shape their thinking and our success in the market. Prepare quality reports, presentations and other client deliverables. Exposure to data gathering techniques and analysis, and reporting insights in a clear Mandatory skill sets Financial Modeling, Bid Management, Feasibility Analysis, Due diligence, Power, Power Market, Energy trading, Energy Portfolio Management. Preferred skill sets Use feedback and reflection to develop self awareness, personal strengths and address development areas. Demonstrate critical thinking and the ability to bring order to unstructured problems. Use a broad range of tools and techniques to extract insights from current industry or sector trends. Years of experience required 7 years Education qualification B.tech + MBA Education Degrees/Field of Study required Master of Business Administration, Bachelor of Engineering Degrees/Field of Study preferred Required Skills Power Management Optional Skills Accepting Feedback, Accepting Feedback, Active Listening, Analytical Thinking, Carbon Accounting, Carbon Footprint, Carbon Offsets, Carbon Pricing and Trading, Carbon Taxes and Incentives, Climate Change Adaptation Program Design, Climate Change Impacts and Risks, Climate Change Scenarios, Climate Finance, Climate Policy, Climate Reporting, Coaching and Feedback, Communication, Creativity, Embracing Change, Emission Trading, Emotional Regulation, Empathy, Energy Efficiency, Energy Policy and Regulation, Energy Transition {+ 15 more} Travel Requirements Government Clearance Required?

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0.0 - 3.0 years

2 - 5 Lacs

Hyderabad

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Our vision is to transform how the world uses information to enrich life. Join an inclusive team focused on one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solution we create help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can spark the very innovation we are pursuing. As a Memory Circuit Design Verification Engineer, you will work in a highly innovative, motivated, young and dynamic design team capable of verifying complete products using state of the art memory technologies. You will need to have the ability to evaluate full chip and/or block level functionality and provide solutions to help the timely delivery of a functionally correct design. Unique Opportunities Complete ownership of verification and end to end analysis of complex full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR4, LPDDR4,DDR5 and LPDDR5 that are capable of operating at high speeds of up to 6400MT/s. Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design. Work on cross functional tasks that can widen your skill set. About Team For nearly 40 years, Micron Technology, Inc. has redefined innovation with the world s most advanced memory and semiconductor technologies. we're an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. Our Global team is growing and we are looking for a passionate Memory Circuit Design & Verification Engineer in Micron Technology s DRAM and Emerging Memory Group (DEG) in India. Responsibilities Participate in simulating, analyzing and debugging pre-silicon full chip designs by applying leading edge verification technique Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Core Requirements Analytical capability for complex gate level circuit designs Basic understanding of CMOS circuit designs Familiar with both SPICE and Verilog simulations Good communication skills and ability to work we'll in a team Education Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field required

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3.0 - 6.0 years

5 - 8 Lacs

Hosur, Bengaluru

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Qualifications Educational qualification: Bachelor s or Master s degree in Computer Science or Electronics or Electrical Engineering or related field. Experience : 3-6 years Skills : Work Experience: Atleast 3+ years of relevant Industry or Academic experience with Linux Kernel Skills/experience: Excellent knowledge of OS fundamentals, Data structures, Linux kernel and its device driver model Excellent programming skills and expert level knowledge of C Excellent debugging skills, using kernel tracers as well as JTAG and GDB debuggers Good knowledge of memory management, interrupt handling and power management in Linux Good understanding of ARM v8/v9 CPU and cache architectures Proficient in Git for development and patch/branch management Experience with python, perl, rust, shell scripting is a plus Know how of Linux Kernel upstream patch submission process with patches merged in kernel.org as well as experience working with community development boards (Dragonboards/Pandaboards) is a double plus Independent and self-motivated problem solver and strategic thinker Effective written and verbal communication Excellent interpersonal and teamwork skills

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3.0 - 5.0 years

3 - 7 Lacs

Hyderabad, Chennai, Bengaluru

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Post Silicon Validation Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Experience in silicon lab validation for power management ICs. Experience with validation of Mixed-signal ICs. Experience in validation test planning, test development, execution, debug and report preparation. Hands-on experience of using lab equipment such as oscilloscope, signal analyzer, signal generator, etc. familiarity of programming and scripting languages like Python, Perl Experience in automation using NI Labview is an advantage Understanding of power management ICs, architecture, specifications interpretation is required Debug skills to zero in on an issue, coordination with cross-functional teams is required Skills Experience LabVIEW, PMIC, Post Silicon Validation, System Validation, Testing Validation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

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4.0 - 9.0 years

4 - 8 Lacs

Hyderabad, Chennai, Bengaluru

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Pre-Silicon Validation Engineer Experience4 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Creating test environments, checker strategies, and test generators for validating embedded power management firmware in the SOC Communicating effectively, coordinating and working with firmware developers and SOC integration teams Potentially participating in the debug of failures in silicon and developing new testing strategies to detect these failures on pre-silicon models Mentoring junior members of the team in their development You should have 3-5 years of experience in the following areas: SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM Reading and interpreting technical specs and Register Transfer Level (RTL) code SW development skills (Unit Testing, Test Driven Development) Hands-on Debug Preferred Skills and Experience: Expertise in any of one domain like Audio, Performance, power management will be a huge plus 4+ years’ experience with writing validation plans and implement those validation plans Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

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3.0 - 8.0 years

2 - 5 Lacs

Bengaluru

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Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

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2.0 - 5.0 years

6 - 10 Lacs

Bengaluru

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- Lead the architecture, design and development of Power Management for a highly virtualized, multi-threaded, many-core and multi-socket SMP (symmetric multi-processor) . - Develop the features, present the proposed architecture in the High level design discussions to hardware and software teams - Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, firmware, software teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Estimate the overall effort to develop the feature - Estimate the silicon area required for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing Server SoC power management features. * Experience with hardware to model correlation * At least 1 generation of silicon bring up experience * In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) * Proficiency of RTL design with Verilog or VHDL * Knowledge of at least one object oriented or functional programming language and scripting language. Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

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3.0 - 6.0 years

0 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Introduction As a Hardware Engineer at IBM, youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in todays market. Your role and responsibilities Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise 3-6years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification : Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

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8.0 - 12.0 years

5 - 9 Lacs

Bengaluru

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Position:Embedded C,Linux kernel, Power Management. Experience:8-12 years Location:Bangalore Education:B.E in Electronics & Communication Engineering. TessolveSemiconductors a venture of Hero Electronix, part of $5B Hero Group companies a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Currently we are 2300+ employees worldwide. We are Global Multi- National Company having Engineering and Sales presences in India, Malaysia, Singapore, USA, UK, Europe, and China. Tessolve has strategic and sustainable growth plan to ensure the business stability to our valued customers and to protect the career of our employees even under disturbed Business situations. Technical Skillset Required: KEY RESPONSIBILITIES: Contribute to the development and optimization of power management features in the Linux kernel, focusing on heterogeneous core architectures. Develop, test, and refine kernel patches related to power management, scheduler enhancements, and S0ix state optimization. Debug and resolve core idle state issues within the Linux kernel to improve system efficiency and performance. Work on DisplayPort (DP) and Alternate Mode (Alt Mode) functionalities in the kernel, ensuring seamless integration and performance. Collaborate with cross-functional teams to design and implement new features and improvements in the Linux kernel. Participate in code reviews, provide feedback, and ensure adherence to best practices and coding standards. Stay updated with the latest developments in the Linux kernel community and contribute to upstream projects. Document design specifications, technical details, and user guides for developed features and patches.

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15.0 - 20.0 years

22 - 27 Lacs

Bengaluru

Hybrid

NES SOC Architecture team is looking for an outstanding engineer to work on definition of NEX SoC(s) for Intel Server, Client and IoT platforms. In this role, you will develop and drives end-to-end SoC architecture for highly optimized, modular, and scalable SoC, based on hardware features, requirements, and interoperability of hardware and software throughout the product life cycle.You will collaborate across disciplines to analyze workloads, identify opportunities for improvement, determine priorities, and balance trade-offs. Responsibilities include: Determining functional requirements based on product goals, use cases, and workload analysis. Defining SoC architecture to meet product requirement and deliver architecture specifications. Evaluates feasibility trade-offs and explores and defines new approaches and novel architectures for SoC. Invents, conceptualizes, and specifies microarchitecture and architectural features for next-generation products to deliver optimized SoC for multiple segments from high performance computing to extreme low-power products. A successful candidate will demonstrate. Broad knowledge of SoC architecture. Performance, power trade-off understanding. Deep expertise in domains such as reset, clock, coherency, debug, power management, performance evaluation Exceptional communication skills. Collaborates with design engineers, system engineers, verification engineers, structural design engineersto improve the overall design of SoC and overcome constraints. Work will include a combination of individual contribution and leveraging team participation through mentoring and leadership of technical initiatives. Qualifications: Minimum Qualifications: Bachelor's degree or higher in Computer Science or Electronics Engineering, 15+ years relevant experience in Silicon development in Arch/Uarch, Modeling, Designincluding multiple project development life cycles with at least one as lead architect or lead u-architect.

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20.0 - 22.0 years

16 - 25 Lacs

Rajasthan

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Min 20 years of experience in Power Distribution Sector. Relevant experience in power utilities & electricity distribution projects. Should have done at least one project of Rs. 1000 Cr or above in the capacity of Team Leader or similar.Developing project plan and implementing the same. Documenting daily, weekly, monthly and yearly report and submitting the same to the top management. Encouraging and assisting the team members and workforce for effective work resulting in improvement.

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3.0 - 8.0 years

7 - 11 Lacs

Bengaluru

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About the Role : We are seeking highly motivated and skilled Power Management Firmware Engineers to join our team and contribute to the development of cutting-edge power management solutions. In this role, you will be responsible for designing, developing, and maintaining firmware for power management subsystems, ensuring optimal power efficiency and system performance. Key Responsibilities : Design, develop, and maintain firmware for power management subsystems, including : a. BIOS power management features (e.g., ACPI, sleep/hibernate states, power profiles) b. Platform power management (e.g., CPU/device power states, hot-plug, dynamic voltage and frequency scaling) c. PCIe power management and link states d. Analyze and debug power-related issues. e. Optimize power consumption across the system. - Collaborate with hardware and software engineers to ensure seamless system integration. - Stay abreast of the latest power management technologies and industry standards. - Contribute to the development and documentation of firmware specifications. Required Skills : Mandatory : - Very strong in C language programming and debugging - Working knowledge of git/gerrit Key Skillsets : - Good understanding and experience with BIOS, power management and PCIe - Good knowledge SoC power management - CPU/Device power states, hot-plug etc - Strong knowledge of UEFI BIOS, ACPI. - AGESA knowledge is a big plus - Experience with embedded systems development and debugging. - Strong analytical and problem-solving skills. - Excellent communication and collaboration skills. Desired Skills (Optional) : - Experience with assembly language programming. - Knowledge of scripting languages (e.g., Python, Perl). - Experience with Agile development methodologies. - Experience with power measurement and analysis tools. Keywords Power Management,BIOS,PCI-e,SoC,Embedded System,Perl,C,git,Firmware*

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10.0 - 12.0 years

12 - 14 Lacs

Bengaluru

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Job Details: Job Description: Develops and drives Power Modelling and Estimation framework for highly optimized, modular, and scalable SoCs. Actively works on power analysis, power optimization, simulation and roll-ups. Should be hands on PTPX/Power artist and other industry standard power estimation tools. Collaborate with the Various SoC and IP teams on various power projections and requirements, including silicon power capture and correlation with pre-si estimates. Perform data mining analysis at the RTL and gate-level to define relevant micro-architectural transactions for high-level power estimation Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. What we need to see Minimum Qualifications: Bachelors degree in Electrical Engineering, Computer Engineering or similar with 10+ years of relevant work experience, e.g. in consumer electronics or semiconductor companies. 5+ years' experience with system design of small, medium, and large power management or power modelling systems including hands on experience with PTPX/Power artist tools. Preferred Qualifications: Bachelors degree in Electrical Engineering, Computer Engineering or similar with 12+years of relevant work experience Strong ability to manage multiple projects, grow knowledge and capabilities of the power team, and perform hands-on testing Background in analog or digital power design. Job Type: Experienced Hire Shift: Shift 1 (India)

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20.0 - 22.0 years

16 - 25 Lacs

Rajasthan

Work from Office

Min 20 years of experience in Power Distribution Sector. Relevant experience in power utilities & electricity distribution projects. Should have done at least one project of Rs. 1000 Cr or above in the capacity of Team Leader or similar.Developing project plan and implementing the same. Documenting daily, weekly, monthly and yearly report and submitting the same to the top management. Encouraging and assisting the team members and workforce for effective work resulting in improvement. Keywords Team Management,Site Management,Power management,Electricity Distribution*,Site Incharge,Electrical Project*,Power Distribution*,Electrical,Power Engineering,Power Utility*,Utility & Electricity*

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1.0 - 3.0 years

0 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Introduction As a Hardware Engineer at IBM, youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in todays market. Your role and responsibilities Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise 1-3 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification : Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

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4.0 - 6.0 years

7 - 8 Lacs

Bengaluru

Work from Office

2 Y+ Experience in Energy Automation & electrical distribution. Passionate about Sustainability, Energy Efficiency and new Energy landscape topics. Expertise in Industrial automation software, PLC programming & SCADA - Knowledge of Schneider PLCs and tools is preferred. Expertise in Industrial communication protocols including Modbus TCP/IP Programming in Structured text and or Ladder logic in compliance with IEC61131. Programming in IEC61499 Automation Expert - (Preferred) Knowledge of Electrical systems and Power Management Systems (Controls, Power inverters, BESS, PV inverters, Gensets, etc.).

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5.0 - 7.0 years

10 - 12 Lacs

Bengaluru

Work from Office

Requirement: 2Y+ Experience in Energy Automation & electrical distribution. Passionate about Sustainability, Energy Efficiency and new Energy landscape topics. Expertise in Industrial automation software, PLC programming & SCADA - Knowledge of Schneider PLCs and tools is preferred. Expertise in Industrial communication protocols including Modbus TCP/IP Programming in Structured text and or Ladder logic in compliance with IEC61131. Programming in IEC61499 Automation Expert - (Preferred) Knowledge of Electrical systems and Power Management Systems (Controls, Power inverters, BESS, PV inverters, Gensets, etc.)

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1.0 - 4.0 years

2 - 5 Lacs

Bengaluru

Work from Office

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-6years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

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6.0 - 10.0 years

17 - 22 Lacs

Bengaluru

Work from Office

locationsIndia, Bangalore time typeFull time posted onPosted 5 Days Ago job requisition idJR0274956 Job Details: About The Role : Foundry Services (FS) is an independent foundry business that is established to meet our customers' unique product needs. With the first Open System Foundry model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient, and sustainable source of supply. This job opportunity in FS will be part of the Customer Solutions Engineering (CSE) group which is responsible for the portions of the system foundry that brings the best of Intel technologies to FS customers, differentiating and accelerating their solutions from architecture to post-silicon validation. We are looking experienced Floorplan Engineer to work on Foor plan, die estimation, Power planning of high performance designs . Responsibilities include Establishes the integration plans for die with optimization for package and board constraints. Bump planning, Die file generation , closing loop with package team on signal and power bump placement restrictions Create physical database for the IP or SoC. Collaborate with architects to optimize the placement of IPs for latency as well as die area/aspect-ratio. Collaborate with the design teams on clocking and dataflow to deliver the physical block level floorplans for APR. Derive specifications and collaterals for the IP blocks to execute the floorplan and automatic place and route (APR) at subsequent hierarchies. Coordinate with power delivery team on trade-offs for metal allocation for signal and power. Have excellent understanding on, die-per-reticle/good-die-per-wafer maximization, and right technology selection on metal layers usage maximization Good knowledge on RDL routing and efficient usage higher metal layers Performs integration of all dies in a package and completes the relevant checks before tape-out. Qualifications: Qualification : 12+ Years of relevant Experience After a Bachelor or Master of Engineering degree in Electrical/ Electronic/VLSI Engineering or related field. Must have led multiple SOCs in capacity of SOC Floorplan lead. Strong Expertise in Design planning, die estimation, Good understanding on package and board level requirement . Must have knowledge on clocking , high speed design signal routing, industry standard protocols and IP architecture; Good understanding on relevant areas of Library / Memory / technology/submicron issues . Teamwork / flexibility / ability to thrive in a dynamic environment are very important Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Intel Foundry is dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. As stewards of Moore's Law, we innovate and foster collaboration within an extensive partner ecosystem to advance technologies and enable our customers to design leadership products. Our strategic investments in geographically diverse manufacturing capacities bolster the resilience of the semiconductor supply chain. Leveraging our technological prowess, expansive manufacturing scale, and a more sustainable supply chain, Intel Foundry empowers the world to deliver essential computing, server, mobile, networking, and automotive systems for the AI era. This position is part of the Foundry Services business unit within Intel Foundry, a customer-oriented service organization that is dedicated to the success of its customers with full P&L responsibilities. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

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