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RTL ASIC Engineer (All Levels)

1 - 15 years

0 Lacs

karnataka

Posted:1 week ago| Platform: Shine logo

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Skills Required

rtl design verilog system verilog asic design timing analysis dft implementation upf cdc rdc lint clocking power management interconnect safety security architecture low power signoff debug

Work Mode

On-site

Job Type

Full Time

Job Description

You should be an ASIC designer with a minimum of 1-15 years of experience in RTL design using Verilog/System Verilog. Your expertise should cover all aspects of the RTL design flow, including Specification/Microarchitecture definition, design and verification, Timing Analysis, DFT, and Implementation. You should also have experience in Integration, RTL signoff tools, UPF/Low power signoff, CDC/RDC, and Lint. Your domain knowledge should be strong in Clocking, System modes, Power management, debug, interconnect, safety, security, and other architectures. As a highly motivated individual, you should be a self-starter with excellent interpersonal skills and the ability to work effectively in a team. Strong communication, critical thinking, and problem-solving skills are essential for this role. Preferred education for this position is any degree.,

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