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Alpha-Numero
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Design and Verification Engineer – 2+ years

Design and Verification Engineer – 2+ years

3 years

|

0 Lacs

Ahmedabad Gujarat India

Posted:1 month ago| Platform:

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Skills Required

design verification verilog analyze code reports communication vhdl coding

Work Mode

On-site

Job Type

Full Time

Job Description

Role: DV Engineer Locations: Hyderabad, Ahmedabad, Bangalore. No. of positions: Multiple Experience : 3+ years Requirements Strond Knowledge of System Verilog and UVM Proven Expertise in Architecting Complex Verification Environments using System Verilog and UVM Ability to quickly ramp-up on complex FPGA Interfaces and must have completed at least one full verification life cycle Strong Digital and verification Fundamentals Ability to Understand the specifications and must have experience developing BFMs/UVCs for industry standard protocols Ability to Analyze Functional and Code reports and experience with the verification closure Strong Written and verbal Communication Strong knowledge of Verilog/VHDL and must be able to read and understand the complex HDL Coding” Show more Show less

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