500 System Verilog Jobs - Page 2

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com . Job Description The position involves designing, developing and deploying UVM/C based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality. The candidate should have worked on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM Cortex and proprietary processor technology and AMBA AHB/AXI/APB along with peripheral interfaces like SDIO, UART, I2S, I3C, PWM. Responsibilities: Develop and track execution of chip level test planning to meet product requirements and established quality standards Lead a team to complete the pre-silicon verification of an SoC Execute and maintain chip level verification regressions. Triage and debug failing tests. Develop or update tests to satisfy the test plan requirements. Tests will be combination of directed (C tests), constrained random (UVM), and formal verification. Perform gate level verification across corners. Provide appropriate activity files for power analysis. Coordinate verification activities with a global team and the design lead. Provide succinct weekly status and drive action items to closure. Experience Level: 12-15 years in Industry Education Requirements: Bachelor or Master s degree in Electrical and/or Computer Engineering Minimum Qualifications: Develop and signoff on test plans and test cases Strong knowledge of digital design and AMBA AHB/AXI/APB based SoC Architecture Strong knowledge of Verilog, System Verilog, UVM, C/C++ Experience in usage of assertions, constrained random generation, functional/code coverage. Knowledge of scripting languages like Perl, Python, Tcl, shell to achieve automation of verification methodologies and flows Very strong Analytical debugging skills Knowledge on C Based Testcases. Knowledge of SoC,Memory and Cache Architectures Knowledge on Low power designs and architectures Verify and debug low-power design Debug SDF Back Annotated Gate Simulations Low-power implementation (UPF) Mixed Signal Real Number Modeling (RNM, Spice) Preferred Qualifications: Knowledge of high-speed interfaces like Quad/Octa-SPI Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN Knowledge of wireless technologies like WLAN, Bluetooth, ZigBee Mentoring skills Exceptional problem-solving skills Good written and oral communication skills Benefits & Perks: Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

We are seeking highy motivated individuas with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to hande the chaenging probems in future technoogies and designs. We are aso ooking for candidates with Strong C/C++background to ead our eading-edge agorithmswithin our EDA soutions to increase our design team’s productivity and chip quaity and performance. Our dynamic goba team is ooking to enist enthusiastic professionas to join word-cass hardware design teams responsibe for deveoping the most chaenging and compex systems in the word. We are seeking energetic, highy motivated individuas wiing to go the extra mie with the aim of heping the overa IBM deveopment team. Strong interpersona skis are needed to coordinate deiverabes and requirements from severa areas within and outside of the organization.There are many opportunities to gain and utiize a deep understanding of future issues and provide input towards decisions affecting system deveopment, ogica and physica design as we as sophisticated methodoogy directions. Individuas who are chosen to become a part of our word cass deveopment teams wi be heping advance IBM’s eadership in deveoping the highest performing computers and changing hardware soutions. Do you want to be an IBMerCome THINK with us! Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise 4+ years of IT experience Strong C/C++programming skis in a Unix/Linux environment is a must. VLSI knowedge, Knowedge in front end inting toos and checkers and RTL Checkers. Great scripting skis – Per / Python/She Proven probem-soving skis and the abiity to work in a team environment are a must Preferred technica and professiona experience RTL Lint Checkers , Front end verification fow, VLSI knowedge, VHDL/Veriog, computer architecture

As a Logic Design Engineer in the IBM Systems division, you wi be responsibe for the microarchitecture design and deveopment of features to meet Secure, high performance & ow power targets of the Mainframe and / or POWER customers. Deep expertise in the impementation of functiona units within the core / cache / Memory controer / Interrupt / crypto / PCIE / DLL Additiona responsibiities: ogic (RTL) design, timing cosure, CDC anaysis etc. Understand and Design Power efficient ogic. Agie project panning and execution. Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise Minimum 8+ years of experience in Chip design and deveopment. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, mutipiers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Veriog

As a Logic design Engineer in the IBM Systems division, you wi be responsibe for the microarchitecture design and deveopment of features to meet Secure, high performance & ow power targets of the Mainframe and / or POWER customers.Deep expertise in the impementation of functiona units within the core / cache / Memory controer / Interrupt / crypto / PCIE / DLLAdditiona responsibiities:ogic (RTL) design, timing cosure, CDC anaysis etc.Understand and Design Power efficient ogic.Agie project panning and execution.Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise Minimum 8+ years of experience in Chip design and deveopment. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, mutipiers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Veriog

About Us: We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trendswe set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. Key Responsibilities: Take part of the verification of designs, whether at the block or subsystem level. Participate in defining and implementing UVM-based test environments. Support the creation of Verification Strategies and contribute to the development and execution of Verification Plans. Develop, run, and debug test cases to ensure design quality under supervision. Contribute to the improvement and optimization of verification methodologies. Generate documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Required Qualifications: Bachelors degree in electrical or computer engineering. 5+ years industry experience in verification using SystemVerilog and UVM. Additional experience will allow placement at higher job levels. Strong experience in / with: development of verification test plans and create directed/randomized test cases. formal verification. in implementing scoreboards, checkers, bus functional models in existing testbench environment. SystemVerilog Assertions. Additional Requirements: Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Experience in low-power design verification. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like. Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more. Primary country and city: India (IN) || Bangalore Req ID: 768626

About this opportunity We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trendswe set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements. Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. You will bring Key Responsibilities: Lead a team of verification engineers, providing mentorship and guidance to ensure efficient and reusable verification practices. Collect and address, team status and metrics. Take full responsibility for the verification strategies that the team has responsibility for. Define and implement UVM-based test environments. Break down requirements to create a Verification Strategy and develop and execute a Verification Plan. Develop, run, and debug test cases to ensure design quality. Continuously improve and optimize verification methodologies. Generate comprehensive documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Develop competence in the technical domain. Foster cross-team collaboration to ensure seamless project delivery and integration. Required Qualifications: Bachelors degree in electrical or computer engineering. 8+ years of industry experience in verification using SystemVerilog and UVM. Proven track record of leading verification test plan development in cross-site environments. Proficiency in/with: architecting and creating new grounds-up random and directed test environments and testcase strategies. formal verification for connectivity checks and using assertion-based VIPs. architecting and leading implementation of scoreboards, checkers, bus functional models SystemVerilog Assertions. Strong experience in low-power design verification. Additional Requirements: Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like. Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more. Primary country and city: India (IN) || Bangalore Req ID: 766878

Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices, Job Description In your new role you will: Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices, Responsible for: Designing self-checking test benches using modern verification techniques Implementing functional coverage and assertions using System Verilog and UVM, Developing TB environment using SV and UVM, Developing test and functional coverage plans based on device specifications, Analyzing and debugging simulation failures, as well as analyzing functional coverage results to guarantee zero defect outcomes, Your Profile You are best equipped for this task if you have: Engineering in Electrical/electronic streams , or equivalent experience, 2+ years experience in constrained-random, coverage driven verification environments, Experience in RAL Experience in developing the test bench from scratch using System Verilog (SV) HDVL and UVM (Universal Verification Methodology), Expertise in Gate Level simulations (GLS) and have debugged, root caused real netlist issues, A solid understanding of verification concepts and experience designing class-based test benches, C coding, Formal verification methods and Power aware simulation will be an advantage Excellent written and oral communication skills Strong debugging skills, functional simulations and GLS simulations, Contact: Gowri ShenoyGowri Shenoy@infineon,, LinkedIn #WeAreIn for driving decarbonization and digitalization, As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals Be a part of making life easier, safer and greener, Are you in We are on a journey to create the best Infineon for everyone, This means we embrace diversity and inclusion and welcome everyone for who they are At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities We base our recruiting decisions on the applicant?s experience and skills, Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process, Click here for more information about Diversity & Inclusion at Infineon,

As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: 1. Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. 2. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. 3. Perform design optimizations for area, power, and performance. 4. Conduct design reviews and ensure compliance with coding standards and best practices. 5. Work closely with verification teams to develop test plans and ensure 100% functional coverage. 6. Debug and resolve design and integration issues during simulation and post-silicon validation. 7. Participate in timing analysis and closure in collaboration with the physical design team. 8. Document design specifications, test cases, and user guides for IP and SoC designs. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 210 years of experience in RTL design and implementation for VLSI systems. 3. Strong expertise in Verilog, SystemVerilog, and RTL design methodologies. 4. Solid understanding of digital design concepts such as pipelining, clock domain crossing, and low-power design techniques. 5. Experience with EDA tools like Synopsys Design Compiler, Cadence Genus, or equivalent. Proficiency in scripting languages (Python, Perl, TCL) for design automation. 6. Familiarity with SoC interfaces and protocols like AXI, AHB, PCIe, USB, or DDR. 7. Experience in static timing analysis (STA) and timing closure workflows. 8. Strong problem-solving skills and the ability to debug complex design issues. 9. Excellent communication and collaboration skills to work effectively in a team environment. Preferred Qualifications: 1. Experience with low-power design and multi-clock domain systems. 2. Knowledge of advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 3. Exposure to formal verification methodologies. Experience in hardware-software co-design and FPGA prototyping. 4. Familiarity with machine learning or AI-based RTL optimizations. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future.

Design Verification Engineer (3-8 years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 3-8 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement Design Verification Engineer (7-10 years’ experience) Company: HCL Tech Job Summary: We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 7-10 years of solid experience in Design Verification for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package commensurate with experience Opportunity to work on leading-edge technologies and projects with a high impact Collaborative and dynamic work environment that fosters continuous learning Potential for professional development and career advancement Design Verification Engineer (Senior Level - 10+ years’ experience) Company: HCL Tech Job Summary: We are seeking a highly accomplished Design Verification Engineer (DV) to join our elite team and lead the verification efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of verification methodologies and the ability to drive the development and execution of comprehensive verification plans. You will be responsible for ensuring the functional integrity and quality of our next-generation integrated circuits through innovative verification strategies. Responsibilities: Lead and define the overall verification strategy for assigned projects, leveraging advanced methodologies (UVM, Formal Verification) Architect and design robust verification environments (testbenches) to achieve exceptional code coverage and functional verification goals Utilize industry-leading verification tools (simulators, formal verification tools) to conduct thorough verification and analysis Debug and troubleshoot complex verification failures, identifying root causes and collaborating with design engineers for efficient resolution Mentor and guide junior DV engineers, fostering a culture of excellence and knowledge sharing within the team Champion best practices for verification code quality and participate in code reviews Stay at the forefront of the verification landscape by actively researching and adopting emerging tools and methodologies Provide technical leadership and contribute to the overall verification roadmap for the team Qualifications: Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred) Minimum of 10+ years of experience in Design Verification for complex ASICs and SoCs Proven track record of successfully leading and executing verification projects In-depth knowledge of digital design principles, advanced verification methodologies (UVM, Formal Verification), and best practices Expertise in Verilog and VHDL with a strong grasp of coding styles and optimization techniques Extensive experience with a broad range of verification tools (simulators, formal verification tools, scripting languages) Excellent leadership, communication, collaboration, and problem-solving skills Ability to manage multiple projects, prioritize tasks, and meet aggressive deadlines Benefits: Competitive salary and benefits package commensurate with experience and expertise Opportunity to lead and influence the verification of cutting-edge technologies Dynamic and challenging work environment with opportunities for professional growth and leadership development Recognition and rewards for outstanding contributions

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: As a Design Verification Engineer, you will be responsible for verifying complex SoC designs, working closely with design teams to ensure robust and high-quality products. You will employ advanced verification methodologies and tools to identify and resolve issues, ensuring that our SoC designs meet industry standards and customer requirements. Responsibilities: 1. Develop and execute comprehensive test plans to verify the functionality of SoC designs. 2. Create and maintain verification environments using advanced verification techniques, such as UVM, SystemVerilog, and assertion-based methodologies. 3. Collaborate with design teams to debug and resolve functional issues in RTL and gate-level simulations. 4. Ensure thorough verification coverage by analyzing and improving functional coverage metrics. 5. Perform regression testing to ensure consistent performance and reliability across design iterations. 6. Work closely with architects and designers to understand design specifications and refine verification strategies. 7. Develop reusable verification components and ensure alignment with project timelines and quality standards. 8. Document verification results, generate detailed reports, and present findings to stakeholders. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 3+ years of experience in SoC design verification within the VLSI domain. 3. Expertise in advanced verification methodologies, including UVM and SystemVerilog. 4. Strong understanding of SoC architectures, protocols, and interfaces (e.g., AXI, PCIe, USB, DDR). 5. Proficiency with simulation tools such as VCS, ModelSim, or Questa. 6. Experience with scripting languages (Python, Perl, TCL) for automation. 7. Familiarity with version control systems like Git. Excellent debugging and problem-solving skills, with a focus on delivering high-quality results. 8. Strong communication and collaboration skills to work effectively with cross-functional teams. Preferred Qualifications: 1. Experience with formal verification tools and techniques. 2. Familiarity with low-power verification strategies. Knowledge of hardware-software co-verification. 3. Exposure to machine learning or AI-based approaches in verification. Why Join Us? 1. Work on state-of-the-art SoC designs in a collaborative and innovative environment. 2. Opportunity to be part of a fast-growing company shaping the future of VLSI solutions. 3. Competitive compensation, professional growth opportunities, and a supportive work culture. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future !

> If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74916 Responsibilities Digital design specification, design, analysis, and HDL (Verilog) coding Behavioral modeling of analog and mixed signal circuits Digital back-end: synthesis, physical implementation (prep for PR), static timing, scan insertion, etc. Verification of digital sub-systems, mixed-signal sub-systems, and the entire chip using a combination of digital models/RTL, firmware, and behavioral models. Test bench development Validation of silicon functionality, behavior, and performance Required Experience and Skills Masters with 7-10 years of IC design experience or PhD with 4-6 years of IC design experience Strong motivation to contribute to all facets of chip design from conceptualization to release to production Working knowledge of digital IC circuit design in an HDL synthesis environment Working knowledge of digital verification and testing techniques Good verbal and written communication skills, positive attitude, desire to learn, and willingness to work on a team Working knowledge of UNIX operating systems Additional skills (one or more of these are highly desirable): Experience with digital design at geometries ranging from 130-40 nm Experience with digital IO interfaces such at I2C, SPI, etc. Competence in high-level languages (e.g. Matlab, C), scripting languages (e.g. Tcl, Perl, Python, SKILL), and version control systems (e.g. SVN, SOS) Working knowledge of System Verilog and/or UVM Experience leading a team of digital designers, either formally or informally Experience with embedded processor design and firmware/software development, especially for 8051 or ARM cores Competence in exploring digital and firmware system/architecture trade-offs such as memory size (ROM, RAM, FLASH, OTP, cache), clock speed, multiple clock domains, and the necessity for dedicated logic and DSP Experience with memory generators and MBIST Low power design and implementation techniques Familiarity with DSP techniques and algorithms Experience with Phase-locked-loops, Frequency Synthesizers or CDR circuits. Desired Experience and Skills Job Segment: Electrical Engineering, Testing, Embedded, Firmware, Network, Engineering, Technology

MTS/SMTS SILICON DESIGN ENGINEER THE ROLE: The Infinity Fabric transport layer verification team is looking for an experienced pre-silicon verification engineer to help verify our configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed across Client, Server, Graphics, and Semi-Custom markets. Our growing team needs additional senior engineering experience to help us enhance our configurable testbench and to mentor junior engineers. THE PERSON: The preferred candidate will have proven experience verifying complex design blocks at the IP, Sub-system or SoC level using System Verilog/UVM or related technologies. He or she should be comfortable creating and executing on test plans in collaboration with design and verification colleagues in a metric-focused environment. KEY RESPONSIBILITIES: Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects. Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture. Understand TestBench Architecture and develop expertise in TestBench Verification Components. Mentor junior engineers. PREFERRED EXPERIENCE: Proficient in IP or Sub-system level ASIC verification Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar. Exposure to RTL design, software development, formal verification, or other related domains. Experience in UVM TestBench Development for complex designs preferred. Experience in RAL is preferred ACADEMIC CREDENTIALS: Bachelor s or master s degree in Electronics or Electrical or Computer engineering #LI-RR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance .

BSEE and at least 5 years of prior experience are required. MSEE and at least 3 years of previous experience are strongly preferred. Prior experience in timing and or RTL design of high-speed interfaces. Prior experience collaborating with Physical Design teams in multiple successful ASIC/IP Tape Outs. Knowledge of the IP/SoC level timing closure flow and methodology. Strong command of Verilog/System Verilog language. Strong command of simulation, lint, synthesis, STA, formal verification, functional coverage, design for test, and design methodologies. Ability to handle multiple projects/tasks successfully. Experience in IP/ASIC timing constraints generation and timing closure. Expertise in STA tools and flow. Hands-on experience in timing constraints generation and management. Proficiency in scripting languages (TCL and Perl). Familiarity with synthesis, logic equivalence, DFT and backend-related methodology and tools. Capability to understand and implement improvements to existing methodologies and flows. Strong background in Constraint analysis and debugging, using industry-standard tools. Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, at speed and Best testing. Team player with a passion for innovating and a can-do attitude. Self-starter and highly motivated. Desired Skills : Knowledge of DDR/GDDR DRAM protocol; high-speed PHYs. Experience designing or integrating IP. Experience in high-speed and low-power digital design using advanced deep-micron processes. Experience with highly configurable designs

We HCL TECH are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 2-10 years of solid experience in Design Verification for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package commensurate with experience Opportunity to work on leading-edge technologies and projects with a high impact Collaborative and dynamic work environment that fosters continuous learning Potential for professional development and career advancement

JD : Must have skills. Payment Domain Expertise, MUST - Knowledge on MT and MX Message, Basics of SQL, and Java Specific skillset on MTS and UPF knowledge. Payment domain expertise, knowledge on MT and MX messages Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. Job Description - Grade Specific JD : Must have skills. Payment Domain Expertise, MUST - Knowledge on MT and MX Message, Basics of SQL, and Java Specific skillset on MTS and UPF knowledge. Payment domain expertise, knowledge on MT and MX messages Skills (competencies) Verbal Communication

Develop RTL (Verilog/SV) per microarchitecture specs, integrate IPs, perform lint/CDC, support synthesis. Strong in digital design, AMBA (AXI/AHB), low-power (UPF), TCL/Python. Tools: DC, Genus, SpyGlass. Collaborate on debug & reviews.

Siemens EDA, a part of Siemens Digital Industries Software, is a global technology leader in electronic design automation. Our technologies enable companies around the world to develop new, highly innovative electronic products faster and more cost-effectively. Our customers use our solutions to push the boundaries of technology to deliver better products in the increasingly complex world of chip, board, and system design. Listener, Understander, Doer. Customers around the world trust in our products and our application engineers significantly contribute to that. You are the first on the scene to tackle any technical problem. You are a competent adviser, team player, and make things possible. Unsolvable is a foreign term, and you dont do unfair. Your focus on the customers needs makes you an invaluable partner. When you join our team, you will reach one hundred percent in your career. As an integral part of the technical team, you will contribute to Siemens EDA by increasing productivity and customer satisfaction Siemens EDAs Verification platform. This is an ambitious position that will assist in growing Siemens's business in India. Your new role: results-oriented and futuristic You will be working collaboratively with customers as well as customer support and engineering teams to optimally deploy Siemens EDAs Questa products and services. Youll fosters a climate conducive to help grow customer satisfaction with Siemens tools by helping them successfully deploy new flows and methodologies. Optionally mentor and lead a team of application engineers, supervise and guide them on the accounts and engagements that they are working on. Youll be working with customers with varying design styles and methodologies to craft the most effective technical solutions. Youll provide key expert advice and contribute to technical campaigns in other regions. Identify and qualify potential new business opportunities and work the account teams to build an engagement plan. Work with Account Managers and the world-wide teams for forming strategies and driving Siemens tools for customer projects to enable business success for Siemens EDA. Become a trusted advisor to your customers. Will have moderate travel within India and abroad We are not looking for superheroes, just super minds Youre a Graduate / Post Graduate (Bachelors/Masters) Electronics and Communication (E&C) / Electrical / Telecom Engineering / Computer Engineering with 4 - 10 years of meaningful experience in Digital design and Clock Domain Crossing or Lint EDA tools. Youve solid understanding on VHDL/Verilog, SystemVerilog and Assertions. Well versed with Multiple Clock and Reset Domains and Asynchronous clock or reset domain crossing verification ( Clock Domain Crossing - CDC & Reset Domain Crossing - RDC ) on designs Expertise in CDC tools like Questa/0in CDC, Spyglass or VC- CDC, or other CDC products is expected Expertise in Formal Verification products like Questa Formal, Jasper or any other Formal products is a plus Low power verification techniques using UPF and CPF is a plus Exposure to static timing analysis (STA) flows involving SDC is a plus

Arm s hardware is at the heart of the computing and connectivity revolution that continues to transform the way people live and businesses operate. As we continue to grow, we need the best engineers to join a team responsible for the development of sophisticated Subsystems and Solutions. Soon, we could be using your talents to develop the technologies that will enable the latest compute solutions in todays Enterprise, Auto and Client markets. Responsibilities: As a verification engineer with a knowledge of subsystems and SoCs you will make valuable contributions to a team tasked with verifying the functional correctness of SoC. Engineers will have ample opportunities to collaborate with designers and architects to understand design specifications and build a functional verification strategy. Key responsibilities will include writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules. Work with the Emulation/FPGA team in understanding various verification collaterals required for driving stimulus at the board level. Work with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, FPGA and board development. Senior engineers are also encouraged to support junior members. Required Skills and Experience : 8+ years of proven experience in working on IP/Subsystem/Soc Verification Experienced in Protocol on Flash Storage device Controller with unipro and MIPI PHY. Experience in Working on any of cross functional flows like Reset, Ras(Error and Interrupt), Security, low Power for High-speed IO IPs. Good Skills in System Verilog, shell programming/scripting (eg Tcl, Perl, Python etc) Experienced in one or more of various verification methodologies UVM, formal and low power. Exposure to all stages of verification: requirements collection, creation of test plans, testbench implementation, test cases development, documentation, and support. Experience with various front-end verification tools - Dynamic simulation tools, Static Simulation tools and Debuggers. Nice To Have Skills and Experience : Possess knowledge of object-oriented programming concepts Practical experience of working on Processor based system design Experience in Server/ Infrastructure SoC Strong understanding of CPU Architecture / micro-architectures! In Return: We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together. These behaviors are assessed as part of the hiring process: Partner and customer focus Collaboration and communication Creativity and innovation Team and personal development Impact and influence Deliver on your promises We offer a hybrid approach to home and office working to provide an adaptable experience for all employees. We expect some working time to be spent in office, to promote a strong collaborative environment with good team integration but are accommodating to different home working requirements.

Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies, with a particular focus on achieving high-efficiency power conversion for applications using GaN devices. Job Description Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies , with a particular focus on achieving high-efficiency powerconversion for applications using GaN devices. D esign and verify pre-silicon analog/mixed-signal integrated circuitblocks , including incorporating features for testing and quality assurance, and providing support for top-level integration. Assist in defining the requirements for analog and mixed-signalblocks , aligning them with IP Module architecture, and ensuring compliance with requirements through documentation. Estimate effort and planning design work packages to meet project milestones. Provide essential support to physical design engineers, post-silicon verification, production testing , and other critical activities extending beyond the design phase. You are best equipped for this task if you have: A masters degree in electrical/Electronic Engineering, Physics or equivalent field of studies. Experience in analog and mixed-signal circuit design, particularly in CMOS and Smart Power Technologies. Good Analytical skills and very good understanding of Analog Design. Familiarity with high-efficiency power conversion, such as DC-DC converters, is highly desirable. Experience in pre-silicon verification and with System Verilog would be a plus. Proficiency in computer-aided design tools and methodologies. Excellent problem-solving and communication skills. Ability to work effectively in a collaborative team environment. Detail-oriented with a commitment to quality and precision. Fluency in English

Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies, with a particular focus on achieving high-efficiency power conversion for applications using GaN devices. Job Description In your new role you will: Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies , with a particular focus on achieving high-efficiency power conversion for applications using GaN devices. Design and verify pre-silicon analog/mixed-signal integrated circuit blocks , including incorporating features for testing and quality assurance, and providing support for top-level integration. Assist in defining the requirements for analog andmixed-signal blocks , aligning them with IP Module architecture, and ensuring compliance with requirements through documentation. Estimate effort and planning design work packages to meet project milestones. Provide essential support to physical design engineers,post-silicon verification, production testing , and other critical activities extending beyond the design phase; Your Profile You are best equipped for this task if you have: A masters Degree in Electrical/Electronic Engineering, Physics or equivalent field of studies. Experience in analog and mixed-signal circuit design, particularly in CMOS and Smart Power Technologies. Good Analytical skills and very good understanding of Analog Design. Familiarity with high-efficiency power conversion, such as DC DCconverters, is highly desirable. Experience in pre-silicon verification and with System Verilog wouldbea plus. Proficiency in computer-aided design tools and methodologies. Excellent problem-solving and communication skills. Ability to work effectively in a collaborative team environment. Detail-oriented with a commitment to quality and precision. Fluency in English

Digital Logic Design: Strong expertise in digital logic design with hands-on experience in RTL coding using Verilog and SystemVerilog. Peripheral Design: Experience in designing high-speed and low-speed peripherals. Design Optimization: Understanding of synthesis, timing constraints, clock domain crossing (CDC), and logic optimization techniques. Low Power Design: Exposure to low power design techniques, including working with multiple power and clock domains will be advantage. Protocol Knowledge: knowledge of protocols such as PCIe, DDRx, Ethernet, USB, AXI, AHB, APB, I2C, and SPI will be preferred. Expectations from the Role: Communication & Independence: Excellent communication and interpersonal skills, with the ability to work independently. Adaptability: A fast learner who can efficiently operate in a distributed work Initiative & Punctuality: Demonstrates ownership, initiative, and punctuality in all

#Hiring FPGA Design Engineer Exp-5- 8Years Notice Period- 0 to 15Days Location- Bangalore Job Description: RTL and FPGA design, implementation, and timing closure using Xilinx & Synopsys development tools. Bring up and validate the design in the lab and generate test reports. Perform hardware validation tasks and debug IPs. Read, understand, and modify software drivers and scripts. Skills RTL Design & FPGA Implementation: Verilog, System Verilog, Vivado , ISE, Synplify, Design Compiler FPGA Platforms: Xilinx 7-series, Ultrascale/Ultrascale+, Zynq Toolchain Expertise: Xilinx Vivado, Synopsys DC/PT, ModelSim, VCS Hardware Validation: Bitstream generation, on-board debugging, performance tuning Lab Equipment: Oscilloscopes, logic/protocol analyzers, JTAG debuggers Software & Scripting: C, C++, Python, Perl, TCL, Bash Operating Systems: Linux (device driver understanding), embedded systems Interested candidates share your resume to sreeja.s@sasnee.com ,

Educational requirement Bachelor or Masters in EE/ECE/CS or related specializations with 3+ years of relevant experience.Strong in UVM/System Verilog/C/C++/scripting, Simulation, Formal verification. Good understanding of SoC architectures Required Candidate profile GLS verification experience at Core level. SV - UVM understanding. Scripting in perl, python. Debug of complicated designs using Verdi. Power aware verification, SDF / timing simulation.

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environment' s Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment . Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience . Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions . ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Position: RTL Verification Experience: 5+ Years Location: Hyderabad Skill Required: System Verilog and UVM, HW Testing, PCIe/SPI/I2C/, Perl, Python or TCL If interested to send your updated resume to irfanai@canvendor.com / reach out to 9585544407