440 Physical Design Jobs - Page 5

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com . Job Description The position involves design verification of next generation modem sub systems (which has MAC, Baseband and RF IP s involved for latest Wi-Fi protocol including 11ax) with emphasis on verifying and signing off performance and power along with functionality. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS and Formal techniques. Candidate will require close interactions with Design, SoC , Validation, Synthesis & PD teams for design convergence. Candidate must be able to take ownership of IP/Block/SS verification. He/She will work with design team (both HW and SW) on RTL debug during Pre-silicon HW development phase. Responsibilities: Develop and execute verification plans using SystemVerilog and UVM to validate complex ASIC/FPGA designs. Design and implement testbenches and verification environments to ensure functional accuracy and performance. Perform Gate-Level Simulations (GLS) to validate designs against their RTL implementations. Create and run comprehensive verification scenarios and identify discrepancies between RTL and gate-level simulations. Collaborate with design engineers to understand requirements and resolve design issues. Debug and troubleshoot complex issues, providing detailed analysis and solutions. Document verification processes, methodologies, and results to ensure clarity and reproducibility. Participate in design reviews and contribute to improving verification strategies and methodologies. Verify and debug low-power design Debug SDF Back Annotated Gate Simulations Collaborate with cross-functional teams to define and execute gate-level simulation test plans. Develop and implement gate-level simulation strategies for complex digital designs. Conduct gate-level simulations to verify the functionality and performance of digital designs. Work closely with design and verification teams to identify and resolve issues at the gate level. Utilize your expertise in SV and UVM to optimize and enhance the gate-level simulation process. Ensure compliance with industry standards and best practices in gate-level simulation. Develop a comprehensive GLS methodology for the CPU Perform gate-level simulations to verify the functionality, performance, and timing of CPU designs. Develop and execute comprehensive test plans for gate-level simulations. Collaborate with RTL design, verification, and physical design teams to identify and resolve simulation issues. Analyze simulation results, debug failures, and propose design improvements. Ensure thorough coverage and validation of all critical paths and corner cases. Automate simulation workflows to enhance efficiency and reproducibility. Assist in the development and maintenance of simulation environments and tools. Document simulation methodologies, results, and best practices. Understanding of industry-standard protocols and interfaces Familiarity with static timing analysis (STA) and power analysis. Understanding of power domains and HW programming guide sequences Develop test plan to verify all low power states Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals Exploring innovative dynamic or static methodologies by engaging with EDA vendors Experience Level: 6-8 years in Industry Education Requirements: Bachelor or Master s degree in Electrical and/or Computer Engineering Minimum Qualifications: 6-8+ years of professional experience in ASIC/FPGA verification with strong expertise in SystemVerilog, UVM, and Gate-Level Simulation (GLS). Proven experience in developing and executing testbenches and verification environments. Strong skills in performing gate-level simulations and analyzing results. Excellent debugging skills with the ability to resolve complex design issues. Effective communication and collaboration skills, capable of working well in a team environment. Analytical debugging skills Verify and debug low-power design Debug SDF Back Annotated Gate Simulations Low-power implementation (UPF) Mixed Signal Real Number Modeling (RNM, Spice) Strong System Verilog/UVM based verification skills Experience with Assertion coverage-based verification methodology Experience in formal / static verification methodologies will be a plus Good understanding of low power design techniques Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells. Experience with UPF/CPF based power aware verification. Experience with Synopsys NLP (native Low Power) tool. Working knowledge of GLS , PAGLS and scripting languages such as Perl, Python is a plus Proficiency in Low-Power standards like UPF/CPF. Working knowledge on UPF based RTL / PGPIN simulations. Proficiency in ASIC design tools, simulation methodologies, and hardware description languages (HDLs). Excellent analytical and problem-solving skills with a focus on power optimization Preferred Qualifications: Mentoring skills Exceptional problem-solving skills Good written and oral communication skills Benefits & Perks : Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

Job Responsibilities : Process & quality monitoring for respective technology plants Identify and analyse deviations Perform root cause analysis Propose corrective action and track the status of process improvement Identify opportunities for profit improvement Identify opportunities for product quality enhancement Process design calculations for the improvement schemes Develop process design package using appropriate tools Participate in commercial plant trials Understand and evaluate basic engineering design documents Participate in plant performance audits as per set guidelines Participate in Critical PHAs and turnaround activities of the related plants Validate MoCs to ensure specified standards and codes are followed in calculations Support preparation of stage gate-2 and 3 document for Capital projects Participate in HAZOP of new projects Validate equipment data sheets prepared by engineering contractor Contribute to derive value from technology network Education Requirement : BE/B Tech in Chemical Engineering from a reputed institute Experience Requirement : 4 years of experience with at least 2 years in plant Operations / CTS Skills & Competencies : Analytical ability for problem solving Programming exposure Knowledge of chemical engineering and process technology Ability to plan / discuss results and network under the guidance of a senior colleagues Process design calculations at Skill level Use of process calculation templates at Skill level Simulation skills Use of Six sigma for problem solving Good communication skills Leadership quality with management skills Result Orientation

With this position you will be in our Technical Ladder: a special career path for those who share innovative ideas, demonstrate comprehensive technical knowledge, show thought leadership, possess problem solving abilities and are able to create business value, Job Description In your new role you will: Contribute to highly complex designs in a multi-site organization covering all aspects of Structural and Physical SoC Design Be responsible for the physical design of multifarious digital SoCs Translate requirements into layout specifics using our state-of-the-art EDA tools and flows Work independently in different phases of the RTL2GDS flow: With focus on (one or many) Synthesis and equivalence check, generation of Floorplans, Placement, Clock Trees, Routing and Power Distribution Network for efficient Timing Closure with Signal Integrity and physical Sign off including Power Integrity Take physical limitation of hierarchical deep sub-micron designs into account and timely implement suitable solutions to overcome implementation issues, Tap your experience to contribute s Your Profile You are best equipped for this task if you have: A degree in Electrical Engineering, Microelectronics or a similar field At least 3-5 years of working experience in Physical Design of highly complex SoCs with sound experience in Synthesis, Place & Route and Timing Closure and involvement in FINFET technologies Know-how in technical leadership in physical design projects Sound programming skills and knowledge in scripting languages like Tcl, Perl or Python Basic experience in RTL coding Understanding of Functional Safety will be a benefit Fluent English language skills with German being an added plus Contact: Gowri Shenoy, LinkedIn #WeAreIn for driving decarbonization and digitalization, As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals Be a part of making life easier, safer and greener, Are you in We are on a journey to create the best Infineon for everyone, This means we embrace diversity and inclusion and welcome everyone for who they are At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities We base our recruiting decisions on the applicant?s experience and skills, Please let your recruiter know if they need to pay special attention to something in ord

Job Responsibilities : Education Requirement : Experience Requirement : Skills & Competencies : Work Output Define project charters and implementation plan, Develop project proposal for management approval & budget Manage projects within allocated budget & resources available, Coordinate with key stakeholders at sites for implementation & embedding of the new process/system, Coordinate with partner/vendor for project execution Actively contribute in managing Knowledge Assets, Evaluate information gathered through workshops & surveys and incorporate in process description, Identify the competitive commercial solution for recommendation, Communicate with internal teams & external clients to deliver functional requirements like GUI, screen, and interface designs, Review process automation documents Plan & schedule end user trainings, Address/resolve application related issues faced by customers, Translate usability and field implementation findings into design improvement Other: Stay updated with the latest automation technologies Analyse & provide necessary up gradation / modification plan to existing automation systems, Co-development with the vendor, technology providers Audit of existing automation facilities and processes, Data Management Collect and analyse data for automation systems, Standardization of reports / templates, Customized reports, Create SOPs/other documents HSE & Other Regulatory Compliance: Carry out risk assessment studies prior to implementation, Follow and enforce applicable HSE procedures/practices Display awareness and compliance of site, statutory, IP and RIL IT regulations Min BE/B Tech in Chemical Engineering from a reputed institute Min 4 years of experience with at least 2 years in plant Operations / CTS Should have aptitude/flair for working with automation systems Analytical ability for problem solving and programming exposure, Flair to learn new technologies, Good awareness of P&ID, PFD, Instrumentation and control systems Good knowledge of at least 1-2 unit operations / processes, Good communication skills Leadership quality with management skills Result Orientation Business Process driven outlook Knowledge of office automation packages

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL design, verification, and DFT teams to ensure seamless integration and sign-off. 4. Debug and resolve issues related to timing, signal integrity, and power. 5. Drive closure of physical verification issues such as DRC, LVS, and ERC. 6. Implement low-power design techniques, including power gating, multi-Vt optimization, and dynamic voltage scaling. 7. Work closely with EDA tool vendors to improve design flows and methodologies. 8. Generate and maintain comprehensive documentation for physical design flows and guidelines. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 2. 3-10 years of experience in physical design for VLSI systems. 3. Proficiency in physical design tools such as Cadence Innovus, Synopsys ICC2, or Mentor Calibre. 4. Strong knowledge of STA tools like PrimeTime, Tempus, or equivalent. 5. Experience with advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 6. Expertise in low-power design techniques and methodologies. Solid understanding of DRC/LVS and parasitic extraction. 7. Familiarity with scripting languages (Python, TCL, Perl) for flow automation. 8. Excellent problem-solving skills with the ability to debug and resolve complex physical design challenges. 9. Strong communication and collaboration skills to work effectively in cross-functional teams. Preferred Qualifications: 1. Hands-on experience with hierarchical design flows and methodologies. 2. Knowledge of 3D IC and advanced packaging technologies. 3. Familiarity with machine learning or AI applications in physical design optimization. 4. Exposure to hardware security aspects in physical design.

DFT Implementation: Strong expertise in implementing DFT architectures, including Scan Insertion, ATPG (Automatic Test Pattern Generation), and MBIST/ LBIST for SoC designs. Test Coverage Optimization: Experience in optimizing test coverage while minimizing test cost and pattern volume. Scan & Compression Techniques: Proficient in scan chain design, scan compression techniques, and reducing test data volume. Boundary Scan (IEEE 1149.1): In-depth knowledge of boundary scan standards and Fault Models: Familiarity with various fault models (stuck-at, transition, path delay, etc.) and their application in test generation. DFT Tools: Hands-on experience with DFT tools like Synopsys TetraMAX, Mentor Graphics Tessent, Cadence Modus, etc. Scripting & Automation: Proficiency in scripting languages (e.g., Perl, Python, TCL) for Sign-Off: Experience with DFT sign-off procedures, including coverage analysis, vector generation, and fault simulation. Post-Silicon Validation: Knowledge of silicon bring-up, ATE (Automatic Test Equipment), and post-silicon validation techniques. Expectations from the Role: Technical Expertise: Demonstrated expertise in DFT methodologies, with the ability to implement robust DFT solutions across complex SoC designs. Problem-Solving: Strong analytical and problem-solving skills, particularly in diagnosing and resolving DFT-related issues. Collaboration: Effective communication and teamwork skills, with the ability to work closely with RTL designers, verification teams, and physical design teams. Innovation: Ability to innovate and improve existing DFT methodologies, driving advancements in test coverage and efficiency. Attention to Detail: High attention to detail, ensuring that all test structures are correctly Project Management: Ability to manage multiple projects, prioritize tasks effectively, and ensure timely delivery of high-quality DFT solutions.

Physical Design Implementation: Experience in block and SoC level PD implementation, covering the entire flow from netlist to GDSII, including PnR/APR. Low Power Design: Proficient in low power design techniques. Flow Expertise: Hands-on experience with floorplanning, power planning, placement, CTS (Clock Tree Synthesis), routing, extraction, and DFM (Design for Analysis Skills: Strong ability to perform congestion and timing analysis, with a focus on achieving better QoR (Quality of Results). Sign-Off Expertise: In-depth knowledge of sign-off processes including STA (Static Timing Analysis), DRC/LVS/Antenna/ERC checks, power analysis, IR/EM analysis, LEC (Logic Equivalence Checking), and ECO (Engineering Change Order) for both Process Knowledge: Comprehensive understanding of the entire physical design process from RTL to GDSII, encompassing floorplanning, placement, CTS, routing, and sign-off stages. ECO Implementation: Experience in implementing ECOs. PnR Tools: Hands-on experience with PnR tools such as Synopsys ICC II and Scripting Skills: Proficient in scripting languages like Perl and TCL, with experience using various EDA tools. Expectations from the Role: Debugging & Problem-Solving: Excellent debugging and problem-solving skills, with the ability to tackle complex design issues. Communication: Effective communication skills for interacting with all Focus & Commitment: Must be highly focused and committed to achieving project goals and closing out tasks. Independence: Ability to work independently and manage tasks with minimal Leadership: Possesses strong leadership skills with a proactive, go-getter attitude.

BSEE and at least 5 years of prior experience are required. MSEE and at least 3 years of previous experience are strongly preferred. Prior experience in timing and or RTL design of high-speed interfaces. Prior experience collaborating with Physical Design teams in multiple successful ASIC/IP Tape Outs. Knowledge of the IP/SoC level timing closure flow and methodology. Strong command of Verilog/System Verilog language. Strong command of simulation, lint, synthesis, STA, formal verification, functional coverage, design for test, and design methodologies. Ability to handle multiple projects/tasks successfully. Experience in IP/ASIC timing constraints generation and timing closure. Expertise in STA tools and flow. Hands-on experience in timing constraints generation and management. Proficiency in scripting languages (TCL and Perl). Familiarity with synthesis, logic equivalence, DFT and backend-related methodology and tools. Capability to understand and implement improvements to existing methodologies and flows. Strong background in Constraint analysis and debugging, using industry-standard tools. Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, at speed and Best testing. Team player with a passion for innovating and a can-do attitude. Self-starter and highly motivated. Desired Skills : Knowledge of DDR/GDDR DRAM protocol; high-speed PHYs. Experience designing or integrating IP. Experience in high-speed and low-power digital design using advanced deep-micron processes. Experience with highly configurable designs

Technical Skill Set - SOC level Floor Plan, PNR, IO Ring Design, Timing Closure, Physical Verification, Power planning and analysis, ECOs on 7nm and 10nm technology nodes. Must-Have Hands-on experience on Full chip floor plan, Full chip PNR, and Design Partitioning. Hands-on experience in IO Planning, Bump Plan and RDL Routing. Experience in ECOs, Synthesis and STA, and Power analysis. Hands-on experience in Physical verification. Hands-on experience on 7nm and 10nm technology nodes. Good-to-Have Effective communication skills to interact with cross-functional teams.

Role & responsibilities Those who had a chance to work on CPU, GPU and / or NPU would be better on 3 or 5 nm Technology . Experience Levels would 4-8 years.

Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies, with a particular focus on achieving high-efficiency power conversion for applications using GaN devices. Job Description Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies , with a particular focus on achieving high-efficiency powerconversion for applications using GaN devices. D esign and verify pre-silicon analog/mixed-signal integrated circuitblocks , including incorporating features for testing and quality assurance, and providing support for top-level integration. Assist in defining the requirements for analog and mixed-signalblocks , aligning them with IP Module architecture, and ensuring compliance with requirements through documentation. Estimate effort and planning design work packages to meet project milestones. Provide essential support to physical design engineers, post-silicon verification, production testing , and other critical activities extending beyond the design phase. You are best equipped for this task if you have: A masters degree in electrical/Electronic Engineering, Physics or equivalent field of studies. Experience in analog and mixed-signal circuit design, particularly in CMOS and Smart Power Technologies. Good Analytical skills and very good understanding of Analog Design. Familiarity with high-efficiency power conversion, such as DC-DC converters, is highly desirable. Experience in pre-silicon verification and with System Verilog would be a plus. Proficiency in computer-aided design tools and methodologies. Excellent problem-solving and communication skills. Ability to work effectively in a collaborative team environment. Detail-oriented with a commitment to quality and precision. Fluency in English

Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies, with a particular focus on achieving high-efficiency power conversion for applications using GaN devices. Job Description In your new role you will: Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies , with a particular focus on achieving high-efficiency power conversion for applications using GaN devices. Design and verify pre-silicon analog/mixed-signal integrated circuit blocks , including incorporating features for testing and quality assurance, and providing support for top-level integration. Assist in defining the requirements for analog andmixed-signal blocks , aligning them with IP Module architecture, and ensuring compliance with requirements through documentation. Estimate effort and planning design work packages to meet project milestones. Provide essential support to physical design engineers,post-silicon verification, production testing , and other critical activities extending beyond the design phase; Your Profile You are best equipped for this task if you have: A masters Degree in Electrical/Electronic Engineering, Physics or equivalent field of studies. Experience in analog and mixed-signal circuit design, particularly in CMOS and Smart Power Technologies. Good Analytical skills and very good understanding of Analog Design. Familiarity with high-efficiency power conversion, such as DC DCconverters, is highly desirable. Experience in pre-silicon verification and with System Verilog wouldbea plus. Proficiency in computer-aided design tools and methodologies. Excellent problem-solving and communication skills. Ability to work effectively in a collaborative team environment. Detail-oriented with a commitment to quality and precision. Fluency in English

You have a passion for modern, complex processor architecture, digital design as we'll as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem-solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi site environment are keys to being successful in this role. KEY RESPONSIBILITIES: RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design Architect and design of power management features, cache, coherency. Design optimization for implementing power efficient IP, implementing the RTL using low power techniques Responsible for the inter IP integration issues resolution Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem. Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design Architecting, micro-architecting and documentation of the design features Lead design team from all aspects of the RTL deliverables. Mentor the junior members of the RTL team to meet the team goals Represents AMD to the outside technical community, partners and vendors Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. PREFERRED EXPERIENCE: 12+ years of experience in Digital IP/ASIC design and Verilog RTL development Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification. Should be we'll versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation. Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects. Should possess expertise in front-end EDA tools sign-off and its flows. Familiarity with low power design and low power flow is an added plus. Ability to program with scripting languages such as Python or Perl is a plus; Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements; Proven interpersonal skills, leadership and teamwork; Excellent writing skills in the English language, editing and organizational skills required; Skilled at prioritization and multi-tasking; Good understanding of engineering terminology used within the semiconductor industry; Good understanding of digital design concepts; Knowledge of, or experience in, functional design verification or design is highly desired. ACADEMIC CREDENTIALS: masters degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or VLSI design Engineering.

As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience ( eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc .) Experience with Mentor testkompress and/or Synopsys Tetramax /DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

ARF Design Pvt Ltd is looking for Physical Design Engineer/Lead to join our dynamic team and embark on a rewarding career journey The Physical Design Engineer is responsible for designing and implementing the physical layout of integrated circuits (ICs) using industry-standard tools and methodologies Participate in design reviews and provide input on design trade-offs, performance targets, and optimization strategies Excellent communication and collaboration skillsStrong analytical and problem-solving skillsFamiliarity with scripting languages, such as Tcl, Perl, or Python

: We are looking for a highly skilled & experienced PD expert to join our Flows & Methodologies team. The candidate must be experienced, hands-on and have robust understanding of physical design including Floorplan, Power-plan, Place & Route, UPF, CTS. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope of Responsibilities: As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define Physical Design methodology to meet SoC & IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools and flows definition, requirement management for SoC Place & Route, UPF, Formal Verification, Floorplan & Power-Plan You will work with EDA Vendors to proactively review latest tools and flows offerings in Physical Implementation domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies. Work with EDA Vendors to review and resolve blocking issues You will be an actor of change for deploying new tools & methodologies across the organization Qualifications Specific skills & knowledge : Bachelor or Master or Ph. D. in Electronics Engineering and specialization in VLSI domain 10+ years of hands-on experience in Physical Design : UPF, Formal & Physical verification, floorplan, power-plan, Place & Route Proven experience in delivering physical implementation closure methodology ensuring timing & physical convergence Experience in Synopys & Cadence tool sets (Fusion Compiler, Innovus) , low geometry node issues, working with EDA team in reviewing & resolving blocking issues in project Experience in customizing flows & methodology to meet low power & area objectives of SoC Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can - do attitude, openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team

Roles and Responsibilities Good experience in PD execution of multiple medium to High critical blocks/HMs from Netlist to GDSII Develop and qualify the methodology and implementation flow in advanced technologies like 14nm and below. Well versed with FC/Innovus tools and good understanding of place/cts/Route critical settings Develop expertise in ASIC Synthesis, Floor Planning, STA (Static Timing Analysis), and other relevant technologies. Good experience in Low power designs Conduct thorough analysis of designs to identify potential issues and implement solutions. Perform physical design activities including floor planning, PNR (Physical Netlist) creation, and timing closure using Innovus tools. Interested candidates can contact me at shubhanshi@incise.in

Your Job The engineer will be responsible for doing physical design implementation, timing closure, and Physical verification at the block level. Job Responsibilities Execute block-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Need experience in full chip physical design such as integration of blocks, top level floorplanning, clock tree synthesis, timing constraints development and convergence. I/O placement and constraints. Experience with UPF coding and modification as per design requirements. Need to take care of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out. Should be able to interface with the Front End Design team to resolve Design Issues Must possess hands on experience in P&R from RTL to GDS including timing closure and Physical verification. Design experience in all aspects of physical design. Proficient and powerful user of Synopsys ICC/ICC2, Cadence innovus. Experience in Mentor Calibre tools to run Physical verification Experience in Apache to run EM IR- analysis is a Plus. Experience in Tcl/ Tk, PERL, Makefile is a Plus Excellet verbal and written communication skill is required. Excellent interpersonal and analytical skills with an ability to work independently and within a team are required. Highly motivated, excellent team player, and customer oriented. Experience 4-6 Years of Physical Design Experience Qualification Bachelor or Master's degree in Electrical and Electronics engineering. Required Skills And Qualification Good understanding of low power concepts. Good exposure in Floorplanning, CTS, STA, Physical Verification. Good understanding of top-level physical design, partitioning and timing constraints, IR Drop. Basic understanding of timing constraints. Knowledge in Automation script (TCL, Perl, etc), Auto FuSA would be an added advantage.

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

- Lead the architecture, design and development of Processor Core Vector- Scalar Execution unit for high-performance IBM Systems. - Architect and design Fixed point/Floating point/Vector/SIMD/Crypto instructions of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise - 8 or more years of demonstrated experience in architecting and designing Execution unit of CPU - Hands on experience of implementing Arithmetic/Crypto/SIMD functions - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of instruction dispatch and load/store units - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of one object oriented language and scripting language - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Master's Degree/PhD

BE Mechanical/Electrical with 6-10 years of experience in the Energy/Manufacturing sector/Auto Sector Preferred candidates from high voltage industry Candidates will be responsible for - Procurement from Import and Domestic (Timely placement of PO's, ensuring on time delivery, incoterm, optimizing freight, timely forecasting etc) Procurement of casting ,machining, sheet metal, fabrication, electrical articles & equipment's (CT/VT/Panels etc)for production (assembly) ensuring freight optimization & product cost out for high voltage GIS(Gas Insulated Switchgear) upto 400kv. Inventory management -Ensuring ITR targets Built safety stocks for Delivery, quality critical parts ensuring lead times Initiate & drive cost out measures Explore new suppliers & expedite development Maintain business relationship with all supplier for best outcome Travelling /Visit to suppliers required. (As per business requirement) Excellent Communication skills (Written/Oral)

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime. This role is based in Bangalore. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. This is your role Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution. Work with design community in solving critical designs problems to achieve desired performance, area and power targets. Deployment of Synthesis solution with various customers working on cutting edge technologies (7nm and forward). Develop & deploy training and technical support to customers using Siemens EDA tools. We don’t need superheroes, just superminds! Typically requires minimum of 9+ years of experience in Logic Synthesis flows Proficiency in Verilog, System Verilog & VHDL. Strong knowledge of RTL2GDSII flow with strong fundamentals in digital design & implementation. Prior experience in IC digital design flows and front-end EDAT tools including Synthesis, DFT, Formal Verification, Logic Equivalence Checks Hands-on experience using commercial synthesis tools like Synopsys-DC/FC, Cadence-Genus is a must. Experience with advance technology nodes 7nm and below. Hands-on experience in debug & deliver solutions to critical design issues related to synthesis. TCL, Perl or Python scripting is a plus. Self-motivated team player with a zeal to drive high team performance. Good problem solving and debugging skills. Strong verbal & written communication skills We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-Hybrid

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Position presents an opportunity to join the award winning and market leading Tessent team, India. The focus of the role is advanced design-for-test (DFT) insertion and automatic test pattern generation (ATPG) for semiconductor designs. It will involve understanding and supporting the latest DFT ATPG electronic design automation (EDA) technologies such as Tessent TestKompress and Streaming Scan Network (SSN). Someone in this role will gain a deep understanding of scan design, on-chip clock controls, and IJTAG infrastructure in support of scan testing. They will support the worldwide application engineering team on complex ATPG issues and build testcases for advanced DFT methodologies. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. Responsibilities for this role include: Build and deliver in-depth technical presentations, develop training material, white papers, supplied articles, and application notes. Work with customers as well as Siemens stakeholders such as regional application engineers, global support engineers, and marketing. Are you expertized in working through complex technical issues and independently building solutions and new methodologies! Explain complex principles in simple terms to broad audiences. Some travel, domestic and international. Successful deployment of existing and new Tessent DFT products in customer designs by enabling AEs. Working closely with our key customers on deployment challenges. Working with PEs and R&D to ensure new product readiness testcase in form of testcases, documentation and trainings. Architecture reviews of customer designs. Closely working with AEs to gather top issues blocking their engagement's success. Deep learning opportunities for Tessent DFT products including opportunities to present at various conferences worldwide including ITC and Siemens U2U. We don’t need hard workers, just superminds! BS degree (or equivalent) in Electrical Engineering, Computer Science or related field is required with 10 - 15 years of experience. Knowledge of design logic design languages, tool usage, design flow steps required. We are looking for someone that has exposure to DFT or SoC design for complex ASICs / SOCs. ATPG, IEEE 1687 IJTAG, boundary scan (BSCAN), hierarchical DFT implementation. Knowledge of a scripting language like TCL. We need someone self-motivated and dedication to improvement with strong problem-solving skills. Excellent organizational skills, written and verbal English language communication skills. Proficiency in LINUX and Windows environments. The role presents many opportunities to build specialized DFT and ATPG knowledge. Publications and other promotions of methodologies is encouraged. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-HYBRID

We are seeking a highly skilled and experienced Synthesis and Static Timing Analysis (STA) expert to join our semiconductor team. The ideal candidate will have a strong background in digital design and a deep understanding of synthesis and STA processes. This role involves working closely with cross-functional teams to ensure the successful implementation and optimization of digital designs. Key Responsibilities: Good Understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints Generation, UPF, Timing Closure and Signoff. Develop TCL scripts and design constraints to perform synthesis, DFT insertion, and static timing analysis. Interface for DFT strategy and implementation. Responsible for design convergence in timing and logic equivalence. Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, LEC, VCLP. Knowledge of scripting languages such as Perl, Python, or TCL. Qualifications Exp : 5 to 12 years of experience Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

As a Logic design lead in the IBM Systems division, you will be responsible for the micro architecture, design and development of a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems. Design and architect different interconnect topologies as driven by bandwidth, latency and RAS requirements Develop the features, present the proposed architecture in the High level design discussion Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of relevant experience - At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC). - Expertise of SMP coherency - Experience in different on-chip interconnect topologies (e.g., mesh, crossbar) - Understanding of various snoop and data network protocols - Understanding of latency & bandwidth requirements and effective means of implementation - Working knowledge of queuing theory - numa/nuca architecture - Proficient in HDLs- VHDL / Verilog - Experience in High speed and Power efficient logic design -Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage - Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design - Experience in leading uarch, RTL design teams for feature enhancements.