414 Physical Design Jobs

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL design, verification, and DFT teams to ensure seamless integration and sign-off. 4. Debug and resolve issues related to timing, signal integrity, and power. 5. Drive closure of physical verification issues such as DRC, LVS, and ERC. 6. Implement low-power design techniques, including power gating, multi-Vt optimization, and dynamic voltage scaling. 7. Work closely with EDA tool vendors to improve design flows and methodologies. 8. Generate and maintain comprehensive documentation for physical design flows and guidelines. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 2. 310 years of experience in physical design for VLSI systems. 3. Proficiency in physical design tools such as Cadence Innovus, Synopsys ICC2, or Mentor Calibre. 4. Strong knowledge of STA tools like PrimeTime, Tempus, or equivalent. 5. Experience with advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 6. Expertise in low-power design techniques and methodologies. Solid understanding of DRC/LVS and parasitic extraction. 7. Familiarity with scripting languages (Python, TCL, Perl) for flow automation. 8. Excellent problem-solving skills with the ability to debug and resolve complex physical design challenges. 9. Strong communication and collaboration skills to work effectively in cross-functional teams. Preferred Qualifications: 1. Hands-on experience with hierarchical design flows and methodologies. 2. Knowledge of 3D IC and advanced packaging technologies. 3. Familiarity with machine learning or AI applications in physical design optimization. 4. Exposure to hardware security aspects in physical design.

We are seeking a talented and detail-oriented Physical Backend Design Engineer to join our IC (Integrated circuit) development team. The role involves key aspects of physical design, including automated place and route, floorplanning, clock tree synthesis (CTS), static timing analysis (STA), power analysis, and physical verification (DRC/LVS). The ideal candidate will have a strong knowledge of physical design methodologies, experience with industry-standard tools, and a passion for delivering high-quality semiconductor solutions. You have: Bachelors Degree in Electrical Engineering, Computer Engineering, or a related field (Masters preferred) 3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementation Experience with tape-out of designs for advanced nodes is highly desirable Strong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid design Experience with physical verification tools like Cadence Pegasus or Mentor Calibre Familiarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC) Scripting skills in Python, Tcl, Perl, or Shell for automation Required ToolsCadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite It would be nice if you also had: Experience with advanced process nodes (e.g., 7nm and below) Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gating Familiarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologies Perform floorplanning, partitioning, and optimization to achieve area, power, and performance targets. Execute automated place and route (PnR) using industry-standard tools to generate physical layouts. Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution. Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements. Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks. Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards. Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance. Work closely with foundry teams to address process technology issues and implement best practices.

5 to 7 years experience in both BW and Native HANA Good skills in SQL and ABAP Well versed in Data warehousing concepts Expertise in both BW and ECC back end object development and support Extractors , experience using various SAP & other sources, ADSOs, Composite Providers, DSOs, info cubes, Multi providers, etc. Hands on and technical conceptswith focus on HANA modelling. Proficient in design & development of HANA models Calculation views, procedures, Table functions Shift timings : 2 PM to 11 PM

Role & responsibilities A VLSI (Very Large Scale Integration) Recruiter typically focuses on finding and hiring talent with expertise in semiconductor design, integrated circuit (IC) design, and VLSI technologies. Below are some of the key roles and responsibilities for a VLSI Recruiter position: 1. Talent Acquisition Sourcing Candidates: Actively source candidates for VLSI design roles, including hardware engineers, design engineers, verification engineers, and other related positions within the semiconductor industry. Job Postings: Create detailed job descriptions, post open positions on job boards, and engage with potential candidates through professional networks like LinkedIn. Screening Resumes: Review resumes and applications to identify qualified candidates based on skills and experience relevant to VLSI design roles. Interviewing Candidates: Conduct initial screening interviews to evaluate candidates' technical skills, experience, and cultural fit. Coordinate Interviews: Schedule interviews with hiring managers, VLSI engineers, and technical teams, ensuring a smooth interview process. 2. Collaboration with Hiring Managers Understand Requirements: Work closely with hiring managers and team leads to understand the specific needs for VLSI roles and the required skill set for each position. Technical Knowledge: Gain a solid understanding of the technical requirements for VLSI design and verification positions to effectively screen candidates. 3. Candidate Relationship Management Build a Talent Pool: Maintain a network of passive candidates for future opportunities, especially for hard-to-fill roles or specialized positions. Candidate Engagement: Keep candidates engaged throughout the hiring process, providing them with feedback, updates, and insights into the company culture and the role. Negotiations: Negotiate offers with candidates, ensuring alignment on salary, benefits, and other terms of employment. Share your resume at durgabhavani.b@acesoftlabs.com

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI HVL Verification. Experience5-8 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI HVL Verification. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Design For Testability - DFT. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Design For Testability - DFT. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: Analog Layout. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: Semiconductor Platform Engineering. Experience3-5 Years.

The ASIC Back-End Head is responsible for leading the physical design and implementation of Application-Specific Integrated Circuits (ASICs), ensuring optimal performance, power efficiency, and manufacturability. Key Responsibilities Strategic LeadershipDefine and execute the ASIC back-end design roadmap. RTL to GDSII Flow ManagementOversee synthesis, floorplanning, placement, routing, timing closure, and sign-off. Physical Design OptimizationEnsure Power, Performance, and Area (PPA) targets are met. EDA Tool ExpertiseWork with Synopsys, Cadence, Mentor Graphics tools for ASIC implementation. Cross-functional CollaborationCoordinate with design, verification, DFT, and packaging teams. Tape-Out & Manufacturing SupportEnsure smooth transition from design to fabrication. Key Skills & Qualifications Extensive experience (15yrs+) in ASIC physical design and implementation. Expertise in timing analysis, power optimization, and physical verification. Strong leadership, communication, and problem-solving skills. Bachelor's/Master's degree in Electronics, Electrical, or related Engineering discipline. Reinvent your world.We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

The ASIC Front-End Head is responsible for leading the front-end design team, ensuring high-quality Application-Specific Integrated Circuit (ASIC) designs, and driving innovation in digital chip development. This role requires expertise in RTL design, verification, synthesis, and architecture development, along with strong leadership and strategic planning skills. Key Responsibilities Technical LeadershipDefine and implement best practices for front-end ASIC design, ensuring efficiency and performance. Architecture & DesignOversee the development of digital circuits, including RTL coding, synthesis, and timing analysis. Verification & ValidationEnsure robust design verification methodologies using tools like UVM, SystemVerilog, and simulation frameworks. Cross-Team CollaborationWork closely with back-end design, physical design, and fabrication teams to optimize chip performance. Innovation & R&DStay updated with emerging semiconductor technologies and drive research initiatives. Mentorship & Team DevelopmentGuide and mentor engineers, fostering a culture of learning and technical excellence. Technical Project ManagementOversee front-end development timelines, ensuring timely delivery of high-quality designs. Required Qualifications EducationBachelor's or Master's degree in Electrical/Electronics Engineering, VLSI Design, or a related field. Experience15+ years in ASIC front-end design, with a proven track record of successful projects. Technical Skills: Expertise in HDLs (Verilog, VHDL), synthesis tools, timing analysis, and low-power design techniques. Leadership & CommunicationAbility to lead teams, manage projects, and communicate effectively with stakeholders. Problem-SolvingAnalytical mindset with a passion for optimizing digital designs for performance and efficiency. Reinvent your world.We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

The candidate must have minimum 1 yr of experience in technologies like ASP.NET MVC, WebAPI,SQL Server,LINQ, Entity Framework, Ajax, JSON. Experience on MVC is mandatory. Developing, Maintaining and Optimization of secure and scalable multi-tier web applications. Developing the website and identifying any technical problems and hitches. Must have worked on both Web and Windows applications. Knowledge of Angular/ React will be preferred. Candidate must have a strong background of ASP.NET (MVC framework) Programming. Candidate must have Knowledge of technologies like HTML, CSS,JQUERY,JAVASCRIPT, BOOTSTRAP, Web Services. Having good knowledge of reporting tools. Sound knowledge of OOPS and optimize physical design of MS SQL database systems.

Should have knowledge in MS SQL DBA (as primary). Secondary database knowledge of MY SQL Server. Experience in developing and maintaining relational structures including backup/recovery and log shipping procedures for SQL Server. Develop and support MS SQL database replication. Optimize MS SQL database performance. Responsible for database integrity, security. Estimate MS SQL database capacities; develop methods for monitoring database capacity and usage. Establish mechanisms for data backup/restore of relational databases provide restoration services as needed. Develop and optimize physical design of MS SQL database systems. Develop application-specific fault-tolerant distributed database mechanisms. Knowledge on other database variants like MS SQL, PostGreSQL or DB2 is preferred. Able to prioritize and execute tasks in a high-pressure environment. Experience working in a team-oriented, collaborative environment. Good written and oral communication skills.. MSSQL cluster technologies experience is also preferred. MSSQL Administrator Certified (Preferred).

Senior Staff Physical Verification Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development. Play Video Job Description Category Engineering Hire Type Employee Job ID 11903 Remote Eligible No Date Posted 22/06/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and proactive professional with a strong technical background in physical design and physical verification at the IP, block, and full-chip levels. You excel in addressing challenges associated with advanced FinFET and GAA processes and have a proven ability to deliver high-quality results in complex design environments. Your expertise spans RTL-to-GDS implementation, physical verification, and signoff methodologies, and you are adept at collaborating with cross-functional teams to achieve optimal design solutions. You are detail-oriented, innovative, and thrive in a collaborative environment where continuous improvement is valued. Your strong communication skills enable you to effectively engage with internal teams and external customers, ensuring alignment and success in project execution. With a passion for technology and a commitment to excellence, you are eager to contribute to the development of cutting-edge semiconductor solutions that shape the future. What You ll Be Doing: Conceptualizing, designing, and productizing state-of-the-art RTL-to-GDS implementations for SLM monitors using ASIC design flows. Designing on-chip Process, Voltage, Temperature, Glitch, and Droop monitors to track silicon biometrics. Performing physical verification tasks, including DRC, LVS, PERC, ERC, ESD, EM, and antenna cleaning. Collaborating with the Place & Route team to resolve full-chip/IP/block-level layout integration issues and drive physical verification closure. Coordinating with internal IP owners to address IP-related issues and with the manufacturing team to resolve DRC-related challenges. Creating and updating flows/methodologies in collaboration with architects and circuit design engineering teams. The Impact You Will Have: Accelerating the integration of next-generation intelligent in-chip sensors and analytics into cutting-edge technology products. Optimizing performance, power, area, schedule, and yield across semiconductor lifecycle stages. Enhancing product reliability and differentiation in the market while reducing risk. Driving innovation in physical verification and signoff design methodologies and tools. Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. What You ll Need: Educational Background : BS/B.Tech or MS/M.Tech in Electrical Engineering with 5+ years of relevant industry experience. Technical Expertise : Strong experience in physical verification and signoff, including DRC, LVS, DFM, ANT, ERC, ESD, EM, and PERC cleaning. Proficiency with digital design tools from any EDA vendor, preferably Synopsys tools like FC and ICV. Solid understanding of physical design, physical verification, and signoff concepts. Proven track record of successful physical verification closure and tape-outs in advanced nodes (14nm, 10nm, 7nm, 5nm, 3nm, 2nm). Experience with design methodologies, including developing custom scripts and enhancing flows for better execution (TCL/PERL scripting required). Additional Skills : Exposure to floorplan and PnR flows and tools such as ICC2/FC/Innovus is an added advantage. Good understanding of reliability physics, including EM, ESD, crosstalk, shielding, latch-up, and deep sub-micron challenges. Who You Are: Proactive and detail-oriented with excellent problem-solving skills. Adept at working independently and providing physical verification and signoff solutions. A strong communicator and teamer, capable of collaborating effectively with diverse teams. An innovative thinker with a passion for technology and continuous improvement. Committed to delivering high-quality results and achieving project goals. The Team You ll Be A Part Of: You will join a dynamic and collaborative team of engineers focused on developing cutting-edge semiconductor solutions. The team works on advanced physical verification methodologies, physical design, and signoff processes, driving innovation and excellence in the development of next-generation technology products. Together, you will tackle complex challenges, push the boundaries of technology, and contribute to the success of Synopsys industry-leading solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply As an applicant your resume, skills, and experience are being reviewed for consideration. Phone Screen Once your resume has been selected a recruiter and/or hiring manager will reach out to learn more about you and share more about the role. Interview You will be invited to meet with the hiring team to measure your qualifications for the role. Our interviews are held either in person or via Zoom. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Sr Staff STA Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development. Play Video Job Description Category Engineering Hire Type Employee Job ID 11904 Remote Eligible No Date Posted 22/06/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and driven professional with a strong technical background in Static Timing Analysis (STA) and physical design at the IP, block, and full-chip levels. You excel in tackling challenges associated with advanced FinFET and GAA processes and have a proven ability to deliver high-quality results in complex design environments. Your expertise spans RTL-to-GDS implementation, timing closure, and signoff methodologies, and you are adept at collaborating with cross-functional teams to achieve optimal design solutions. You are detail-oriented, proactive, and thrive in a collaborative environment where innovation and continuous improvement are valued. Your strong communication skills enable you to effectively engage with internal teams and external customers, ensuring alignment and success in project execution. With a passion for technology and a commitment to excellence, you are eager to contribute to the development of cutting-edge semiconductor solutions that shape the future. What You ll Be Doing: Conceptualizing, designing, and productizing state-of-the-art RTL-to-GDS implementations for SLM monitors using ASIC design flows. Designing on-chip Process, Voltage, Temperature, Glitch, and Droop monitors to track silicon biometrics. Developing digital back-end activities, including synthesis, pre-layout STA, SDC constraints development, placement, CTS, and routing, while collaborating with functional teams to achieve optimal design solutions. Performing post-layout STA, timing and functional ECO development, and timing signoff for high-frequency IP designs. Collaborating with the Place & Route team to resolve full-chip/IP/block-level layout integration issues and drive timing closure. Coordinating with internal RTL IP owners to address constraints-related issues. Creating and updating flows/methodologies in collaboration with architects, physical design, and RTL design engineering teams. Ensuring pre-layout and post-layout timing closure and timing model characterizations across various design corners to meet reliability and aging requirements for automotive and consumer products. The Impact You Will Have: Accelerating the integration of next-generation intelligent in-chip sensors and analytics into cutting-edge technology products. Optimizing performance, power, area, schedule, and yield across semiconductor lifecycle stages. Enhancing product reliability and differentiation in the market while reducing risk. Driving innovation in STA and signoff design methodologies and tools. Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. What You ll Need: Educational Background : BS/B.Tech or MS/M.Tech in Electrical Engineering with 5+ years of relevant industry experience. Technical Expertise : Strong experience in physical design, pre- and post-layout STA, and signoff, including SDC development and multi-mode design development. Proven expertise in functional and test constraints development (shift, capture, and at-speed) and timing closure with MCMM. Experience in generating ECOs for DRV cleaning and timing closure. Proficiency with digital design tools from any EDA vendor, preferably Synopsys tools like FC/PT/PT-PX. Solid understanding of OCV, POCV, derates, crosstalk, and design margins. Advanced Node Experience : Successful timing closure and tape-outs in advanced nodes (14nm, 10nm, 7nm, 5nm, 3nm, 2nm). Scripting Skills : Experience in scripting with TCL/PERL for developing custom scripts and enhancing design flows. Who You Are: Proactive and detail-oriented with excellent problem-solving skills. Adept at working independently and providing physical design and signoff solutions. A strong communicator and team player, capable of collaborating effectively with diverse teams. An innovative thinker with a passion for technology and continuous improvement. Committed to delivering high-quality results and achieving project goals. The Team You ll Be A Part Of: You will join a dynamic and collaborative team of engineers focused on developing cutting-edge semiconductor solutions. The team works on advanced STA methodologies, physical design, and signoff processes, driving innovation and excellence in the development of next-generation technology products. Together, you will tackle complex challenges, push the boundaries of technology, and contribute to the success of Synopsys industry-leading solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply As an applicant your resume, skills, and experience are being reviewed for consideration. Phone Screen Once your resume has been selected a recruiter and/or hiring manager will reach out to learn more about you and share more about the role. Interview You will be invited to meet with the hiring team to measure your qualifications for the role. Our interviews are held either in person or via Zoom. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Shrimad Rajchandra Mission Dharampur is looking for Senior Placement Officer to join our dynamic team and embark on a rewarding career journey Career Counseling: Provide guidance and career counseling to students or job seekers, helping them identify their skills, interests, and career goals Job Placement: Facilitate job placements by matching candidates with suitable job openings based on their qualifications and preferences Employer Engagement: Build and maintain relationships with employers, businesses, and organizations to understand their hiring needs and requirements Job Postings and Recruitment: Post job vacancies and coordinate recruitment processes, including conducting interviews and coordinating selection procedures Resume and Interview Preparation: Assist candidates in preparing resumes, cover letters, and interview techniques to enhance their chances of securing a job Internship and Training Opportunities: Identify and promote internship and training opportunities for students and job seekers to gain practical experience Networking Events: Organize job fairs, networking events, and industry-specific workshops to connect candidates with potential employers

THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the Power Delivery convergence team , you will work closely with the architecture, physical design teams, package, board, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work on full chip SoC electrical signoff convergence with physical design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Drive full chip IR/EM convergence on multiple ASICs across different technology nodes. Work closely with architecture, power management, package and floorplan team to come up with robust power delivery design. Work with RTL and PD team in coming up with the low power and UPF specification for the SoC. Work closely with CAD team to come up with new flows and methodologies in the power integrity domain. PREFERRED SKILLSET: 18+ years of professional experience in the industry with a proven track record of successfully delivering complex SoCs Sound knowledge of Power delivery and power integrity domains Hands on experience on industry standard tools especially Redhawk based power integrity analysis Should have lead IR/EM convergence on multiple full chip SoCs Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: Analog Layout. Experience1-3 Years.

Single Line Diagram (SLD) of Plant wide power distribution Conceptualization and Development various electrical layouts such as substation layout, earthing layouts, cable tray/ trench layouts, illumination and lighting protection layout, bus duct layout. Developing physical design deliverables in compliance with Indian/ International codes & standards, OEM recommended practice) Cable routing and developing cable scheduling Proficiency in 3D. Experience on E3D is preferred. Leading team of junior designers as well as training and mentoring, ensuring teams optimum capacity utilization. Vendor dwg review and approval Estimation of electrical bulk item such as cables, cable trays, earthing materials, terminations Coordination with end-clients, equipment suppliers, and internal disciplines e.g. Civil, Mechanical, I&C

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. E view modeling Characterization Verilog behavior modeling, timing lib modeling, Power view modeling, model verification of mixed signal analog IPs like DDR-MSIP, DDRIOs,. SERDES analog, ADC/DAC, PLLs e.t.c. . Functional understanding of mixed signal analog IPs as above for modeling and Characterization verification Proficiency in Verilog modeling and verification. Write behavioral Verilog/Verilog MS/real models of analog blocks. Developing and maintaining the self-checking Test-benches /Test-Plans. SV modeling and testbench development for verification against transistor level netlist Proficiency in Simulators such as VCS e.t.c. 5+ years of experience with characterization tool and simulators like Silicon Smart, Hspice, Finesim, Nanosim and Liberty format description Basic skills on AMS verification and knowledge preferable Self-motivation, teamwork, and strong communication skills. Tcl/Perl/Skill Scripting aware for automation You may e-mail or call Qualcomm's toll-free number found . To all Staffing and Recruiting Agencies :

We are seeking a diligent Verification leader to join our team at Renesas. The Verification engineer will be responsible for performing various verification tasks including Test Plan creation, Testcase creation, Coverage closure, Requirements traceability and Gate Level Simulation. They will also review system requirements and track quality assurance metrics. Ultimately, the role of the Verification Engineer is to ensure that our products, applications, and systems work correctly, safely & securely. Responsibilities: Drive Verification R&D team driving technical execution and best in class methodologies used in the design of advanced microcontrollers and microprocessors. Work closely with system architects to understand high level specifications to be able to verify them. Work with various EDA vendors to deploy next generation tools Build strong collaboration with other R&D teams such as RTL, DFT, digital IP, PD, Design Enablement, Emulation, and Validation to achieve project milestones Promote continuous improvement to design techniques to ensure Zero Defect chips Collaborate with SME s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence overall design improvements and verification methodologies Responsible for developing detailed Technical SoC verification execution plans, progress reports and tracking milestones, managing technical risks, and providing mitigations to meet schedule quality and costs commitments. Communicate across technical teas as well as provide executive level presentations Complete ownership for SoC verification quality sign-offs ensuring all deliverables for team hand-offs. Drive best in class verification methodologies collaborating with global internal and external SME s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI. Qualifications Degree in Electrical/Electronic Engineering, Computer Engineering or Computer Science At least 10 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits. Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC. Experience in Microcontroller and Microprocessor architecture & Interconnect Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR5/5x) and memory controllers. Advanced knowledge of Verilog, System Verilog, C/C++, Shell . Good knowledge in scripting like Perl, TCL or Python is a plus High proficiency in Metric Driven Verification concepts, functional and code coverage. Expertise in directed and constrained random methodologies. Good knowledge of formal verification methodologies and assertions. Experience with debugging of designs pre- and post-silicon, in simulation and on the bench. Excellent written and verbal communication skill. Must have worked on complex, multi-core SoC s with extensive interconnects and a large range of peripherals. Fair domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must. Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, UCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/Flex NOC interconnect; Flash memory subsystems. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Domain : Semiconductor | VLSI | Chip Design Must-Have Skills: Floor Planning Hands-on experience with Innovus Familiarity with Fusion Compiler Good to Have: Scripting knowledge in Tcl/Tk/Perl Understanding of Physical Design Methodologies Experience working with submicron nodes (28nm and below) Location : Bangalore | Hyderabad | Cochin | Pune