Debug IP Design Lead / MicroArchitect

You will be responsible for designing and developing Debug IPs focusing on CoreSight IP design. Your role will involve ensuring that the Debug IPs meet the required specifications and performance standards. You will utilize your expertise in RTL design using Verilog and/or SystemVerilog for complex SoC development. Additionally, you will apply your knowledge of Arm-based designs and/or Arm System Architectures to develop and optimize IPs. Collaboration with cross-functional teams, SoC integration & Architecture teams is essential to ensure successful IP delivery within specified timelines. Implementing rigorous verification processes to ensure that the IPs meet all functional and performance requirements is a key aspect of the role. To qualify for this position, you should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in RTL design for complex SoC development using Verilog and/or SystemVerilog is required. A strong understanding of Arm-based designs and/or Arm System Architectures is essential. Proficiency in IP design, verification, and delivery, with a focus on Debug IPs, is also a key requirement. Excellent communication and collaboration skills are necessary to effectively work with cross-functional teams. Preferred skills for this role include experience with CoreSight based Debug IP design and strong problem-solving and analytical skills.,