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Custom HM design engineer

Custom HM design engineer

Qualcomm

3 - 8 years

5 - 10 Lacs

Bengaluru

Posted:4 days ago| Platform:

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Skills Required

circuit hardware engineering datadriven perl logic design python static timing analysis simulation hspice rtl lec verilog cadence rtl design design compiler gds csi circuit designing shell scripting synopsys tcl system verilog rtl compiler

Work Mode

Work from Office

Job Type

Full Time

Job Description

Job Area: Engineering Group, Engineering Group > Hardware Engineering
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.Job Summary:

This position is open for 2-10 years’ experience candidate in Qualcomm CSI (Custom/SemiCustom implementation) team

Candidate will be part of CSI team working on RTL- GDS HM implementations using custom flow and methodology for custom design .

Qualcomm is one of the fastest growing semiconductor organization in India making high-end Chips with the most advanced technologies. To support its growing needs, we have strong CSI team for the design, development of various highspeed and low power IP’s being used in SoC. Individual has to work on RTL-GDS implementation. This will involve innovating new solutions in close collaboration with the other design teams.

Job Responsibilities:

Job responsibilities include design and development of custom macro using

Schematic design at block level (Ex RegArray, memory subsystem)

Frontend verification and model generations

CLP/PAGLS/LEC verifications at block level.

Functional verification using spice/gatesim.

Timing Signoff using PT,

Candidate should be able to collaborate with different teams.

Skillset/Experience:

2-10 year of experience:

Strong knowledge in transistor circuit design& block level logic design of Memory subsystem & Data path.

STA for the design to close Set-up, Hold, MPW, Transition, etc

Design verification using ESPCV & LEC, Simulation using Finesim & HSPICE.

Front-end RTL Design (Verilog RTL design, System Verilog, Synopsys Design Compiler, Cadence RTL Compiler, LEC, PLDRC, Static Timing Analysis and PTPX)

Physical Design using industry-standard RTL2GDS flow including Synopsys ICC2, Cadence Encounter.

Scripting in Perl/Python/Shell/Tcl for productivity is a plus

IP development (custom macro transistor level design, physical integration, collateral generation, flow development) and PPA quantification.

Interface with Process Technology Team to understand the complex DRC and DFM requirements of the advanced technology nodes

Work with cross functional teams (Architecture, Test/Verification , Product, CAD, Layout, Physical Design) to gather/define/implement specs

Transistor level implementation of the block using CMOS/Domino/Cell-Based/Data path styles

Implement power/clock gating techniques, Implement power/clock gating techniques, Implement industry standard as well as custom DFT techniques

Implement clock distribution using custom/CTS techniques for low skew/latency/power, Implement block layout using custom/compiler techniques using custom/semi-custom/stdcell libraries

Implement block level floor planning using custom and/or tiling techniques

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Custom HM design engineer