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ASIC Design Verification Engineer | UVM

ASIC Design Verification Engineer | UVM

Cisco

6 - 11 years

14 - 19 Lacs

Bengaluru

Posted:1 day ago| Platform:

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Skills Required

asic verification python design verification asic design perl asic sta physical design simulation primetime netlist lvs rtl uvm verilog physical verification ethernet floor planning formal verification silicon drc pnr pcie system verilog

Work Mode

Work from Office

Job Type

Full Time

Job Description

Meet the Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We craft the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by crafting, developing and testing some of the most sophisticated ASICs being developed in the industry. You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle.

Your Impact

You will contribute to developing Ciscos progressive data center solutions by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include:

Architect block, cluster and top-level DV environment infrastructure.
Develop DV infrastructure from scratch.
Maintain and improve existing DV environments.
Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus.
Ensure complete verification coverage through implementation and review of code and functional coverage.
Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist.
Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and efficient performance.
Support testing of design in emulation.
Lead all aspects of and manage the ASIC bring-up process.

Minimum Qualifications

Bachelors Degree or equivalent experience in EE, CE, or other related field.
7+ years of related ASIC design verification experience.
Proficient in ASIC verification using UVM/System Verilog.
Proficient in verifying sophisticated blocks, clusters and top level for ASIC.
Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
Scripting experience with Perl and/or Python.

Preferred Qualifications

Masters Degree in EE or CE with 5+ years of relevant work experience.
Experience with Forwarding logic/Parsers/P4.
Experience with Veloce/Palladium/Zebu/HAPS.
Formal verification (iev/vc formal) knowledge.
Demonstrated ability on one or more protocols (PCIe, Ethernet, RDMA, TCP).

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ASIC Design Verification Engineer | UVM