66 Formal Verification Jobs

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 1-3 yrs years of experience in Physical Design/Implementation

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. o BE/BTech degree in CS/EE with 3+ years’ experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred : o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologiesJTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Role * Physical Design Life cycle of chip development, especially Floorplanning and PnR * Hands on PD execution at block/SoC level along with PPA improvements * Strong understanding of the technology and PD Flow Methodology enablement. * Work with Physical design engineers to rollout robust, identify areas for flow improvement methodologies. (area/power/performance/convergence), develop plans and deploy/support them * Provide tool support and issue debugging services to physical design team engineers across various sites * Develop and maintain 3rd party tool integration and productivity enhancement routines * Understand advance tech PNR and STA concepts and methodologies and work closely with EDA vendors to deploy solutions. Skill Set * Strong programming experience & Proficiency in Python/Tcl/C++ * Understand physical design flows using Innovus/fc/icc2 tools * Knowledge of one of Encounter/Innovus or FC (or other equivalent PNR tool) is mandatory * Basic understanding of Timing/Formal verification/Physical verification/extraction are desired * Ability to ramp-up in new areas, be a good team player and excellent communication skills desired Experience 3-5 years of experience with the Place-and-route and timing closer and power analysis environment is required Niche Skills Handling support tools like Encounter/Innovus/edi/fc/Icc2 (or other equivalent PNR tool). One or more of the above is mandatory*

Grow with us About Us: We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrows mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport - to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we dont just follow industry trends we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, youll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, youll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. Youll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. Key Responsibilities: Take part of the verification of designs, whether at the block or subsystem level. Participate in defining and implementing UVM-based test environments. Support the creation of Verification Strategies and contribute to the development and execution of Verification Plans. Develop, run, and debug test cases to ensure design quality under supervision. Contribute to the improvement and optimization of verification methodologies. Generate documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Required Qualifications: Bachelor s degree in electrical or computer engineering. 5+ years industry experience in verification using SystemVerilog and UVM. Additional experience will allow placement at higher job levels. Strong experience in / with: development of verification test plans and create directed/randomized test cases. formal verification. in implementing scoreboards, checkers, bus functional models in existing testbench environment. SystemVerilog Assertions. Additional Requirements: Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Experience in low-power design verification. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson? What happens once you apply? Primary country and city: India (IN) || Bangalore Req ID: 768626

Grow with us About Us: We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrows mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport - to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we dont just follow industry trends we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, youll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, youll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. Youll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. Key Responsibilities: Take part of the verification of designs, whether at the block or subsystem level. Participate in defining and implementing UVM-based test environments. Support the creation of Verification Strategies and contribute to the development and execution of Verification Plans. Develop, run, and debug test cases to ensure design quality under supervision. Contribute to the improvement and optimization of verification methodologies. Generate documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Required Qualifications: Bachelor s degree in electrical or computer engineering. 5+ years industry experience in verification using SystemVerilog and UVM. Additional experience will allow placement at higher job levels. Strong experience in / with: development of verification test plans and create directed/randomized test cases. formal verification. in implementing scoreboards, checkers, bus functional models in existing testbench environment. SystemVerilog Assertions. Additional Requirements: Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Experience in low-power design verification. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Primary country and city: India (IN) || Bangalore Req ID: 768626

Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices, Job Description In your new role you will: Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices, Responsible for: Designing self-checking test benches using modern verification techniques Implementing functional coverage and assertions using System Verilog and UVM, Developing TB environment using SV and UVM, Developing test and functional coverage plans based on device specifications, Analyzing and debugging simulation failures, as well as analyzing functional coverage results to guarantee zero defect outcomes, Your Profile You are best equipped for this task if you have: Engineering in Electrical/electronic streams , or equivalent experience, 2+ years experience in constrained-random, coverage driven verification environments, Experience in RAL Experience in developing the test bench from scratch using System Verilog (SV) HDVL and UVM (Universal Verification Methodology), Expertise in Gate Level simulations (GLS) and have debugged, root caused real netlist issues, A solid understanding of verification concepts and experience designing class-based test benches, C coding, Formal verification methods and Power aware simulation will be an advantage Excellent written and oral communication skills Strong debugging skills, functional simulations and GLS simulations, Contact: Gowri ShenoyGowri Shenoy@infineon,, LinkedIn #WeAreIn for driving decarbonization and digitalization, As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals Be a part of making life easier, safer and greener, Are you in We are on a journey to create the best Infineon for everyone, This means we embrace diversity and inclusion and welcome everyone for who they are At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities We base our recruiting decisions on the applicant?s experience and skills, Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process, Click here for more information about Diversity & Inclusion at Infineon,

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. BE/BTECH/ME/MTECH Or Equivalent Degree EXP7-13years Design Verification role for IP development team. Position is based in Bangalore , part of Cadence IP Group. Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C) UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs. In addition to UVM functional verification, role could involve Formal verification of complex design modules. In addition to UVM functional verification, role could involve participating in Emulation qualification of design IPs. Understand design and produce detailed verification strategy and test plan. Self-starter and learner with passion for getting the job done on time with great quality. Strong problem solving, analytical and debug skills Excellent verbal and written communications skills We re doing work that matters. Help us solve what others can t.

Description: Minimum Required Qualifications Education Bachelors / Masters Degree in Electrical Engineering, Electronic Engineering, Mechanical Engineering, Computer Science Engineering or equivalent. Work Experience Minimum 6 years of experience with Bachelors in areas such as System Architecture, System Design, Hardware Engineering or equivalent OR no prior experience required with Masters Degree. Systems Test Engineer,Responsibilities: Responsible for software and system testing activities Adheres to the test plans and test strategies for multiple concurrent projects Implement and monitor structured system testing (manual and automated) methodologies Understand the System Requirement, sub-system requirement and software requirements review effort to ensure that requirements are actionable, measurable and testable Work with development teams to employ iterative development test strategies and tactics on assigned projects and ensure full execution of the test plan. Provide effort estimates for the test cases, and bring in Automation as needed. Create, review and optimize test design, reusable test cases and test procedures to ensure complete functional and non-functional test coverage for multiple projects concurrently Build reusable test case framework to support positive, negative and boundary testing and avoid redundant test case development Ensure all supported hardware environments and catheters are tested in a production-like environment for formal verification and subject to strict change control Ensure defect are logged in clearly and analysis done to recognize the weak areas of code/product. Interface with cross functional teams. Provide timely communications on significant issues or risks identified in traceability matrix Analyze available data and identify trends and track actual testing progress against the plan and ultimately provide visibility into release readiness and release quality Qualifications Minimum Six years formal system test experience Strong analytical and problem-solving skills Demonstrate organizational and interpersonal skills working in a cross-functional, regulated environment Knowledge of testing methods at all levels (unit, integration, system, V&V, acceptance) applied within the product development lifecycle Applies advanced technical experience and has full knowledge of other related disciplines (Multi-discipline, multi-domain) Test automation experience is desired Self-motivated Team player Previous work experience on medical device in FDA regulated industry is a plus,2 Manual test Engineers requirement for the PVIVUS and CV IVUS projects as per the approval from Michael Golms . Level of Experience India Additional Details Minimum required qualifications : In this role, You are responsible for Lead software and system testing activities Create test plans and test strategies for multiple concurrent projects Implement and monitor structured system testing (manual and automated) strategies/methodologies Lead the System Requirement, sub-system requirement and software requirements review effort to ensure that requirements are actionable, measurable and testable Work with development leads to employ iterative development test strategies and tactics on assigned projects and ensure full execution of the strategy. Provide effort estimates. Identify common trends on planned estimated effort hours vs actual hours. Create, review and optimize test design, reusable test cases and test procedures to ensure complete functional and non-functional test coverage for multiple projects concurrently Build reusable test case framework to support positive, negative and boundary testing and avoid redundant test case development Work closely with automation architect to develop functional automation infrastructure and automation framework Ensure all supported hardware environments and catheters are tested in a production-like environment for formal verification and subject to strict change control Provide training and guidance in an effort to minimize procedure errors and that may result into corrections and deviations. Create defects trends analysis to recognize the weaken areas of code Define and measure key progress indicators on requirement coverage, test case effectiveness, Test execution and defect identification and closure Interface with cross functional teams. Provide timely communications on significant issues or risks identified in traceability matrix Analyze available data and identify trends and track actual testing progress against the plan and ultimately provide visibility into release readiness and release quality Create Final verification reports Mentor and guide junior test engineers/ technicians and lead continuous improvement programs. Level of Experience India : e. 8 - 10 Years Job Profile Name : Systems Test Engineer 60 Job Grade : 60

: We are looking for a highly skilled & experienced PD expert to join our Flows & Methodologies team. The candidate must be experienced, hands-on and have robust understanding of physical design including Floorplan, Power-plan, Place & Route, UPF, CTS. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope of Responsibilities: As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define Physical Design methodology to meet SoC & IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools and flows definition, requirement management for SoC Place & Route, UPF, Formal Verification, Floorplan & Power-Plan You will work with EDA Vendors to proactively review latest tools and flows offerings in Physical Implementation domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies. Work with EDA Vendors to review and resolve blocking issues You will be an actor of change for deploying new tools & methodologies across the organization Qualifications Specific skills & knowledge : Bachelor or Master or Ph. D. in Electronics Engineering and specialization in VLSI domain 10+ years of hands-on experience in Physical Design : UPF, Formal & Physical verification, floorplan, power-plan, Place & Route Proven experience in delivering physical implementation closure methodology ensuring timing & physical convergence Experience in Synopys & Cadence tool sets (Fusion Compiler, Innovus) , low geometry node issues, working with EDA team in reviewing & resolving blocking issues in project Experience in customizing flows & methodology to meet low power & area objectives of SoC Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can - do attitude, openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime. This role is based in Bangalore. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. This is your role Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution. Work with design community in solving critical designs problems to achieve desired performance, area and power targets. Deployment of Synthesis solution with various customers working on cutting edge technologies (7nm and forward). Develop & deploy training and technical support to customers using Siemens EDA tools. We don’t need superheroes, just superminds! Typically requires minimum of 9+ years of experience in Logic Synthesis flows Proficiency in Verilog, System Verilog & VHDL. Strong knowledge of RTL2GDSII flow with strong fundamentals in digital design & implementation. Prior experience in IC digital design flows and front-end EDAT tools including Synthesis, DFT, Formal Verification, Logic Equivalence Checks Hands-on experience using commercial synthesis tools like Synopsys-DC/FC, Cadence-Genus is a must. Experience with advance technology nodes 7nm and below. Hands-on experience in debug & deliver solutions to critical design issues related to synthesis. TCL, Perl or Python scripting is a plus. Self-motivated team player with a zeal to drive high team performance. Good problem solving and debugging skills. Strong verbal & written communication skills We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-Hybrid

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Questa Simulation Product It is a core R&D team working on multiple verticals of Simulation. A very energetic and enthusiastic team of motivated individuals. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! Key Responsibilities: We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role Job Qualification: An ideal candidate should have skills below: B.Tech or M.Tech in Computer Science & Engineering (CSE), Electrical Engineering (EE), or Electronics & Communication Engineering (ECE) from a reputable engineering institution having 8 - 15 years of experience. Strong knowledge of C/C++, algorithms, and data structures. Familiarity with compiler concepts and optimizations. Experience with UNIX and/or LINUX platforms is essential. Excellent problem-solving and analytical skills. Self-motivated with the ability to work independently and guide others towards successful project completion. We are not looking for superheroes, just super minds! Having the below skills will be an added advantage: Strong understanding of basic digital electronics concepts. Familiarity with machine learning (ML) and artificial intelligence (AI) algorithms, particularly their implementation in data-driven tasks. Proficiency in hardware description languages such as Verilog, SystemVerilog, and VHDL. Experience with parallel algorithms and job distribution techniques. Exposure to simulation or formal verification methodologies is a plus. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-Hybrid #DVT

Do you have a passion for invention and self-challengeDo you thrive on pushing the limits of what s considered feasibleAs part of an extraordinary modem team, you ll craft sophisticated leading-edge embedded firmware that deliver more performance in our products than ever before. You ll work across subject areas to transform improved hardware elements into a single, integrated design. Join us, and you ll help us innovate new wireless systems technologies that continually outperform the previous iterations! By collaborating with other product development groups across Apple, you ll push the industry boundaries of what wireless systems can do and improve the product experience for our customers across the world!As a Cellular 5G/4G Firmware Verification Engineer, you will be at the center of the embedded 5G/4G multimode cellular firmware effort within a silicon design group responsible for crafting and productizing state-of-the-art cellular SoCs. This position requires someone comfortable with all aspects of embedded firmware verification, that thrives in a dynamic multi-functional organization, is not afraid to debate ideas openly, and is flexible enough to pivot on constantly evolving requirements. Description We work with a team of component validation, integration, protocol test engineers, firmware developers and system engineers to create firmware verification test cases and end to end physical layer performance - Design and develop validation frameworks for the 4G/5G firmware. Also, design, develop, and execute test cases for the 4G/5G firmware and debug and analyze issues found during the testing - Create test automation of 4G/5G UEs, test simulators and test gNodeBs.Verify key protocol, signal processing and numerical algorithms with very tight time, latency and energy budgets. Work with Systems / Firmware teams to perform validation of new and existing features.We are looking for candidates who can assist in the development of pre-silicon emulation systems/virtual platforms and use them for pre-silicon firmware design and HW verification. Also, evaluate and implement cutting edge tools for build, formal verification and test. In-depth understanding of 5G and 4G 3GPP physical layer and protocol stack procedures and configurations Experience with firmware test case planning, design, and development for the 4G/5G functional and performance scenarios Strong understanding of automation tools and scripting languages, such as Python, C/C++, Java (a plus) Solid understanding of multiple 4G/5G signalling and physical layer test equipment (Keysight/Anritsu/RS) along with their automation interfaces Preferred Qualifications Bachelors degree in Electrical Engineering, Computer Science or related experience is required Strong analysis and debugging capabilities to be able to define issues and work with firmware development and systems design teams to close these issues Deep understanding of software engineering principles, and core computer science fundamentals Fundamental facility with build and source code control tools Versatile to learn new architecture, frameworks and experience with network emulators, silicon prototyping, emulation systems, and virtual platforms a plus

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL, AMS system modelling and PD teams. Lead technical alignment on verification strategies. Define and architect verification environments and methodologies. Take initiative to drive overall execution efficiency and quality improvements. Improve and evolve existing verification methodologies : Co-Simulation (Co-SIM), UPF Power Aware Simulations (UPF PA Sim), VIP/DIP integration and Verification, increase Formal Verification usage especially FPV, Safety Verification Analyze execution and quality issues to define, develop, and deploy new functional verification methodologies for continuous improvement. Required Qualifications: Solid background in functional verification fundamentals. Experience in: Verification environment development Test plan creation Verification closure RTL and GLS debug skills, formal verification, PA simulation Strong SystemVerilog and UVM methodology expertise. Prior digital verification experience in serial bus multiprotocol PHY IPs (UCIE or SerDes IPs is preferred) B. E/B. Tech/M. E/M. Tech with 10+ years of experience Good to Have (Not Mandatory): Exposure to analog modeling and AMS (Analog/Mixed-Signal)-digital co-simulations. Experience with automotive IP verification (e. g. , fault injection). Emulation exposure. We re doing work that matters. Help us solve what others can t.

What You'll Be Doing: Manage a team of product application engineers to promote the adoption of Synopsys Formal Verification Apps. Develop and strengthen strategic partnerships with key customers. Drive management and technical review meetings with strategic customers. Perform competitive analysis to guide the development of differentiating formal technologies and methodologies. Collaborate with R&D and Product Management teams to develop new flows and functionalities. Define formal verification flows and methodologies to enhance customer productivity. Drive the scoping and execution of formal consulting services. Lead the development of assertion IPs to meet customer requirements. The Impact You Will Have: Facilitate the widespread adoption of Synopsys Formal Verification Apps, driving innovation in the industry. Build and maintain strong relationships with strategic customers, ensuring their needs are met and exceeded. Enhance the competitive edge of Synopsys through thorough competitive analysis and innovation. Drive the development of cutting-edge verification flows and methodologies, setting industry standards. Improve customer productivity and satisfaction through well-defined verification processes. Lead a high-performing team, fostering an environment of collaboration and continuous improvement. What You'll Need: EE graduate from a reputed school, with post-graduate qualifications preferred. 15+ years of industry experience in RTL design or verification using simulation-based technologies. 5+ years of experience managing medium to large-sized teams. In-depth understanding of Assertion-based verification using formal and simulation methods. Strong knowledge of hardware design (Verilog/VHDL) and micro-architecture. Expertise in Unix/Linux automation shell (bash, csh) and scripting (Tcl, Perl, Python). Excellent oral and written communication skills. Expertise in one or more areas such as Formal Property Verification testbench development, floating point arithmetic operations, C/C++, IEEE math libraries, Security architecture, Automotive Safety (FuSa) verification, and Verification signoff with formal.

As part of the team, design, develop and drive improvements to the verification technology Support the existing functionality and continually aim to enhance the versatility, performance and memory utilization while improving quality of the software. Work requires algorithm, data structure design as well as developing robust and efficient implementations. Interact with other members of Synopsys R&D, customer as necessary to understand customer needs and product goals. Skills Required: A minimum of 8 years of related experience. Excellent Software development experience with C / C++ on UNIX/Linux platforms Broad understanding of data structures, algorithms and their applications. Should have experience working in a multi-person product development environment with high dependencies and tight schedules. It is essential that the applicant is highly motivated and has solid desire to learn and explore new technologies. Demonstrated history of good analytical, debugging and problem-solving skills. Experience with complex software tool development and usage with legacy code base Exercise of judgment in developing methods, techniques, and evaluation criteria to meet project goals. Ability to work in both self-directed and collaborative settings. Understanding/Experience in Unified Power Format (UPF) would be beneficial Good written and oral communication skills, for team collaboration and product presentations. Preferred Skills: Special consideration given to those with background and experience in formal verification and/or synthesis techniques. Experience in Compilers and RTL Synthesis would be beneficial Knowledge of software specification and design process, and regression testing. Ability to know about customer wants and needs in the formal verification user community, by working with sales and field personnel.

As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Drive formal verification for the block and write formal properties and assertions to verify the design Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design Responsible for verification quality metrics like pass rates, code coverage and functional coverage PREFERRED EXPERIENCE: Project level experience with design concepts and RTL implementation for same Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics Good understanding of computer organization/architecture ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Overview UVM Based verificaton at SOC level Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Bachelor’s/ Master’s degree or higher in EEE/ECE 5+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platformsUVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. * Hands on PD execution at block/SoC level along with PPA improvements * Strong understanding of the technology and PD Flow Methodology enablement. * Work with Physical design engineers to rollout robust, identify areas for flow improvement methodologies. (area/power/performance/convergence), develop plans and deploy/support them * Provide tool support and issue debugging services to physical design team engineers across various sites * Develop and maintain 3rd party tool integration and productivity enhancement routines * Understand advance tech PNR and STA concepts and methodologies and work closely with EDA vendors to deploy solutions. Skill Set * Strong programming experience & Proficiency in Python/Tcl/C++ * Understand physical design flows using Innovus/fc/icc2 tools * Knowledge of one of Encounter/Innovus or FC (or other equivalent PNR tool) is mandatory * Basic understanding of Timing/Formal verification/Physical verification/extraction are desired * Ability to ramp-up in new areas, be a good team player and excellent communication skills desired Experience 3-5 years of experience with the Place-and-route and timing closer and power analysis environment is required Niche Skills Handling support tools like Encounter/Innovus/edi/fc/Icc2 (or other equivalent PNR tool). One or more of the above is mandatory*

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. o BE/BTech degree in CS/EE with 3+ years experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred : o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologiesJTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Job Responsibilities Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 2+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 3+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Masters degree in Electrical/Electronic Engineering from reputed institution 12+ years of experience in Physical Design/Implementation Minimum Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems "which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl /Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's/ Masters degree in Electrical /Electronic Engineering from reputed institution 2-10 years of experience in Physical Design/Implementation

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Are you interested in working with a world-class CPU design teamAre you interested in the application of formal methods to the verification of application processorsIn contributing to the development of the next generation of formal methodologies in this space Qualcomm's CPU team has some of the best CPU architects and engineers on the planet, developing the processors that will power the future. Come and join us on this exciting adventure. Sharpen your formal verification skills to their fullest on some of the complex designs ever attempted. Roles and Responsibilities Work with design team to understand design intent and bring up verification plans and schedules with an eye towards the end-to-end formalization of the refinement from architecture to micro-architecture Define formal verification architecture, develop test plans and build end-to-end formal sign-off environments for Qualcomm CPU components Engage in full-spectrum deployment of model-checking technology to hardware designs including property verification, math proofs, architectural modeling and validation amongst other cutting-edge application areas To be successful in this position you will need BA/BS degree in CS/EE with 8+ years of practical experience in application of formal methods in hardware or software Strong model checking or theorem proving background/experience in verification of complex systems Experience in writing assertions and associated modeling code in Hardware Description Languages or in proving correctness of architectural specifications using formal methods Working familiarity with model checkers like Jaspergold and VC-Formal or theorem-proving tools such as ACL2 and HOL The ideal candidate will have the following experience MS/PhD degree in CS/EE; 4+ years of practical experience Strong foundation in formal methods and in their application to hardware specifications and/or implementations Domain knowledge in one or more of these areasMicroprocessor architecture and micro-architecture, instruction set architecture, floating-point math, memory consistency, memory coherency, security architectures Strong software engineering skills with proven ability in automation and proficiency in at least one programming language (C++, Python, TCL etc.) Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.