Analog Layout Engineer -Lead

Your Role and Responsibilities 1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield.4. Participate in building and enhancing layout flow for faster, higher quality design process.5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks6. Collaborate with Circuit Designers to solve challenging problems7. Writing /PYTHON scripts to automate repetitive tasks8. Work with Place and Route engineer to integrate custom macros into top level.9. Able to perform design reviews across global team10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from IndiaJob requirements:1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc.2. Experience in designing layouts for high-speed circuits is a plus.3. Layout experience in the following technology nodes3nm, 5nm and 7nm FinFET.4. Good team worker with multi-discipline, multi-cultural and multi-site environments5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serialIO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.