640 Semiconductor Jobs

Job Title: Embedded & VLSI Recruiter Location: Marathahalli, Bangalore (Work From Office 5 Days a Week) Experience: Minimum 3 Years Job Type: Full-Time | On-Site | Immediate Joiners Interview Mode: Face-to-Face (F2F) Job Description: We are looking for a passionate and experienced Embedded & VLSI Recruiter to join our dynamic talent acquisition team. The ideal candidate will have a strong background in hiring for niche technologies in Embedded Systems and VLSI domains, especially through Contract-to-Hire (C2H) models for product-based clients. Roles and Responsibilities: Handle end-to-end recruitment for Embedded Systems and VLSI requirements Manage Contract-to-Hire (C2H) hiring with precision and compliance Source, screen, and shortlist profiles using portals, LinkedIn, referrals, and Boolean/X-Ray searches Interact and coordinate with hiring managers and technical teams for scheduling and feedback Build strong pipelines and talent pools for niche Embedded/VLSI skill sets Maintain and update candidate databases and ATS Ensure quick turnarounds and a high quality of hires Coordinate and manage F2F interviews at the client location Required Skills: Minimum 3 years of experience in technical recruitment Strong exposure to Embedded and VLSI domain hiring Contract hiring (C2H) experience is mandatory Experience working with product-based clients Good understanding of sourcing tools, LinkedIn, and Boolean search Excellent verbal and written communication skills Highly organized and deadline-driven Nice to Have: Familiarity with ATS tools like Ceipal , JobDiva , etc. Knowledge of basic technical terms in Embedded/VLSI space Ability to work in a high-paced, dynamic environment Interested candidates can share their resumes at durgabhavani.b@acesoftlabs.com Quick Connect on WhatsApp: 9701923036

Job Title: Technical Sales Engineer - Electronics/Semiconductors Location: Chennai Experience Required: 1 to 3 Years Industry: Electronics / Semiconductor / Electronic Components Department: Sales / Business Development / Technical Support Employment Type: Full Time, Permanent Job Description We are looking for a dynamic and technically strong Technical Sales Engineer to join our team in Chennai. The ideal candidate should have 1 to 3 years of experience in technical sales or application engineering, preferably in the electronics or semiconductor industry. Key Responsibilities: Handle sales of electronic components and semiconductor products in assigned territory Interact with customers to understand their technical requirements and provide appropriate solutions Prepare and deliver technical presentations and product demos Generate new leads and convert them into business opportunities Coordinate with product teams for customized solutions and post-sales support Maintain relationships with OEMs, design engineers, and procurement teams Key Skills Required: Strong technical knowledge in: Semiconductors (Microcontrollers, Sensors, Analog/Digital ICs, Power Electronics) Embedded systems and basic circuit design Understanding of PCB layouts and testing tools (Multimeter, Oscilloscope, Logic Analyzer, etc.) Excellent communication and customer relationship skills Experience in B2B sales / field sales / technical support / application engineering Ability to work independently and manage time effectively Self-driven with a passion for technology and solution selling Qualifications: B.E. / B.Tech in Electronics & Communication, Electrical, or related discipline Experience : 1 to 3 years of relevant experience in the electronics/semiconductor field Preferred Industry Background: Semiconductor distributors Electronics components sales Electronic product companies (OEMs/EMS) Technical marketing/application support in electronics domain Call or WhatsApp your resume to - 8861103561

Summary / Role Purpose As a Product Specialist II , you will be part of the team responsible for overall development and validation of Ansys EDA Products. This involves working with Software developers, Architects, Application Engineers, and Semiconductor Customers, from ideation all the way to final product release and deployment. Key focus areas will include all areas related to IP/SoC/3DIC Power Integrity, Signal Integrity, Reliability aspects like EM/ESD/Thermal, Advanced timing/jitter, Packaging - the top challenges for any chip design on advanced nodes like 7/5/3 nm. Key Duties and Responsibilities Be part of Product Engineering Team that Works with Global-Customers / IP-providers / Foundries to understand design challenges of cutting-edge SoCs & 3DICs on 7/5/3 nm and creates EDA product specifications. Works with Software developers to develop state-of-the-art EDA products solving Power-Noise-Reliability challenges across Chip-Package-System Works on Ansys-Seascape platform - Semiconductor Industry s First and Only True Big-Data design Platform! Performs in-depth validation to ensure Product meets accuracy and other requirements. Collaborates with Application Engineers to support Global Customers in solving their design challenges on leading edge SoCs. Minimum Education/Certification Requirements and Experience Bachelor s/Master s degree in Electronics Engineering/VLSI from Top Institutions (NITs/IITs and likes) Strong problem-solving skills Good programming skills Excellent verbal and written communication skills Preferred Qualifications and Skills Passion to learn and deploy new technologies. Ability for minimal travel 2-3 years of prior experience in either of a) ASIC Physical design, b) Power-Integrity / Signal-Integrity / Reliability Closure c) Custom circuit design and simulation At Ansys, we know that changing the world takes vision, skill, and each other. We fuel new ideas, build relationships, and help each other realize our greatest potential. We are ONE Ansys. We operate on three key components: our commitments to stakeholders, our values that guide how we work together, and our actions to deliver results. As ONE Ansys, we are powering innovation that drives human advancement Our Commitments: Amaze with innovative products and solutions Make our customers incredibly successful Act with integrity Ensure employees thrive and shareholders prosper Our Values: Adaptability: Be open, welcome what s next Courage: Be courageous, move forward passionately Generosity: Be generous, share, listen, serve Authenticity: Be you, make us stronger Our Actions: We commit to audacious goals We work seamlessly as a team We demonstrate mastery We deliver outstanding results

About Marvell . Your Team, Your Impact Marvell is a leading provider of innovative technologies, including ultra-fast read channels, high-performance processors, leading edge transceivers, highly efficient analog designs, and powerful cryptographic engines. These solutions address all segments of the hard disk drive (HDD) and solid-state drive (SSD) electronics markets, providing complete solutions including controllers, product firmware, and reference board designs. Many of the same technologies have been utilized in Marvell system solutions products, powering PCs, servers, cloud, and enterprise systems. What You Can Expect As a member of our team, you will work closely with architects and technologists to influence R&D in accelerated compute, networking, storage, and security technologies, including emerging low-latency transport protocols. Intelligently structure new feature designs and other software changes so that code is scalable, maintainable, and easily mergeable to legacy products as well as new products. Collaborate with R&D to develop new features and contribute to open source communities like DPDK, Linux kernel Implement AI/ML-driven transport protocols and software for advanced hardware. Develop proof-of-concept materials for innovative technologies and assist early adopters. Participate in software development design flow, submitting and attending code reviews, managing and updating issue-tracking tickets (JIRA), following team-specific design and coding guidelines. Analyze performance metrics and troubleshoot complex issues in large-scale environments. What Were Looking For Bachelor s degree in computer science, Electrical Engineering or related fields and 8-12 years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 8-12 years of experience. Proficient in multiple programming languages, including C, Perl, Python, and shell scripting. In-depth knowledge of Linux operating systems, including kernel-level programming. Understanding of DMA, interrupts, processes, memory management, and synchronization. Familiarity with DPDK (Data Plane Development Kit), OVS (Open vSwitch), ODP (Open Data Plane) and RDMA (Remote Direct Memory Access) will be an advantage. Knowledge of ARM multicore SoC architecture. Strong experience with networking technologies and protocols. Understanding of RoCE, RDMA, and DPU concepts. Experience with high-speed network packet I/O, networking security. Familiarity with security protocols such as PSP, IPSec, TLS Hands-on experience in performance benchmarking, system profiling, and tuning. Strong proficiency in Linux environments and networking. Eager to learn and thrive in fast-paced environments. Strong analytical and problem-solving skills. Effective in collaboration and customer engagement. Excellent communication skills in distributed team settings. Capable of independent task planning and execution. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-RS1

About Marvell . Your Team, Your Impact Marvell innovates in Ethernet switching technology across a broad portfolio of segment-focused product families. Marvell switches power next-generation campus, industrial, 5G, cloud and AI networks. What You Can Expect Develop and document SW features for a software development kit. Deliver SW releases, sample codes, and patches to customers and involved in the SW integration into their platform. Troubleshoot complex software problems (SW API, GUI, SW Tools/Drivers) and recommend corrective action. Closely follow and check customer technical issues, provide remote or on-site troubleshooting. Support customer lab/field trial, able to understand customer application environment and provide insightful advice on customer products. Help/train customer to understand Marvell product architecture and features, promote and demo Marvell products functionalities with Sales and Marketing. Work cross functionality with silicon development, system validation, and marketing team to deliver SW solution. Develop technical collateral material including application notes, user guide/manual, release notes, white papers and other technical documents. Articulate technology and product positioning to both business and technical users. Assist sales team through preparation and delivery of technical presentations and statements of work by matching specific client business requirements with effective technical solutions. Create relationships with key decision makers and serve as external technical spokesperson. Provide customer feedback to executive and development teams to participate in functionality roadmap planning. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience. Must possess excellent written and verbal communication skills. Be able to present and clearly articulate solutions to customers. Previous experience of working as an Application Engineer or any equivalent Customer interacting role (i. e. ability to handle customers) is a must. 5-10 years of experience in networking, with a focus on AI infrastructure. 5 - 10 years of experience in customer-facing roles, providing technical support and solutions. Preferred Qualifications: Experience with switch driver development and community software such as SAI/Sonic. Proficiency in developing and debugging device drivers and silicon. Understanding of system-level switch and hardware requirements. Familiarity with networking protocols and VLSI design. Strong leadership and communication skills, with the ability to inspire and guide teams. Working with internal and external customer teams. Wide knowledge in code review, debug, and preparing patches. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-RS1

Overview Keysight is on the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do. Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers. We are seeking a Senior Machine Learning Engineer to lead the design, development, and deployment of scalable machine learning models that power business decisions across the enterprise. This role combines technical depth in ML/AI with a strong understanding of business domains such as Sales, Service, Finance, Order Fulfillment, and Supply Chain. You will collaborate closely with Data Scientists, Data Engineers, and business partners to build production-ready solutions that drive measurable impact. Responsibilities 1. Machine Learning Development Deployment Design and implement supervised and unsupervised models for predictive analytics, including churn prediction, demand forecasting, renewal risk scoring, and cross-sell/upsell opportunity identification. Translate business problems into ML frameworks and production solutions that improve efficiency, revenue, or customer experience. Build, optimize, and maintain ML pipelines using tools such as MLflow, Airflow, or Kubeflow. 2. Cross-Functional ML Use Cases Partner with teams across Sales (e.g., lead scoring, next-best action), Customer Service (e.g., case deflection, sentiment analysis), Finance (e.g., revenue forecasting, fraud detection), Supply Chain (e.g., inventory optimization, ETA prediction), and Order Fulfillment (e.g., delivery risk modeling) to define impactful ML use cases. Develop domain-specific models and continuously improve them using feedback loops and real-world performance data. 3. Model Governance and MLOps Ensure robust model monitoring, versioning, and retraining strategies to keep models reliable in dynamic environments. Work closely with DevOps and Data Engineering teams to automate deployment, CI/CD workflows, and cloud-native ML infrastructure (AWS/GCP/Azure). 4. Data Engineering and Feature Architecture Collaborate with data engineers to define feature stores, data quality checks, and model-ready datasets on platforms like Snowflake or Databricks. Perform feature selection, transformation, and engineering aligned with each domain s business logic. 5. Communication Stakeholder Collaboration Present technical insights and model results to business and executive stakeholders in a clear, actionable format. Work with Product Owners and Program Managers to scope, prioritize, and plan delivery of ML projects. Qualifications Required: 4+ years of experience in machine learning, data science, or AI engineering, with a strong software engineering foundation. Proficiency in Python, and libraries such as scikit-learn, XGBoost, PyTorch, TensorFlow, or similar. Experience deploying models into production using ML pipelines and orchestration frameworks. Strong understanding of data structures, SQL, and cloud platforms (e.g., AWS SageMaker, Azure ML, or GCP Vertex AI). Preferred: Experience supporting business functions such as Finance, Sales, or Operations with ML use cases. Familiarity with MLOps tools (MLflow, SageMaker Pipelines, Feature Store). Exposure to enterprise data platforms (e.g., Snowflake, Oracle Fusion, Salesforce). Background in statistics, forecasting, optimization, or recommendation systems. Careers Privacy Statement Keysight is an Equal Opportunity Employer.1. Machine Learning Development Deployment Design and implement supervised and unsupervised models for predictive analytics, including churn prediction, demand forecasting, renewal risk scoring, and cross-sell/upsell opportunity identification. Translate business problems into ML frameworks and production solutions that improve efficiency, revenue, or customer experience. Build, optimize, and maintain ML pipelines using tools such as MLflow, Airflow, or Kubeflow. 2. Cross-Functional ML Use Cases Partner with teams across Sales (e.g., lead scoring, next-best action), Customer Service (e.g., case deflection, sentiment analysis), Finance (e.g., revenue forecasting, fraud detection), Supply Chain (e.g., inventory optimization, ETA prediction), and Order Fulfillment (e.g., delivery risk modeling) to define impactful ML use cases. Develop domain-specific models and continuously improve them using feedback loops and real-world performance data. 3. Model Governance and MLOps Ensure robust model monitoring, versioning, and retraining strategies to keep models reliable in dynamic environments. Work closely with DevOps and Data Engineering teams to automate deployment, CI/CD workflows, and cloud-native ML infrastructure (AWS/GCP/Azure). 4. Data Engineering and Feature Architecture Collaborate with data engineers to define feature stores, data quality checks, and model-ready datasets on platforms like Snowflake or Databricks. Perform feature selection, transformation, and engineering aligned with each domain s business logic. 5. Communication Stakeholder Collaboration Present technical insights and model results to business and executive stakeholders in a clear, actionable format. Work with Product Owners and Program Managers to scope, prioritize, and plan delivery of ML projects.

Bring substantial experience in effective team management to help mentor, coach and grow the Physical Design and Implementation team with an emphasis on positive influence on team morale and culture Will be responsible for delivering silicon for a wide range of applications Primarily a management position, however, the candidate is required to have significant RTL to GDSII knowledge to probe into technical details Candidate will be required to collaborate and foster good relationship with all parts of engineering: Architecture team, Front End Design teams and Program management Qualifications Minimum 15 years of ASIC physical design experience Minimum 5 years of management experience with leading a physical design and implementation teams from RTL-to-GDSII Should have excellent collaboration and teamwork capabilities across various chip development disciplines. Will be responsible to hire talent and mentor, build expertise, and grow each team member Ability to define and drive flows and methodologies to optimize physical design work, define guidelines and checklists, drive execution, and track progress Ability to resolve design and flow issues related to physical design through the identification of potential solutions and drive resolution Experience in working with the front-end teams to understand chip architecture and drive physical aspects early in the definition cycle Experience working relationships with EDA Vendors Multiple successful tape out Excellent communication (oral and written) skills Ability to present to and interface with internal customers Ability to handle a dynamic environment and to coordinate team action Bachelor s Degree in Electrical Engineering or closely related discipline is required Masters Degree in Electrical Engineering or closely related discipline is preferred Company Overview MaxLinear is a global, NASDAQ-traded company (MXL) where the entrepreneurial spirit is alive and well. We are a fabless system-on-chip product company, striving to improve the world s communication networks for everyone through our highly integrated radio-frequency (RF), analog, digital, and mixed-signal semiconductor solutions for access and connectivity, wired and wireless infrastructure, and industrial and multi-market applications. We hire the best people in the industry and engage them in some of the most exciting opportunities that connect the world we live in today. Our growth has come from innovative, bold approaches to solving some of the world s most challenging communication technology problems in the most efficient and effective manner. MaxLinear began by developing the world s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn t achieve the extremely high-performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we ve developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments. Over the years, we ve expanded through organic growth and through several acquisitions that have perfectly complemented our existing portfolio and enabled us to deliver complete end-to-end solutions in our target markets. One such example was the acquisition of Intel s Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers needs. Our headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Waltham, Massachusetts; Vancouver, Canada; Valencia, Spain; Bangalore and Chennai, India; Villach, Austria; Munich, Germany; Israel; and Singapore. We have approximately 1,500 employees, a substantial majority of whom have engineering degrees and include masters and Ph.D. graduates from many of the premiere universities around the world. Our employees thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building the best and most innovative products on the market.

Leading the design,development, and implementation of high speed boards for servers, includingprocessors, memory, storage, and network interfaces. Experience in full HDLC like schematic design, PCB layout, SI-PI, mechanicaland software integration. Experience in High Speed board design with interfaces like PCIe 5.0,LPDDR4/5,SSD s,M.2,U.2 NVMe, SATA, CXL, USB, Ethernet. etc Understanding customer requirements,translating them into technical specifications, and working with otherdepartments to ensure a robust and scalable solution . Who you are Hands on experience in server class of board design with AMD or Intel GPU s,with high speed interfaces like PCIe 5.0,LPDDR4/5, SSD s,M.2,U.2 NVMe,SATA,CXL,USB, Ethernet. etc. Proficient in Design Architecturalanalysis, schematic design, BOM selection. Mentoring and guiding a team of hardwareengineers, providing technical expertise and support, and ensuring team membersadhere to industry standards. Collaborating with cross function team in managing PCB layout, SI-PI simulations,Software development, mechanical, thermal and other stakeholders to ensure acohesive and efficient system design. Experience with relevant design tools like Altium and orcad. Hands onexperience in Hardware Development Life Cycle like design, bringup, testing andvalidation of boards, functional testing, trouble shooting, debugging andFailure analysis. Hand on experience in using instrumentslike high speed Oscilloscopes, DMM, electronic loads etc. Expertise on PCB design process, Technical document writing. GoodCommunication and interpersonal skills

The group you ll be a part of In the Global Products Group, we are dedicated to excellence in the design and engineering of Lams etch and deposition products. We drive innovation to ensure our cutting-edge solutions are helping to solve the biggest challenges in the semiconductor industry. The impact you ll make As a Software Engineer at Lam, you will be at the forefront of innovation by designing, developing, and troubleshooting, and debugging software programs. Your role is pivotal in developing software tools that support design, infrastructure, and technology platforms. Your expertise will determine hardware compatibility and influence design, ensuring seamless integration between software and hardware. In this role, you ll make an impact across Lam s entire product portfolio of equipment working within our centralized software engineering team, collaborating with some of the brightest minds in the industry. What you ll do Design, develop, troubleshoot, and debug software programs for enhancements and new products. Implement new customer requirements and features in our existing application. Maintain and enhance existing code base by investigating and resolving problem areas. Demonstrate, clearly communicate, and present solutions through clear documentation, flowcharts, and well-structured code. Collaborate with cross functional teams to design and develop software programs. Provide technical guidance and mentoring for more junior engineers. May visit customer site to provide support and have ability to travel (total is less than 10%). Who we re looking for Minimum Qualifications: Bachelor s degree in Computer Engineering, Electronics, Mechanical Engineering with 12+ years of experience; or Master s degree with 8+ years experience; or a PhD with 5+ years experience; or equivalent experience. Knowledge of Object-Oriented Software (OOS), Object Oriented Design (OOD), or Object-Oriented Programming (OOP) implementation and design, including Design Patterns and Finite State Machines. Knowledge of multithreading, including preemptive thread scheduling. Knowledgeable with communication protocols such as Inter-Integrated Circuit (I2C), Service Provider Interface (SPI), Universal Asynchronous Receiver-Transmitter (UART). Preferred qualifications Prior semiconductor equipment experience. Experience in distributed embedded controls system desired. Software development skills in one or more general purpose programming languages: C++, C#. Our commitment We believe it is important for every person to feel valued, included, and empowered to achieve their full potential. By bringing unique individuals and viewpoints together, we achieve extraordinary results. Lam Research ("Lam" or the "Company") is an equal opportunity employer. Lam is committed to and reaffirms support of equal opportunity in employment and non-discrimination in employment policies, practices and procedures on the basis of race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, genetic information, marital status, sex (including pregnancy, childbirth and related medical conditions), gender, gender identity, gender expression, age, sexual orientation, or military and veteran status or any other category protected by applicable federal, state, or local laws. It is the Companys intention to comply with all applicable laws and regulations. Company policy prohibits unlawful discrimination against applicants or employees. Lam offers a variety of work location models based on the needs of each role. Our hybrid roles combine the benefits of on-site collaboration with colleagues and the flexibility to work remotely and fall into two categories - On-site Flex and Virtual Flex. On-site Flex you ll work 3+ days per week on-site at a Lam or customer/supplier location, with the opportunity to work remotely for the balance of the week. Virtual Flex you ll work 1-2 days per week on-site at a Lam or customer/supplier location, and remotely the rest of the time.

The Group You ll Be A Part Of In the Global Products Group, we are dedicated to excellence in the design and engineering of Lam s etch products. We drive innovation to ensure our cutting-edge solutions are helping to solve the biggest challenges in the semiconductor industry The Impact You ll Make As a Mechanical Engineer at Lam, youre designing and defining cutting-edge mechanical and electro-mechanical systems. Your role involves feasibility studies, testing, and guiding teams in detailed design and fabrication. You provide the crucial design information needed to shape our technologys packaging. In this role, you will directly contribute to you will directly contribute to the design and development of sub-systems and assemblies used in Semi-conductor machines. What You ll Do Responsible & accountable to execute multi-discipline (Mechanical, Thermal) & multi-domain (CFD, Ceramic materials, coating technologies) engineering problems with full ownership - Concept maturity, Engineering, Testing & Deployment Responsible to lead a team of Engineers to drive engineering excellence, optimize and implement solutions for projects as part of trouble shooting at customer or supplier end, continuous improvement programs (CIP), cost reduction, reliability improvement and RCCAs Support staffing, training, mentoring & coaching, and strategic planning to build capacity and capability. Lead medium to high complex sub-system related projects with full ownership through product life cycle of mechanical and electro-mechanical systems from concept to productization including, designing, CAD modeling, development, and testing / validation.. Lead design reviews, project reviews and participate in technical discussions. Collaboration with cross functional teams to develop robust design solutions. Who We re Looking For Minimum Qualifications: Bachelor s degree in Mechanical Engineering or related field with 8+ years of experience; or Master s degree with 6+ years experience; or equivalent experience. Excellent communication, both written and verbal, and technical presentation skills. Highly proficient in 3D CAD tools such as Siemens NX Preferred Qualifications Experience in Semiconductor industry is a plus. Experience in leading projects, or problem solving while managing time and multiple priorities. Our Commitment We believe it is important for every person to feel valued, included, and empowered to achieve their full potential. By bringing unique individuals and viewpoints together, we achieve extraordinary results. Lam Research ("Lam" or the "Company") is an equal opportunity employer. Lam is committed to and reaffirms support of equal opportunity in employment and non-discrimination in employment policies, practices and procedures on the basis of race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, genetic information, marital status, sex (including pregnancy, childbirth and related medical conditions), gender, gender identity, gender expression, age, sexual orientation, or military and veteran status or any other category protected by applicable federal, state, or local laws. It is the Companys intention to comply with all applicable laws and regulations. Company policy prohibits unlawful discrimination against applicants or employees. Lam offers a variety of work location models based on the needs of each role. Our hybrid roles combine the benefits of on-site collaboration with colleagues and the flexibility to work remotely and fall into two categories - On-site Flex and Virtual Flex. On-site Flex you ll work 3+ days per week on-site at a Lam or customer/supplier location, with the opportunity to work remotely for the balance of the week. Virtual Flex you ll work 1-2 days per week on-site at a Lam or customer/supplier location, and remotely the rest of the time.

We are seeking a Principal Analog Design Engineer to lead the architecture, design, and development of Power Management ICs (PMICs). This is a high-impact technical leadership role, focused on designing complex, high-performance analog and mixed-signal circuits with emphasis on quality, reliability, and innovation. Key Responsibilities Define architecture and lead transistor-level design of analog and mixed-signal blocks for PMICs, including: LDOs, DC-DC converters (Buck/Boost), Voltage supervisors, Power sequencing, Load switches, Bandgap references, Oscillators, and Bias circuits Drive system-level specification and partitioning in collaboration with Systems and Application teams Perform pre- and post-layout simulations and analysis across PVT corners using industry-standard EDA tools Work closely with layout engineers to optimize performance, area, and noise/EMI sensitivity Collaborate with cross-functional teams across design, verification, test, validation, and reliability Ensure designs meet functional safety, reliability, and regulatory compliance standards Support silicon bring-up, characterization, and debug Mentor junior designers and lead design reviews Promote IP reuse, documentation best practices, and patent/IP generation initiatives Qualifications Bachelor s, Master s, or PhD in Electrical Engineering or related field 15+ years of hands-on experience in analog/mixed-signal IC design, with a focus on PMICs Deep expertise in analog circuit design, power management, and system-level integration Familiarity with ISO 26262, AEC-Q100, and other quality/reliability standards Strong experience with Cadence tools and analog simulation methodologies Demonstrated leadership in delivering complex designs from concept to production Excellent problem-solving, communication, and collaboration skills Experience with high-voltage BCD processes (e.g., 40V/60V) Proven track record of successful silicon tape-outs and production ramp Knowledge of industry design standards and practices for reliability and safety Understanding of layout impact on analog performance and EMC/EMI mitigation We recognize and appreciate the value and contributions of individuals with diverse backgrounds and experiences and welcome all qualified individuals to apply. Equal Opportunity Employer: Disability/Veteran Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Backed by top angels in India and the USA, Suitable ai raised a pre-seed round in 2022. a) Speed: Suitable AI provides enterprises with a TAT from the date of job activation to the date of release of a first offer of just ~10 days (The fastest was 3 days as well), b) Quality: A client on the Suitable AI platform shortlists ~80% of all resumes shared, indicating high-quality CV curation. Screening resumes submitted by the best agencies ensures a high Client Shortlist Rate (CSR), c) Scale: 1000+ screened and vetted resumes are uploaded on the platform every month. Moreover, long-tail mid-market firms who struggle to capture supplier attention due to their limited size, are now able to fill positions efficiently given Suitable AI's base, Key Responsibilities:. Develop recruiting strategies for identifying candidates, Manage end-to-end recruitment, from sourcing to data validation, Responsible for creating a medium to large-sized recruiting pipeline, meeting requirement targets, and providing regular status reports, Draft recruitment job advertisements for advertising on job portals and social media platforms, Source and find qualified candidates for open positions using various sources such as resume databases (Naukri, Insthyre, LinkedIn, etc,), job postings, social media campaigns, networking, career fairs, and phone calls, Create and maintain databases for candidates along with corresponding resume database, Maintain contact with candidates to keep them apprised of the status of their applications, Proposal and offer negotiation, Perform analysis of hiring needs and provide employee hiring forecasts, Plan and execute selection procedures within predefined recruitment processes (conduct interviews and screening calls, technical interviews, etc,), Find bottlenecks in the recruiting process, Use different sourcing methods for hard-to-fill roles, Maintain a right flow of communication and open culture within the team, Day-to-day grievance handling of team members, Guide, mentor, and delegate tasks to team members, Motivate and engage the team to achieve goals, Requirements:. 2-4 Years of proven experience as a Technical Recruiter or similar role, Must have experience in Contractual hiring. Minimum 2 years of experience working in core recruitment consulting companies, In-depth knowledge of the full recruitment cycle and different sourcing techniques, Excellent written and verbal communication skills, Knowledge of office tools (MS Office, MS Excel, etc,) for proofreading, editing, and formatting, Experience using different job portals such as Naukri, Insthyre, LinkedIn, and Indeed, Technical qualification preferred (B-Tech/BCA/BSc(IT)/MCA/m-tech), Self-confidence and self-starter, Ability to learn technical information, Adaptable, enthusiastic, and energetic, Goal-oriented, self-starter, team player, and a quick learner, Experience with Aerospace ,semiconductors profile hiring is a plus and good to have. Perks and Benefits:. Competitive Salary as per Market standards, Revenue sharing, Referral Bonus, Rewards and Recognition program, Periodic Training & Development sessions for professional development, Work-life balance (5 working days), Fun Fridays and outdoor trips, Medical insurance. Show more Show less

Principal DFT Engineer (MBIST) in Pune, MH, India Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: The ideal candidate will work with multi-functional global teams to design, implement and verify Boundary Scan, ATPG (Stuck-AT/AT-Speed) SCAN, MBIST, IO BIST and JTAG/IJTAG DFT features on our next generation highly complex server class processor products. Will work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug. What youll achieve: DFT features like EDT, SSN, shared bus based MBIST insertion, ijtag, simulation and debug on RTL and gates netlist Boundary Scan insertion, simulation and verification Scan insertion, Scan compression, Stuck-At, At-Speed test and coverage analysis Scan ATPG pattern generation, simulation and debug on RTL and gates netlist Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification (Mentor, Cadence, Synopsys) STA DFT Test mode timing constraint development and analysis In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data Bachelors degree & 8 years of related experience or Masters degree & 6 years of related experience Expert with methods and techniques to design, implement and verify regular and shared bus based Memory BIST on repairable and non-repairable memories using Electrical fuses. Expert knowledge and practical work experience partnering with designers to implement highly customized and tools-driven MBIST solutions. Solid understanding of MBIST algorithms needed for 5nm and lower technology nodes and ability to code new algorithms, operation sets supporting tool driven solutions. Experience in implementing EDT, SSN, boundary scan, jtag/ijtag features. Work independently to generate test plans, run simulations and debug failures on RTL and Gate Level Hands on experience in the usage of industry standard tools, like Siemens Tessent Shell flow, or Synopsys SMS/SHS flow Expert understanding tradeoffs to optimize coverage and test time reduction with the ability to foresee physical implementation and timing challenges during early development. Experience in working with physical design teams to support STA constraints, reviewing timing reports. Expert in using silicon debug/diagnosis tools to root cause silicon bringup and production test issue. Experience in setting up and running Scan DRC flows in RTL. Experience with industry standard simulation tools, including Verilog, and scripting languages like Perl, Python, Shell or Tcl. Experience in revision control systems like GIT, perforce etc.. Needs in depth experience in stuck at, transition delay, path delay, etc. coverage loss analysis and identifying solutions to improve test coverage Experience in leading the effort to derive cell aware fault models and develop necessary flows to generate ATPG and to support silicon debug. Good knowledge of functional safety, clock domain crossing analysis, logic synthesis and scan insertion At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Principal DFT Engineer (MBIST) in Bangalore, KA, India Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: The ideal candidate will work with multi-functional global teams to design, implement and verify Boundary Scan, ATPG (Stuck-AT/AT-Speed) SCAN, MBIST, IO BIST and JTAG/IJTAG DFT features on our next generation highly complex server class processor products. Will work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug. What youll achieve: DFT features like EDT, SSN, shared bus based MBIST insertion, ijtag, simulation and debug on RTL and gates netlist Boundary Scan insertion, simulation and verification Scan insertion, Scan compression, Stuck-At, At-Speed test and coverage analysis Scan ATPG pattern generation, simulation and debug on RTL and gates netlist Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification (Mentor, Cadence, Synopsys) STA DFT Test mode timing constraint development and analysis In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data Bachelors degree & 8 years of related experience or Masters degree & 6 years of related experience Expert with methods and techniques to design, implement and verify regular and shared bus based Memory BIST on repairable and non-repairable memories using Electrical fuses. Expert knowledge and practical work experience partnering with designers to implement highly customized and tools-driven MBIST solutions. Solid understanding of MBIST algorithms needed for 5nm and lower technology nodes and ability to code new algorithms, operation sets supporting tool driven solutions. Experience in implementing EDT, SSN, boundary scan, jtag/ijtag features. Work independently to generate test plans, run simulations and debug failures on RTL and Gate Level Hands on experience in the usage of industry standard tools, like Siemens Tessent Shell flow, or Synopsys SMS/SHS flow Expert understanding tradeoffs to optimize coverage and test time reduction with the ability to foresee physical implementation and timing challenges during early development. Experience in working with physical design teams to support STA constraints, reviewing timing reports. Expert in using silicon debug/diagnosis tools to root cause silicon bringup and production test issue. Experience in setting up and running Scan DRC flows in RTL. Experience with industry standard simulation tools, including Verilog, and scripting languages like Perl, Python, Shell or Tcl. Experience in revision control systems like GIT, perforce etc.. Needs in depth experience in stuck at, transition delay, path delay, etc. coverage loss analysis and identifying solutions to improve test coverage Experience in leading the effort to derive cell aware fault models and develop necessary flows to generate ATPG and to support silicon debug. Good knowledge of functional safety, clock domain crossing analysis, logic synthesis and scan insertion At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Minimum qualifications:. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.. 3 years of experience with functional tests for silicon validation (e.g., C, C++ or Python) or developing embedded software.. Experience in silicon bring up, functional validation, characterizing, and qualifying silicon.. Experience with board schematics, layout, and debug methodologies using lab equipment.. Preferred qualifications:. Experience in hardware/software integration (i.e. pre-silicon use of emulation and software-based test and diagnostics development).. Experience in scripting languages, such as Python for Automation development.. Experience with Power Characterization, PCIe, DDR.. Experience in RTL design, verification or emulation.. Knowledge of SoC architecture, including boot flows.. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.. In this role, you will be responsible for post-silicon validation of the Cloud TPU projects. You will create test plans and test content for exercising the various subsystems in the AI/ML SoC, verify the content on pre-silicon platforms, execute the tests on post-silicon platforms, and triage and debug issues. You will work closely with engineers from architecture, design, design verification, and software/firmware teams. You will be validating the functional, power, performance, and electrical characteristics of the Cloud Tensor Processing Unit (TPU) silicon to help deliver quality designs for next generation data center accelerators.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.. Responsibilities. Develop and execute tests in post-silicon validation and on HW emulators and assist in bring-up processes from prototyping through post-silicon validation.. Drive debugging and investigation efforts to root-cause cross-functional issues. This includes pre-silicon prototyping platforms as well as post-silicon bring up and production.. Ensure validation provides necessary functional coverage for confident design.. Help operate and maintain our hardware emulation platform for pre-silicon integration and validation.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

At Oxford Instruments, we enable the world’s leading industrial companies and scientific research communities to image, analyse and manipulate materials down to the atomic and molecular level. With a sixty-year history, and fourteen Queen’s Awards for Enterprise, our world-class products and technologies are helping our customers to address the greatest challenges of the 21st century.. Primary Purpose:. Support PT’s customers in India on new tool installs, upgrade, warranty support and billable service, and based in Delhi / Mumbai / Chennai.. Key Responsibilities:. New tools install and commissioning: follow QCF300 commissioning guide to install and commissioning the new tools. This will involve domestic and overseas travels.. Upgrades: follow upgrade SOPs to install and commissioning upgrades.. Warranty Support: maintain and sustain the warranty tools, and troubleshoot and repair the warranty tool issues.. Billable Service: carrier out billable service and training on out of warranty tools.. Typical Performance Measures:. Meet targeted numbers of new tool installs within a certain period of time and spec.. Meet targeted numbers of billable upgrades and PMs within spec.. Meet good customer satisfaction on warranty support.. Follow up the reporting and documentation requirements for every service activity.. Stocks and materials RMA assistance.. Education / Qualifications. Person Specification – Essential requirements unless stated. A relevant engineering degree. EE or ME engineering preferred.. Significant hardware experience on semiconductor equipment.. Professional Skills/ Abilities. Able to look up electrical drawings.. Familiar with Vacuum and RF components operating mechanism and theory.. Logical thinking on tool issues troubleshooting.. Prefer the work experience with either Ion Beam (Deposition or Etch) or PECVD / ICPCVD / ALD or RIE / ICP tools.. Mater at communication and negotiation in English.. Personal Qualities:. Able to work independently.. Prepare proactively and act efficiently. Positive thinking and easy going with. Willing to take responsibility and own accountability. Willing to take challenges and accept to travel frequently.. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, or disability.. Show more Show less

Minimum qualifications:. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.. 5 years of experience in architecture, hardware, digital design, and software co-design. 3 years of experience in Verilog/SystemVerilog.. Experience in computer architecture and digital design or Internet Protocol (IP) integration (e.g., Peripheral Component Interconnect Express (PCIe), Double Data Rate (DDR) memory).. Preferred qualifications:. Master's degree in Electrical Engineering, Computer Science, or a related field.. 4 years of experience working on Field Programmable Gate Array (FPGA) platforms or Emulation platforms with Internet Protocols (IPs) (e.g., Peripheral Component Interconnect Express (PCIe), Double Data Rate (DDR) memory, Gigabit Ethernet, Flash).. Experience in developing architectures for Machine Learning Accelerators.. Experience in writing or debugging Verilog/Register-Transfer Level (RTL) code for ASIC/FPGA designs, waveform debug skills with knowledge of chip design flows.. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.. In this role, you will integrate hardware and software stacks and operate them on emulation platforms for pre-silicon validation of our Google Cloud Tensor Processing Unit (TPU) projects. You will create software-based custom test cases, workloads, test generators, infrastructure, analysis tools, and debugging tools. You will be responsible for silicon bring-up, validation, characterization and qualification, and sustaining programs and their quality. You will help ensure our fleet runs at maximum efficiency, and help debug and root when causing issues. You will collaborate with Product Firmware, System Software and Application-Specific Integrated Circuit (ASIC) Design in the development of tools, validation firmware, functional and performance tests, and testing infrastructure for our platforms and Google Cloud data center systems.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.. We prioritize security, efficiency, and reliability across everything we do from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.. Responsibilities. Enable bring-up of chip features through firmware and driver stack. Integrate and validate hardware and software designs in pre-silicon.. Architect and design Application-Specific Integrated Circuit (ASIC) models for Emulation/Field Programmable Gate Array (FPGA) Prototypes. Design Register-Transfer Level (RTL) transformations to optimize mapping to Emulation/FPGA platforms and design solutions to improve Internet Protocol (IP) modeling.. Design solutions to improve hardware modeling accuracy and scale to various system configurations and enable serving of ASIC models for software and validation teams.. Bringup chip features on software reference models and hardware prototypes (e.g., Emulation/FPGA) and drive debug discussions with design/design validation/physical design/software/architecture teams and help root-cause failures.. Develop the integration plan with software and system partners, coordinate hardware and software delivery and benchmark performance.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

Minimum qualifications:. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.. 5 years of experience in High Bandwidth Memory/Double Data Rate (HBM/DDR).. Experience in silicon bringup, functional validation, characterizing, and qualification.. Experience with board schematics, layout, and debug methodologies with using lab equipment.. Preferred qualifications:. Experience in hardware emulation with hardware/software integration.. Experience in coding (e.g., Python) for automation development.. Experience in Register-Transfer Level (RTL) design, verification or emulation.. Knowledge of SoC architecture including boot flows.. Knowledge of HBM/DDR standards.. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.. In this role, you will be responsible for post-silicon validation of the Cloud Tensor Processing Unit (TPU) projects. You will create test plans and test content for exercising the various subsystems in the Artificial Intelligence/Machine Learning (AI/ML) System on a Chip (SoC), verify the content on pre-silicon platforms, execute the tests on post-silicon platforms, and triage and debug issues. You will work with engineers from architecture, design, design verification, and software/firmware teams. You will be validating the functional, power, performance, and electrical characteristics of the Cloud Tensor Processing Unit (TPU) silicon to help deliver high-quality designs for next generation data center accelerators.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.. We prioritize security, efficiency, and reliability across everything we do from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.. Responsibilities. Develop and execute tests for memory controller High Bandwidth Memory (HBM) post-silicon validation and on hardware emulators and assist in bring-up processes from prototyping through post-silicon validation.. Drive debugging and investigation efforts to root-cause, cross-functional issues. This includes pre-silicon prototyping platforms as well as post-silicon bringup and production.. Ensure validation provides necessary functional coverage for skilled design.. Help operate and maintain our hardware emulation platform for pre-silicon integration and validation.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

Senior Staff/Staff Field Application Engineer with Power electronics background and experience in control Algorithms.. Job Description. In your new role you will:. Actively working towards achieving the Design Win Targets of the Automotive segment products in India.. Technical support to direct OEMs/Tier-1s, distribution customers and design-houses to enable rapid adoption of Infineon products.. Working dedicatedly on joint development projects with customers as and when needed.. Working closely with Sales/Marketing, Distribution, Application Engineers in other regions to achieve the targets & collaborate.. Performing technical analysis of circuits/boards to resolve issues or meet customers’ criteria or benchmarking against competitors’ products.. Working on proof of concepts/demonstrators/reference solutions to support customers & build system knowledge.. Capturing & feeding the regional requirements, product issues/fixes &improvement ideas to Headquarters through Regional Centre.. Preparing the training material & conducting technical trainings, workshops and seminars in India.. Preparing presentations, technical documents, application notes, SAE Papers, Patent Ideas, etc.. Troubleshooting of FAR issues on application level and propose effective solutions.. Your Profile. You are best equipped for this task if you have:. BE / BTECH / ME / MTECH in Electrical/Electronics engineering with 5+years of experience in Power Electronics with good understanding of control algorithms would be added advantage.. Contact:. Jyoti.vimal@Infineon.com. #WeAreIn for driving decarbonization and digitalization.. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.. Are you in?. We are on a journey to create the best Infineon for everyone.. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicants experience and skills.. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.. Click here for more information about Diversity & Inclusion at Infineon.. Show more Show less

Join our team and unlock your potential in the world of Semiconductor. We are looking for #TrainedFresher and. #internship in #analogLayout. Preferred Qualifications:. Knowledge of SiGe and CMOS technology nodes 45/32/28nm and below is an advantage. Hands-on knowledge of state-of-the-art analog design flows and knowledge of ADC, DACs is a plus. Good publication and patent record. Dedication and the ability to work within a very dynamic interdisciplinary environment. Ability to communicate as well as work efficiently in an international multi-disciplinary environment.. Exceptional spoken and written Proficiency in English. Strong analytical and problem-solving skills.. Percentage : min 70%,. internship completed engineers with hands on exp on layout will be preferred. #Intern and #trained candidates only considerable.. Explore exciting career opportunities at www.Digicommsemi.com. Show more Show less

Keysight Technologies is looking for R&D Engineer 1, Software to join our dynamic team and embark on a rewarding career journey Lead and contribute to complex R&D projects from concept to completion, including design, development, testing, and implementation of new products or technologies. Collaborate with cross-functional teams, including scientists, engineers, and product developers, to define project goals, scope, and requirements. Conduct thorough literature reviews, market analysis, and feasibility studies to guide project planning and decision-making. Design and execute experiments, prototypes, and proof-of-concept studies to validate new concepts and technologies. Analyze experimental data using advanced statistical methods and contribute to the interpretation of results. Mentor and provide technical guidance to junior engineers and team members. Stay abreast of industry trends, emerging technologies, and competitive landscapes. Ensure compliance with safety regulations, quality standards, and intellectual property considerations. Prepare detailed technical reports, documentation, and presentations for internal and external stakeholders. Assist in the development and optimization of research methodologies and engineering protocols.

Design of DC-DC High Frequency Switching Power Supplies using ADI s large portfolio of Power Management Integrated Circuits. New DC-DC Monolithic (Integrated Power and Controller) Power Products definition. Validation of the new generation Power Management Integrated Circuits. Full product life-cycle ownership - Definition, Validation and Market Introduction. Responsibilities include: Development of product evaluation kits and system reference design boards Circuit schematic design and PCB layout creation Performance optimization and characterization in application circuits Validate new products, creating new test methodologies. Data collection for datasheets and release notes Collate results with design and test engineers. Technical support to key customers and field engineers Simulation of Power Electronics Converters Minimum Requirements: Masters degree in Power Electronics At least 4+ years of hands-on experience in developing switching power supplies. Basic understanding of transistor-level analog circuit design Strong written and verbal communication skill Want to make a difference and take on challenges every dayJoin us at Analog Devices. With analog integration, the possibilities are endless.

As a Principal Test Engineer, you will play a crucial role in delivering world class test solutions with high quality and low cost of test for a fast growing business. Your responsibilities will include: Implementing ATE test solutions for final test, characterization, WT in both engineering and production Deliver test programs in languages such as C, or C++ to automate test processes Collaborating with cross-functional teams including design engineers, manufacturing teams, and quality assurance (QA) teams to address technical issues and optimize testing processes. Analyzing test results, identifying trends, troubleshooting issues, and generating detailed test reports and documentation. Staying updated with industry trends, advancements, and best practices in semiconductor testing methodologies. Mentoring of junior engineers Establish test deliverables Qualifications A minimum of a bachelor s degree in electrical, computer engineering or other degree with adequate coursework in electronics, programming, physics, etc. Experience in working with Automotive IC s is a plus. Test Engineer with 7+ Years experience developing hardware and software at Wafer Sort and Final Test for Power Management IC products. Experience using Advantest 93k, Eagle, SPEA, Cohu Diamondx or equivalent tester. A strong understanding of board design software(Cadence, Orcad, Altium, etc) Experience using I2C, I3C, and SPI protocol as well as trim implementations for power IC products Understand and apply best practices to develop robust test solutions at the lowest cost. Experienced with various test deliverables like GR&R, Sampling, Qual, Characterization, Production Test Self-starter, motivated, takes initiative, and able to work independently Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Job Summary: We are seeking a highly motivated and technically proficient Systems & Applications Engineer to join our team. The ideal candidate will have hands-on experience in embedded systems, power management solutions, and customer-facing technical support. You will be responsible for system-level design, testing, and support for electronic components and applications, collaborating with cross-functional teams to deliver high-quality solutions. Key Responsibilities: Provide system-level support for power management products. Collaborate with customers to recommend products, review schematics, and debug board layouts. Conduct lab testing and failure analysis to resolve device and application issues. Develop and release evaluation modules, PSpice models, and design calculators for new product launches. Create technical collateral such as application notes, videos, and design tools. Lead customer support initiatives through various platforms. Work with certification bodies (UL, IEC) to ensure compliance of devices. Mentor junior engineers and interns. Required Skills: Proficiency in C, C++, Python, VHDL, MATLAB Experience with Embedded Systems , Raspberry Pi , PSpice , LTspice , HFSS , Altium Designer Strong analytical and debugging skills Excellent communication and collaboration abilities Familiarity with system-level design and testing methodologies Preferred Qualifications: Published technical articles or patents in the field of electronics Experience in developing GUI applications for embedded platforms Knowledge of industry standards like UL2367, IEC62368-1/3 Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Take over responsibility of assigned product groups Overview & understanding of all relevant topics in BlueYonder (BY) planning Ensuring good plan quality of BY planning system Being first point of contact for BY topics for logistics planner of ME Semiconductor Support in finding process solutions and driving analysis Training of new end users Coordination and representation of logistics topics / stories in the Design Authority Board (DAB) of ME Semiconductor and in the sprint planning of BY Deep system understanding in terms of how the planning parameters impact the overall plan quality Create and validate complex BY processes, through scenario planning Joint development and validation of improvements in BY with experts and users Definition and establishment of new processes including ensuring process compliance