868 Uvm Jobs - Page 27

Role & responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Preferred candidate profile Bachelors/ Masters degree or higher in EEE/ECE 4+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

Principal Design Verification Engineer (India) Bangalore (Hybrid ) / Hyderabad (Hybrid ) Principal Design Verification Engineer (India) India Company Background We areon a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, We are unleashing the revolution in next-gen computing fabrics. Summary Join an ambitious, experienced team of silicon and distributed systems experts as a design verification engineer. You have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and to help solve key infrastructure challenges facing our customers. We are looking for talented, motivated candidates with experience designing and verifying large-scale networking and computing chips, and who are looking to grow in a fast paced, dynamic startup environment. We seek experienced verification engineers who can contribute across the full lifecycle of complex chip development, from microarchitecture definition to DV infrastructure and test development, to post-silicon testing. Roles and Responsibilities Collaborate with world-class distributed systems hardware and software architects to transform product vision and behavioral specifications into efficient, comprehensive block-level and top-level tests which achieve outstanding coverage. Incorporate state-of-the art verification techniques to efficiently tackle the demanding scale and performance requirements of a functionally complex device. Define and implement infrastructure for effective HW/SW co-simulation. Execute on a verification strategy which ensures that the prototype meets both the device level specifications as well as the system-level requirements. The ideal candidate should have the versatility to build infrastructure and tests that can be leveraged across both ASIC and FPGA platforms. Skills/Qualifications Proven industry experience and successful track record in verifying chip- and block-level RTL designs for high-performance networking or computing chips, such as Network Interface Controllers, Smart-NICs, DPUs, accelerators, and/or switches in advanced silicon geometries. DDR5 Deep experience with full chip verification and infrastructure development. Strong current knowledge of UVM constructs, components, and practices. Expert knowledge of SystemVerilog, as well as Python or other scripting languages. Experience with C/C++ and general software engineering principles is highly desirable. Minimum BSEE/CE + 12-17years or MSEE/CE + 12-15 years experience. Proven track record of design execution and quality on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

What Youll Work On: Develop and execute UVM-based testbenches for IP/SoC verification Write test plans, assertions, and coverage to ensure design quality Debug issues in simulation and collaborate with design & DFT teams Work on block-level and system-level verification Use tools like VCS, Questa, Verdi, Jasper , etc. What We’re Looking For: 3+ years of hands-on experience in UVM/RTL verification Strong understanding of verification methodology, SystemVerilog, SVA Experience with debugging tools and coverage analysis Solid scripting skills (Python/TCL/Perl) a big plus Exposure to complex SoCs or multi-clock domain verification is a bonus

Develop verification environments for our ICs using Universal Verification Methodology (UVM); Job Description In your new role you will: create and define verification plans; develop verification environments for our ICs using Universal Verification Methodology (UVM); draw on test scenarios using SystemVerilog; verify functionality using the Constrained Random approach; develop assertions in SystemVerilog for formal verification; Interact with other disciplines, such as Concept and ApplicationEngineering, to define verification plans and strategies; provide proactive support to users of our verification flowenvironment; be responsible for our verification methods; Your Profile You are best equipped for this task if you have: You have successfully completed a university degree in Electrical Engineering, Computer Science or a similar academic discipline; You have at least 3 years of experience in Constrained-Random Metric-Driven Verification You have capabilities and experience in working withmicrocontroller-based ICs, as well as security and safety requirements; You have good know-how with UVM especially using SystemVerilog; Have knowledge of firmware and RTL design (VHDL); Ideally have knowledge of working with Verification IPs (VIPs) Contact: swati.gupta@infineon.com We are on a journey to create the best Infineon for everyone.

Job Description Job Description We are seeking a highly skilled and experienced Staff Engineer for Functional Modeling & Verification to join our innovative team in Bengaluru, India. As a Staff Engineer, you will play a crucial role in shaping our technical direction, leading complex projects, and mentoring junior engineers. Lead architectural decisions and provide technical guidance to cross-functional teams Collaborate with product managers and other stakeholders to define technical requirements and solutions Conduct code reviews and ensure code quality across projects Mentor and guide junior engineers, fostering their professional growth Identify and resolve complex technical issues across multiple projects Stay current with emerging technologies and industry trends, recommending innovations to improve our tech stack Contribute to the development of engineering best practices and coding standards Participate in system design discussions and technical planning sessions Optimize existing systems for improved performance and scalability Hands-on experience in C++ & System C based Model development/test creation Prior Experience with C based Tests/Test bench development Python coding would be a plus Knowledge on NAND concepts will be an advantage Knowledge on Memory and Digital Design Concepts would be preferable (SRAM/DRAM/ROM/Flash) Circuits/Logic Participate in design / modeling reviews and provide technical guidance to junior engineers. Document all phases of Modeling releases and development for future reference and maintenance. Stay updated with the latest technologies and trends in NAND Flash and Modeling. Languages Expertise - C, C++, Python, System C, SystemVerilog/UVM will be a plus - Tool Expertise - VisualStudio, Git, Bitbucket Hands-on contributions coding C++ & System C models & test creation Debug issues in Firmware environment Validating the developed model using SV/UVM testbench Debug failures and root-cause it by interacting with other teams/groups Etc. Qualifications Qualifications Bachelors or Masters degree in Computer Science or a related field BE/BTech/ME/MTech in Engineering with Computer Science, ECE or related field

NVIDIA is seeking best-in-class Design Verification (DV) Engineers to verify world s leading Smart Network Interface Cards (Smart-NICs) and Data Processing Units (DPUs) which help accelerate network performance while reducing the CPU overhead of Internet Protocol (IP) packet transport, freeing more processor cycles to run applications. These networking processors also embed innovative hardware engines that offload and accelerate security with in-line encryption/decryption. With unmatched RDMA over Converged Ethernet (RoCE) performance, NVIDIA Smart-NICs and DPUs deliver efficient, high-performance remote direct-memory access (RDMA) services to bandwidth- and latency-sensitive applications. The Networking Chip Design in India is a new team which is growing at a fast pace. We are currently seeking an Experienced Verification Engineer with strong verification fundamentals to work in Networking Chip Design team. You will join a group of hardworking engineers to implement the next innovative Networking Silicon chip. You will work closely with architects, design engineers and verification engineers to accomplish your tasks. What youll be doing: Be responsible for verifying the smartNIC designs, architecture and micro-architecture using advanced verification methodologies. You are encouraged to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design. Come up with test plans, tests and verification infrastructure for complex IPs/sub-systems. Use advanced verification methodologies like e-specman, SV-UVM etc. What we need to see: BS (or equivalent experience) / MS with 4+ years of experience in design verification. Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.). C/C++ programming/scripting language experience desirable. Prior experience of smartNIC and/or high-speed interconnects. Strong debugging, problem-solving and analytical skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a phenomenal teammate. Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/ #LI-Hybrid

What You'll Be Doing: Developing emulation solutions for industry-standard protocols such as AXI, AMBA, JTAG, AVB, CAN, and TSN. Engaging in software development using C/C++ and synthesizable RTL development using Verilog. Verifying emulation solutions to ensure they meet the highest standards of quality and performance. Interacting with customers during the deployment and debugging phases to provide technical support and ensure successful implementation. Collaborating with cross-functional teams to integrate emulation solutions with other Synopsys products and technologies. Continuously improving and optimizing emulation solutions to meet evolving industry needs and standards. The Impact You Will Have: Enhancing the efficiency and performance of semiconductor design processes through advanced emulation solutions. Contributing to the development of high-performance silicon chips and software content that drive technological innovation. Supporting semiconductor customers in overcoming design and verification challenges, leading to successful product launches. Improving the reliability and functionality of emulation solutions, thereby increasing customer satisfaction and trust in Synopsys products. Driving continuous improvement and innovation within the emulation solutions domain. Facilitating seamless integration of emulation solutions with other Synopsys technologies, enhancing overall product offerings. What You'll Need: Strong programming skills in C/C++ and understanding of OOPS concepts. Good understanding of digital design concepts. Knowledge of HDL languages such as System Verilog and Verilog. Experience with scripting languages like Perl or TCL is a plus. Understanding of ARM architecture is an added advantage. Knowledge of UVM and functional verification will be a plus.

What You ll Be Doing: Making architectural decisions on test bench design. Writing verification plans and specifications. Implementing test bench infrastructure and writing test cases. Implementing a coverage-driven methodology. Leading technical aspects of verification projects. Collaborating with international teams of architects, designers, and verification engineers. The Impact You Will Have: Enhancing the robustness and reliability of IP cores used in critical applications. Driving innovation in verification methodologies and tools. Ensuring high-quality deliverables through rigorous verification processes. Improving productivity, performance, and throughput of verification solutions. Contributing to the success of Synopsys customers in industries such as AI, automotive, and server farms. Mentoring and guiding junior engineers in the verification domain. What You ll Need: Knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI. Hands-on experience with UVM/VMM/OVM, test planning, and coverage closure. Proficiency in SystemVerilog and UVM, object-oriented coding, and verification. Experience with scripting languages like C/C++, TCL, Perl, Python. Experience with functional safety standards such as ISO26262 and FMEDA (preferred). Who You Are: Independent and precise in your work. Innovative and proactive in problem-solving. Excellent communicator and team player. Detail-oriented with a strong analytical mindset. Eager to learn and grow within a technical role

We are seeking a highly motivated and skilled Design Verification Engineer with a strong background in UVM, SystemVerilog , and IP-level verification . The ideal candidate will be responsible for developing and executing robust testbenches, simulation, and debugging strategies to ensure first-time-right silicon. Key Responsibilities: Develop and maintain UVM-based verification environments for IP-level testbenches. Perform RTL and Gate-level simulation and debug functional issues. Define and execute comprehensive test plans to validate functional correctness. Integrate and verify AMBA bus protocols such as AHB and AXI. Develop and close assertions and functional coverage to meet verification completeness. Write reusable SystemVerilog assertions (SVA) and functional coverage models. Collaborate with design, architecture, and verification teams to debug and resolve complex issues. Utilize scripting languages ( Shell, Perl, Python ) to automate flows and enhance productivity. Participate in regular code reviews and contribute to verification process improvements. Communicate effectively across cross-functional teams and global engineering groups. Required Skills & Experience: Strong expertise in UVM and SystemVerilog for testbench development. Solid experience in RTL and gate-level simulation and debug . Hands-on experience in test planning, writing, and executing test cases . Good working knowledge of AHB/AXI bus protocols . Proficient in assertion-based verification and coverage development/closure . Working knowledge of C programming and scripting using Shell, Perl, or Python . Excellent communication, problem-solving, and team collaboration skills. Prior experience with IP-level DV and delivery is a must. Interested can share resume on Shubhanshi@incise.in

Participate in development of verification test plan, verification environment documentation, and test environment usage documentation. Evaluate and exercise various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics (functional coverage and code coverage). Collaborate with architects, designers, VIP team, and peers to accomplish all verification goals. Identify design problems, possible corrective actions, and/or inconsistencies on documented functionality. Adhere to quality standards and good test and verification practices. May work to coach junior engineers and help them in debugging complex problems. Key Qualifications: Proven desire to learn and explore new state-of-the-art technologies. Demonstrate good written and spoken English communication skills. Demonstrate good review and problem-solving skills. Knowledgeable with Verilog, VHDL, and/or SystemVerilog. Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus. Understanding of verification methodology such as UVM. Good organization and communication skills. 5+ years of relevant experience.

Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You'll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience in any of the protocols, UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol. Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. Proficiency in writing scripts using Perl, Python, and Shell scripting.

Applications Engineer position offers a wonderful opportunity to work on most challenging technical problems in verification domain and innovative technologies under Synopsys Verification Platform. Looking for an experienced and motivated professional who enjoys problem solving, open to continuous learning, passionate to work on cutting edge technologies and has excellent communication skills. It gives exposure to the breadth of HDL/HVL, methodologies, static and formal verification, dynamic simulation aspects including debug and experience in working in a diverse environment where interaction with domain experts across global locations will be involved. Key Requirements Experience: Bachelors degree in Electronics with 7+ Years or Master s degree in Electronics with 5+ Years Experience in verification technologies (Simulation, UVM, SVA, LRM understanding) Strong HDL language support (Verilog, VHDL, System Verilog) Simulation, UVM, Design Verification Digital design fundamental and RTL coding understanding Good Debugging skills. Scripting - Perl, TCL, Make, Shell Scripting. Role - VCS Simulation Technology Product Engineer Solid fundamentals in Digital design, HDLs (Verilog/VHDL) and System Verilog Exposure to Synopsys EDA tools (SpyGlass, VC SpyGlass, Verdi) would be added advantage Excellent written and oral communication skills is a must as the role requires interfacing global teams, proposing solutions Must have working knowledge on UNIX, TCL and/or any other scripting language to be effective Team player, partners with multiple stakeholders, has attention to detail and innovative mindset Motivated, doer and self-organized team worker with good social communication skills Open to travel, ability to multi-task, be detail-oriented Drive VCS/related technology customer deployment working closely with field and R&D Drive competitive engagements, requirements gathering for delivery strong product roadmap Work directly with R&D, Product Validation & Customers to suggest improvements in implementation and validation Use in-depth product understanding to provide technical expertise, diagnose, troubleshoot issues

* Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc ) * Generate verification test plan, verification environment documentation and test environment usage documentation * Define, develop, and verify complex UVM verification environments * Evaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) * Collaborate with architect, designers , VIP team to accomplish tasks. * Identify design problems, possible corrective actions and/or inconsistencies on documented functionality * Work with peers to improve methodologies and improve execution efficiency. * Adhere to quality standards and good test and verification practices. * Work as a lead, mentor junior engineers, and help them in debugging complex problems. * Able to Support Customer issues, by their reproduction and analysis. * Should be able multitask between different activities. Key Qualifications * Proven desire to learn and explore new state of the art technologies * Demonstrate good written and spoken English communication skills * Demonstrate good review and problem-solving skills * Knowledgeable with Verilog, VHDL and/or SystemVerilog * Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus * Understanding of verification methodology such as UVM . * Good organization and communication skills * Be a solution provider. * 8+ years of relevant experience

Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You'll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. You will be responsible for functional verification involving coherent and non-coherent IP designs. Proficiency in writing scripts using Perl, Python, and Shell scripting.

Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol

What You ll Be Doing: Understanding design specifications, defining verification scopes, developing test plans, tests, and verification infrastructure. Implementing and analyzing System Verilog assertions and coverage (code, toggle, functional). Collaborating with other verification team members to develop and execute verification test cases. Leading and mentoring junior engineers, helping them debug complex problems. Working with architects, designers, and pre- and post-silicon verification teams to accomplish tasks. Adhering to quality standards and best verification practices. Ramping up on new verification tools and methodologies using Synopsys products to enable customers. Developing innovative solutions to problems independently. Setting task-level goals and consistently meeting schedules. Collaborating with other Synopsys teams, including BU AEs and Sales, to develop and deploy tool and IP solutions. The Impact You Will Have: Ensuring the correctness and reliability of complex SoC designs. Enhancing the efficiency and effectiveness of verification processes. Mentoring and developing the skills of junior engineers. Contributing to the successful delivery of high-quality SoC products to market. Driving innovation in verification methodologies and tools. Strengthening Synopsys position as a leader in the semiconductor industry through your technical expertise. What You ll Need: B.E/B. Tech/M. E/M. Tech in electronics with 4-8 years of experience in the verification domain. Experience in IP level or SoC level verification. Proficiency in processor-based SoC level verification, including Verilog, System Verilog, and UVM. Hands-on experience with verification tools such as VCS and waveform analyzers. Experience with third-party VIP integration (e.g., Synopsys VIPs). Proficiency in UVM, C/C++, and System Verilog verification languages. Understanding of AXI-AMBA protocol variants. Experience with scripting languages (shell, Makefile, Perl). Strong understanding of design concepts and ASIC flow. Strong problem-solving, analytical, and debugging skills. Experience with ARM core verification and ARM-based technologies. Experience with USB, PCIe, and MIPI protocols. Excellent communication skills. Who You Are: An innovative thinker with a passion for technology and verification. A collaborative team player who excels in dynamic environments. An excellent communicator who can articulate complex ideas clearly. A problem solver with a keen eye for detail and quality. A mentor and leader committed to developing the skills of junior engineers. A lifelong learner dedicated to staying at the forefront of technological advancements.

What You ll Need: Looking for 2+yrs experience with BTech / MTech in VLSI / Electronics/Microelectronics Knowledge or hands-onexpertise/analysis of Analog and digital CMOS circuit designs Knowledge on electrical circuit networks and analysis Knowledge or hands-on Verilog/System Verilog languages and supported methodologies like VMM, UVM Must be able write/modify testcases, checkers, scoreboards in a system Verilog based test environment AMS verification experience in high speed Serdes designs supportingmulti-protocols is an advantage. Experience with the Synopsys Analog mixed-signal design tool set is an advantage. Modelling languages Verilog-a/ams can be an advantage Programming/scripting know-how e. g. tcl, perl, python Experience with Linux Good communication skills, ability to take ownership Self-organized to ensure that project timescales are met

Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Locally should be to be go-to person on all technical aspects of VIP At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683Aschheim, GermanyEngineering Principal Analog Design EngineerMississauga, CanadaEngineering Verdi InternshipHsinchu, TaiwanInterns/Temp

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are an experienced and motivated professional with a passion for solving challenging technical problems in the verification domain You are open to continuous learning and thrive on working with cutting-edge technologies You possess excellent communication skills and enjoy collaborating with domain experts across global locations You have a strong foundation in digital design, HDLs, and System Verilog, and you are proficient in using verification technologies Your attention to detail and innovative mindset make you a valuable team player who partners effectively with multiple stakeholders You are self-organized, motivated, and capable of multitasking in a dynamic environment, What Youll Be Doing: Working on challenging technical problems in the verification domain under the Synopsys Verification Platform, Engaging with HDL/HVL methodologies and dynamic simulation aspects, including debugging, Collaborating with global teams to propose and implement solutions, Utilizing your knowledge of UNIX, Tcl, and other scripting languages to enhance productivity, Participating in continuous learning and staying updated with the latest verification technologies, Contributing to a diverse environment and interacting with domain experts across various locations, The Impact You Will Have: Accelerating the design and verification of high-performance silicon chips, Enhancing the usability and adoption of Synopsys verification products and solutions, Optimizing chip designs for power, cost, and performance, thereby reducing project schedules, Driving technological innovation and contributing to the development of next-generation processes and models, Fostering collaboration and knowledge sharing within a global team, Supporting the creation of advanced technologies that power self-driving cars, AI, the cloud, 5G, and IoT, What Youll Need: Bachelors degree in Electronics with 3+ yearsexperience or a Masters degree in Electronics with 2+ yearsexperience, Proficiency in verification technologies such as Simulation, UVM, SVA, and LRM, Experience with Synopsys EDA tools (e-g, VCS, Verdi) is an advantage, Strong fundamentals in digital design, HDLs (Verilog/VHDL), and System Verilog, Excellent written and oral communication skills for effective global team interactions, Who You Are: A team player with a collaborative mindset and the ability to work with multiple stakeholders, A detail-oriented and innovative thinker who can propose effective solutions, Motivated, proactive, and self-organized with good social communication skills, Open to travel and capable of multitasking in a dynamic environment, The Team Youll Be A Part Of: You will be part of our Silicon Design & Verification business unit, which focuses on building high-performance silicon chips faster We are the leading provider of solutions for designing and verifying advanced silicon chips, and we develop next-generation processes and models to manufacture these chips Our team is dedicated to optimizing chips for power, cost, and performance, and we work collaboratively with global experts to drive innovation, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

The environment must support identifying verification environment requirements from various sources like specifications, design functionality, and interfaces. It needs to generate verification test plans, verification environment documentation, and test environment usage documentation. The environment should allow you to define, develop, and verify complex UVM verification environments. It must enable evaluating and exercising various aspects of the development flow , including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics (functional coverage and code coverage). The environment should facilitate collaboration with architects, designers, and VIP teams. It needs to help identify design problems, possible corrective actions, and inconsistencies in documented functionality. The environment should support improving methodologies and execution efficiency. It must adhere to quality standards and good test and verification practices. The environment should assist leads in mentoring junior engineers and debugging complex problems. It needs to support reproduction and analysis of customer issues. The environment's infrastructure should allow for multitasking between different activities. It requires knowledge of Verilog, VHDL, and/or SystemVerilog. Proficiency with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus. An understanding of UVM verification methodology is essential.

Expertise in UVM and System Verilog. Experience in verification IP modeling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol. Job Responsibilities: Able to contribute to the development of the VIP. Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology

Working on Functional Verification of High-Speed PHY IPs for DDRxx, LPDDRxx, PCIex, Display, and HDMI protocol standards. Studying IP/design blocks/Firmware Specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Developing DV/Firmware test benches, test plans, and test cases. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs). Performing simulation, random and focused stimulus generation, and coverage analysis. Collaborating closely with digital designers for debugging and achieving desired coverage. Developing architecture and micro-architecture knowledge of complex digital design blocks under test. The Impact You Will Have: Ensuring the high quality and reliability of our High-Speed PHY IPs. Contributing to the successful delivery of cutting-edge technology solutions. Enhancing the performance and functionality of our products through rigorous verification. Driving innovation and excellence in our verification processes. Supporting the rapid integration of capabilities into SoC designs. Enabling our customers to bring differentiated products to market quickly with reduced risk. What You'll Need: B. Tech/M. Tech in EC/CS with 3-6 years of relevant experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs. Understanding of functional verification flow with experience on industry-standard development and verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in System Verilog Assertions, code and functional coverage implementation, and review. Excellent debug and diagnostic skills. Experience with scripting and automation using TCL, PERL, or Python.

What You ll Need: MSEE or BSEE with 10+ years of digital design and verification experience. Strong understanding of verification methodologies like System Verilog and UVM. Familiarity with RTL coding and design principles. Proficiency in scripting languages like Perl and Python for automation. Excellent debugging and troubleshooting abilities. Experience with test chip and full chip knowledge is an advantage. Proven leadership and team-building skills.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a highly skilled and experienced SoC Verification Lead with a passion for pushing the boundaries of technology With a minimum of 12 years of experience in the SoC/IP/Subsystems verification domain, you possess deep technical expertise in various aspects of pre-silicon verification, including UVM, coverage analysis, verification plan creation, and debugging You have a strong understanding of design concepts and ASIC flows, and you are adept at leading teams to perform verification on complex SoC/IP/Subsystems Your knowledge of protocols such as PCIe, Ethernet, USB, and DDR, along with your hands-on experience with verification tools like VCS, waveform analyzers, and third-party VIP integration, makes you an invaluable asset Excellent communication skills and the ability to mentor and guide your team are key aspects of your profile You are proactive, able to anticipate and mitigate risks, and committed to adhering to high-quality standards, What Youll Be Doing: Working with Synopsys customers to understand their needs and define verification scope and activities, Understanding the complexity and requirements of verification and proposing resource requirements to complete the activities, Leading a team of engineers to perform various pre-silicon verification activities on IPs/Subsystems, Anticipating problems and risks and working towards a resolution and risk mitigation plan, Assisting and mentoring the team in day-to-day activities and growing the capabilities of the verification team for future assignments, Reviewing various results and reports to provide continuous feedback to the team and improve the quality of deliverables, Reporting status to management and providing suggestions to resolve any issues that may impact execution, Collaborating with architects, designers, and pre and post-silicon verification teams to accomplish your tasks, Adhering to quality standards and good test and verification practices, Ramping up on new Verification tools and methodologies using Synopsys Products to enable customers, Working with other Synopsys teams including BU AEs and Sales to develop, broaden, and deploy Tool and IP solutions, The Impact You Will Have: Driving the success of customer projects by ensuring robust and thorough verification of SoC designs, Enhancing Synopsys reputation as a leader in verification through high-quality deliverables and customer satisfaction, Mentoring and growing the verification team, building a strong foundation for future projects, Identifying and mitigating risks early, ensuring smooth project execution and delivery, Improving verification methodologies and practices, contributing to the overall efficiency and effectiveness of the team, Collaborating with cross-functional teams to achieve seamless integration and execution of verification activities, Providing valuable feedback and insights that drive continuous improvement in verification processes and tools, What Youll Need: E/B Technical expertise in various aspects of pre-silicon Verification (UVM, Coverage Analysis, Verification plan creation, debugging, etc), Good knowledge of various protocols (PCIe, Ethernet, USB, DDR, etc) and/or processor/interconnect/debug architecture, Hands-on experience with verification tools such as VCS, waveform analyzers, and third-party VIP integration (such as Synopsys VIPs), Ability to lead a team to perform verification on complex SoC/IP/Subsystems, Experience with planning and managing verification activities for SoC/Subsystems/IPs, Strong understanding of design concepts, ASIC flows, and stakeholders, Good communication skills, Who You Are: A proactive and detail-oriented leader who can guide and mentor a team, An excellent communicator who can collaborate effectively with cross-functional teams, A problem-solver who can anticipate challenges and develop effective mitigation strategies, A continuous learner who stays updated with the latest verification tools and methodologies, A team player who values quality and strives for excellence in deliverables, The Team Youll Be A Part Of: The System Solutions Group (SSG) at Synopsys delivers tool, methodology, architecture, design creation, design verification, and physical implementation expertise to enable leading-edge customers to complete their most challenging SoC design projects Our work spans from sub-blocks to full turnkey end-to-end SoCs Our customers range from start-ups to industry leaders, commercial companies, and government agencies Our customers develop SoCs for high-performance computing, automotive, aerospace & defense, and more, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a skilled Emulation R&D Engineer with over 8 years of experience and a strong academic background in Electronic & Communication or Computer Science Engineering Your expertise in C/C++, OOPS, and HDL languages like System Verilog and Verilog, along with your scripting skills in Perl or TCL, make you a valuable team member You possess knowledge of protocols such as ENET, HDMI, MIPI, AMBA, and UART, and have experience with UVM and Functional Verification You are a resourceful problem-solver, a team player, and have excellent communication skills, What Youll Be Doing: Designing and developing emulation models, Implementing and verifying digital designs using System Verilog and Verilog, Developing scripts in Perl, TCL, or other languages, Collaborating with cross-functional teams, Conducting protocol verification for various standards, Utilizing UVM for design validation, The Impact You Will Have: Enhancing emulation model efficiency, Contributing to high-performance silicon chips, Improving design reliability through verification, Streamlining workflows with automation, Ensuring protocol compliance, Driving technological advancements, What Youll Need: E / M Proficiency in C/C++ and OOPS, Knowledge of digital design and HDL languages, Experience with scripting languages, Familiarity with multiple protocols like ethernet, pcie, cxl, CSI, DSI, UFS AMBA, CHI and UVM, Who You Are: Effective communicator, Team player, Resourceful and detail-oriented, Innovative problem-solver, Adaptable learner, The Team Youll Be A Part Of: Join a dynamic team dedicated to developing and verifying advanced emulation models for high-performance silicon chips Collaborate with cross-functional teams to ensure seamless integration and adherence to industry standards, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits Your recruiter will provide more details about the salary range and benefits during the hiring process, Inclusion and Diversity: Synopsys considers all applicants for employment without regard to race, color, religion, sex, gender preference, national origin, age, disability, or status as a Covered Veteran in accordance with federal law,