868 Uvm Jobs - Page 25

As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6. Estimate the overall effort to develop the feature and close design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of work experience of one or more areas Power management Architecture/ microarchitecture/ Logic design – Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques. 1. Experience of working on Power Management designs handling Power/Performance States, Stop states of Core and Cache, Chip and System thermal management and power supply current over-limit management 2. Experience in working with research, architecture/ FW/ OS teams 3. Experience in low power logic design 4. Experience in working with verification, validation for design closure including test plan reviews, verification coverage 5. Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high- performance design and timing closure of high frequency designs 6. Experience in silicon bring-up

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Understand the design specification , Memory and Memory BIST engine connections Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in DFT Verification - Demonstrated execution experience of verification of Memory BIST Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Hardware debug skills backed by relevant experience on projects Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , etc Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic unit. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

The team is responsible for modelling the Power processor and systems which is used to evaluate the performance of new generation Power processor and systems and provide design guidance. The team is also responsible for performance verification and bring up of new Power processor and systems. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise As a Hardware Performance Modelling your responsibilities would be to work on multiple HW performance projects Develop test and validation plan for hardware bringup, pre-silicon performance verification and post-silicon performance validation Develop kernels and methodologies to correlate software model with hardware performance. Interact and collaborate with hardware, software and firmware development teams during system bringup and ensure the system meets its performance objectives Root causing of fails in simulation for performance changes/difference between Hardware and simulator Build automation frameworks, test cases and result analysis scripts. Design and develop model to simulate sub-systems like cache, interconnect and memory protocols Working with Architects/Research teams for optimizing architecture and system design, improving performance of next generation POWER processor and system. Demonstrate leadership in characterizing benchmarks, workloads and use cases (application code), and proposing system design optimisations to improve system level performance. Independently own system unit and successfully drive performance missions. responsibilities would include Excellent coding skills Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. Were united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology. Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. You will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks. #LI-Hybrid What we need to see: B. Tech. / M. Tech or equivalent experience 2+ years of relevant experience Experience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog Expertise in comprehensive verification of IP or interconnect protocols (e. g. PCI Express, USB, SATA) Experience in developing and working in functional coverage based constrained random verification environments Background in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug Ways to stand out from the crowd: Excellent knowledge of PCIE protocol - Gen3 and above Good understanding of the system level architecture of PCIE/CXL-based designs Perl, Python or similar scripting and SW programming language experience Good debugging and analytical skills Good interpersonal skills dream to work as a great teammate #LI-Hybrid

- Lead the architecture, design and development of an Interrupt Controller for a highly virtualized, multi-threaded, many-core and multi-socket SMP (symmetric multi-processor) . - Develop the features, present the proposed architecture in the High level design discussions to hardware and software teams - Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, firmware, software teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature - Estimate the silicon area required for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise - 10 to 15 years of relevant experience - At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC). - Expertise of SMP coherency - Experience in different on-chip interconnect topologies (e.g., mesh, crossbar) - Understanding of various snoop and data network protocols - Understanding of latency & bandwidth requirements and effective means of implementation - Working knowledge of queuing theory - numa/nuca architecture - Proficient in HDLs- VHDL / Verilog - Experience in High speed and Power efficient logic design - Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage - Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design - Experience in leading uarch, RTL design teams for feature enhancements. - Follow agile project leadership principles. Work with the team on estimation and execution plan. - Ability to quickly understand issues spanning multiple functional domains, switch context frequently and provide solutions to problems, is necessary. Preferred technical and professional experience Bachelors / Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance.

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Responsibilities: * Design, develop & verify complex SoCs using SV, UVM & LPDDR * Collaborate with cross-functional teams on RISC processor integration * Lead IP verification Interested professionals share your resume to mansoor@hisoltech.com

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Experience in assertions development/closure, constraint randomization, functional and code coverages, formal verification Experiences in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills We re doing work that matters. Help us solve what others can t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. 2+ years of domain experience Proficiency in functional verification using SV/UVM and strong debugging skills. Strong Digital Electronics and Programming fundamentals. Hands-on knowledge of C/C++/Scripting. Working experience on MIPI will be a strong plus. Prior VIP usage and development experience Self-motivated individuals with strong analytical and communication skills. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success. Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests. You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary: Job Title: Software Engineer II Work : Ahmedabad We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This position requires the technical expertise in protocol and formal verification methodologies. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other s success, and are passionate about technology and innovation. Job responsibilities: Responsible for the design and development of VIP using C/C++. Involve in managing multiple VIPs, leading a small team and interacting with customers. Experience and Technical Skills required: 2+ years of domain experience Proficiency in functional verification using SV/UVM and strong debugging skills. Strong Digital Electronics and Programming fundamentals. Hands-on knowledge of C/C++/Scripting. Working experience on MIPI will be a strong plus. Prior VIP usage and development experience Self-motivated individuals with strong analytical and communication skills. Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent Behavioral skills required. Must possess strong written, verbal and presentation skills. Ability to establish a close working relationship with both customer peers and management. Explore what s possible to get the job done, including creative use of unconventional solutions. Work effectively across functions and geographies Push to raise the bar while always operating with integrity. Regards kmadhup@cadence. com K Madhu Prasad We re doing work that matters. Help us solve what others can t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests JOB Requirements BE/BTECH/ME/METCH or Equivalent Degree EXP-5-8years Strong expertise in HVL(System Verilog, Specman e) with UVM/OVM/eRM methodology Experience. Experience in TB development including assertions development/closure, constraint randomization, functional and code coverages, testcase development, formal verification Experiences in test-bench development, Strong RTL and GLS (w/ or w/o SDF) simulation debug skills, Familiarization with IP or sub-system verification etc. 6-8yrs of industry experiences in DV w/ background in Ethernet/PCIe/Phy verification is preferred. We re doing work that matters. Help us solve what others can t.

Principal Accountabilities: Collaborate effectively with the US and UK based Design and Verification teams. Assist in integrating design verification processes to achieve first-pass silicon success, performance goals, and schedule compliance. Perform any additional tasks as assigned by the manager. Key Performance Measures: Learn quickly and demonstrate a strong willingness to continuously acquire new skills. Meet deadlines with high-quality deliverables. Actively share skills and knowledge with team members. Collaborate effectively with team members. Maintain a high level of professionalism in all tasks and interactions. Demonstrate elements of Spirit of Renesas in all aspects of work Embrace and embody the companys organizational culture and values. Qualifications 7+ years of experience in mixed-signal IC design and/or verification. Proficient in Verilog, SystemVerilog, VerilogAMS, and UVM. Ability to independently solve complex technical and non-technical issues as they arise. Strong understanding of analog circuits, digital design processes, and top-level integration. Solid knowledge of PMIC and DC-DC converters. Excellent simulation debugging skills, with the ability to analyze waveforms and identify issues in schematics, models, or RTL. Proficient in Unix environment and shell scripting, with a working knowledge of Python. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Senior Design Verification Engineer We are seeking talented Design Verification Engineers with proven expertise in industry-standard protocols such as PCIe and CXL. You will play a key role in the functional verification of designs, from developing block-level and system-level verification plans to writing test sequences, executing tests, and collecting and closing coverage. Responsibilities: Develop and execute block-level and system-level verification plans. Write and execute test sequences and collect and close coverage. Collaborate with RTL designers to debug failures and refine verification processes. Utilize coding and protocol expertise to contribute to functional verification. Develop user-controlled random constraints in transaction-based verification methodologies. Write assertions, cover properties, and analyze coverage data. Create VIP abstraction layers for sequences to simplify and scale verification deployments. Basic Qualifications: Minimum of 8 years experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications. Strong academic and technical background in Electrical Engineering or Computer Engineering (bachelor s degree required, master s preferred). Professional attitude with the ability to prioritize tasks, prepare for customer meetings, and work independently with minimal guidance. Knowledge of industry-standard simulators, revision control systems, and regression systems. Entrepreneurial, open-minded behavior and a can-do attitude, with a focus on customer satisfaction. Required Experience: Interpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments. Experience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above. Ability to independently develop test plans and sequences in UVM to generate stimuli. Experience writing assertions, cover properties, and analyzing coverage data. Developing VIP abstraction layers for sequences to simplify and scale verification deployments. Preferred Experience: Expertise in verifying Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols, including compliance on PCIe/CXL EP/RC. Experience with buffering and queuing with QoS on complex NOC-based SoCs. Analyzing performance at the system level on switching fabrics. Salary: Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

3+ years of experience in IP/SOC verification Strong expertise in DDR protocols Hands-on experience with verification methodologies (UVM, System Verilog.)

As a Hardware at , you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today s market. Your role and responsibilities As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6. Estimate the overall effort to develop the feature and close design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of work experience of one or more areas Power management Architecture/ microarchitecture/ Logic design - Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques. 1. Experience of working on Power Management designs handling Power/Performance States, Stop states of Core and Cache, Chip and System thermal management and power supply current over-limit management 2. Experience in working with research, architecture/ FW/ OS teams 3. Experience in low power logic design 4. Experience in working with verification, validation for design closure including test plan reviews, verification coverage 5. Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high- performance design and timing closure of high frequency designs 6. Experience in silicon bring-up ABOUT BUSINESS UNIT

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Product Engineer Location: Bangalore Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary: Drives development of products and technologies and has material responsibility for the success of that product/technology. VIP PE is expected to be an expert in Memory domain of Verification IP family- protocol and product-wise. PE main role is to help accelerate VIP portfolio adoption at Cadence s top tier customers by supporting pre-sales technical activities. To ensure that, one must have strong verification expertise and understand customer design and verification flows. As a Memory model VIP and protocol expert, PE drives product knowledge transfer across our field engineers and customer, providing training and developing collaterals. The PE will also need to translate high-level requirements from customers into a technical spec and drive the product definition that fits the customer needs. PE is expected to work independently and collaborate with other team members (RD, Marketing, support) to ensure all dimensions of the product are aligned. This role requires approximately 20% travel on average. Job responsibilities: (edit as per the requirement) Leads projects with high resource, risk and/or complexity Develops and leads large and multiple cross-functional and cross-organizational programs, initiatives, and activities with high resource requirements, risk and/or complexity Continually evaluates technology effectiveness/data interoperability of complex systems Manages issue resolution with vendors on tech/product quality and functionality and influences vendor roadmap and direction of products Communicates highly-complex ideas, anticipates potential objections and persuades others, often at senior levels, to adopt a different point of view. Experience and Technical Skills required (edit as per the requirement): At least 4+ to 8 years of experience with Verification and Design Working knowledge with Memory Models like DDR, HBM, LPDDR protocols is a must Experience with Developing Verification environments using System Verilog Working knowledge and experience with the UVM methodology Good experience on solving complex problems where analysis of situations or data requires an in-depth evaluation of various factors. Exercises judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results. Excellent problem-solving and debugging skills Qualifications BE/BTech/ME/MS/MTech in Electrical, Electronics Comm or Computer Science Engineering Behavioral skills required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We re doing work that matters. Help us solve what others can t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Principal Product Engineer Location: Bangalore Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary: Drives development of products and technologies and has material responsibility for the success of that product/technology. VIP PE is expected to be an expert in Memory domain of Verification IP family- protocol and product-wise. PE main role is to help accelerate VIP portfolio adoption at Cadence s top tier customers by supporting pre-sales technical activities. To ensure that, one must have strong verification expertise and understand customer design and verification flows. As a Memory model VIP and protocol expert, PE drives product knowledge transfer across our field engineers and customer, providing training and developing collaterals. The PE will also need to translate high-level requirements from customers into a technical spec and drive the product definition that fits the customer needs. PE is expected to work independently and collaborate with other team members (RD, Marketing, support) to ensure all dimensions of the product are aligned. This role requires approximately 20% travel on average. Job responsibilities: (edit as per the requirement) Leads projects with high resource, risk and/or complexity Develops and leads large and multiple cross-functional and cross-organizational programs, initiatives, and activities with high resource requirements, risk and/or complexity Continually evaluates technology effectiveness/data interoperability of complex systems Manages issue resolution with vendors on tech/product quality and functionality and influences vendor roadmap and direction of products Communicates highly-complex ideas, anticipates potential objections and persuades others, often at senior levels, to adopt a different point of view. Experience and Technical Skills required (edit as per the requirement): At least 7+ to 12 years of experience with Verification and Design Working knowledge with Memory Models like DDR, HBM, LPDDR protocols is a must Experience with Developing Verification environments using System Verilog Working knowledge and experience with the UVM methodology Good experience on solving complex problems where analysis of situations or data requires an in-depth evaluation of various factors. Exercises judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results. Excellent problem-solving and debugging skills Qualifications BE/BTech/ME/MS/MTech in Electrical, Electronics Comm or Computer Science Engineering Behavioral skills required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We re doing work that matters. Help us solve what others can t.

Role: AMS Verification Engineer / Sr. Engineer Experience required: 5-15 years Work location: Pune, Bangalore, Hyderabad, Chennai, and Noida Minimum 5 Years of overall experience in ASIC Verification Should have worked on AMS Verification for a minimum of 2 years Develop and execute verification plans for AMS designs. Create test benches and run simulations using tools such as Cadence Virtuoso, Spectre, or AMS Designer. Verify mixed-signal blocks (e.g., ADCs, DACs, PLLs) and ensure proper analog-digital interaction. Debug and resolve design issues in collaboration with design teams. Document verification results and ensure compliance with design specifications. Interested candidates can send in their profile to bindu@logicalhiring.com or careers@logicalhiring.com References are welcome! For other open roles, please visit - www.logicalhiring.com

Role: ASIC Verification Engineer Experience Required: 5-15 Years Work location: Bangalore, Hyderabad, Chennai, Ahmedabad, and Pune Minimum 5 years of experience in System Verilog HVL. Minimum 5 years of experience in OVM/UVM/VMM/Test Harness. Hands-on experience in developing assertions, checkers, coverage, and scenario creation. Must have executed at least 2 to 3 SoC Verification projects Experience in developing test and coverage plan, verification environment and validation plan. Knowledge of at least one industry standard protocol like Ethernet, PCIe, MIPI, USB, or similar is required. Review and Audit participation. At least 1 year of experience in handling a team for the senior roles Define/derive the Scope, Estimation, Schedule, and Deliverables of the proposed work. Interested candidates can send in their profile to bindu@logicalhiring.com or careers@logicalhiring.com References are welcome! For other open roles, please visit - www.logicalhiring.com

Mirafra is hiring!!! Hardware (HW) Verification Engineer Location: Hyderabad Experience: 5 to 10 Years Job Description: Mirafra Technologies is hiring experienced Hardware Verification Engineers to work on top-tier SoC verification projects. The ideal candidate will have strong UVM/SystemVerilog expertise and hands-on experience with FPGA and protocol-level testing. Responsibilities: Develop SV/UVM testbenches at Top/Sub-system/Block-levels Drive creation and execution of test plans and test specs Document verification phases: user guides, test reports, and execution logs Contribute to verification architecture and methodology development Required Skills: Strong programming skills in SystemVerilog and UVM Protocol verification experience: Ethernet, PCIe, SPI, I2C, USB Hands-on hardware testing experience using logic analyzers, traffic generators Exposure to FPGA verification and Xilinx tools Solid debugging skills at both device and board level Proficiency in scripting languages: Perl, Python, TCL Strong interpersonal, communication, and analytical skills Apply Now or send your resume to swarnamanjari@mirafra.com Note: This is a client-based selection process .

Design Verification Engineer (4-7 years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement

Lead /Senior Design Verification Engineer-GLS/UVM |Hyderabad, India | Experience:7-12 Years Role Overview: We are looking for an experienced and detail-oriented Design Verification Engineer with strong expertise in Gate-Level Simulation (GLS) and SystemVerilog/UVM methodology . The role involves validating complex SoC/IP designs in post-synthesis environments, working closely with design, DFT, and physical implementation teams. Experience with HBM (High Bandwidth Memory) is a strong advantage. Key Responsibilities: Develop and maintain UVM-based verification environments for complex digital IP and SoCs. Plan and execute GLS (Gate-Level Simulation) flows including SDF annotation, X-checking, and timing-aware validation. Perform debug of timing-related and X-propagation issues at netlist level. Drive regression automation, simulation coverage analysis, and documentation of results. Work closely with cross-functional teams (DFT, synthesis, STA, PD) to resolve post-synthesis and post-layout issues. (Optional) Support validation of HBM interfaces , including protocol-level behavior and error scenarios. Required Skills: 7-12 years of design verification experience in ASIC or SoC environments. Solid expertise in SystemVerilog, UVM , and assertion-based verification. Strong hands-on experience in GLS including: SDF annotation Debugging setup/hold, X issues Power-aware simulations (optional) Familiarity with simulation tools : VCS, Xcelium, Questa, Debussy/Verdi. Experience with scripting (Perl, Python, Shell) for automation. Good understanding of chip lifecycle from RTL to GDSII. Nice to Have: Experience working with HBM protocols or memory controller verification. Exposure to low-power verification , UPF flows. Familiarity with post-silicon bring-up and debug is a plus. Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com

Position #1: Lead/Senior Design Verification Engineer - CPU / RISC-V Location : Bangalore Experience : 612 Years Domain : Semiconductors | SoC | RISC-V | CPU Subsystems Role Overview: We are seeking an experienced Design Verification (DV) Engineer to join our core CPU verification team focused on RISC-V based processors and subsystems . This is a hands-on role requiring strong technical knowledge in processor architecture , microarchitecture verification , and end-to-end validation of complex SoCs. Key Responsibilities: Develop and execute test plans and environments for CPU and RISC-V based subsystems. Build UVM-based verification environments for simulation and regression. Create testbenches, assertions, checkers, and functional coverage models. Debug failures using waveform viewers, logs, and deep architectural understanding. Collaborate with architects, designers, and firmware teams across all verification phases. Required Skills: 612 years of hands-on DV experience, primarily on CPU cores or RISC-V . Strong understanding of RISC-V or ARM microarchitectures . Proficient in SystemVerilog, UVM , and scripting (Python/Perl/Tcl). Experience with cache coherency, MMUs, branch prediction, or pipeline logic is a plus. Exposure to verification tools like VCS, Questa, or Xcelium . Position #2: Lead/Senior Design Verification Engineer - High-Speed PCIe Location : Bangalore Experience : 612 Years Domain : Semiconductors | SoC | High-Speed Interfaces | PCIe Gen4/Gen5 Role Overview: We are looking for a skilled Design Verification Engineer with expertise in high-speed interface protocols , particularly PCI Express (PCIe) . The role will focus on validating complex SerDes-based subsystems and ensuring full compliance and performance coverage. Key Responsibilities: Define and implement UVM-based testbenches for PCIe-based subsystems. Verify protocol-level compliance (PCIe Gen4/Gen5/Gen6). Generate, run, and debug simulations across various protocol scenarios and stress conditions. Ensure full coverage functional, code, and assertion-based . Collaborate with silicon validation and firmware teams for end-to-end test alignment. Required Skills: 612 years of DV experience with PCIe (mandatory) and high-speed interface protocols. Strong command of UVM, SystemVerilog , and assertion-based verification. Deep understanding of PCIe layers , packet formats, credit flow, and link training. Experience with VIPs (Synopsys/Cadence/Mentor) and waveform debugging tools. Knowledge of AXI/AMBA , DDR, or USB is a strong plus. Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com

Job Title: Design Verification Engineer Location: Hyderabad Experience: 3 to 8 Years Job Description: Mirafra Technologies is looking for experienced Design Verification Engineers to join our team in Hyderabad . This role involves a mix of IP-level ownership, feature enhancement, and debug responsibilities. Key Responsibilities: Own design verification at the IP level Plan and execute feature additions and mode re-enablement for specific design variants Perform bug fixes and analyze regression signatures Minimum Qualifications: Proficient in SystemVerilog, UVM, UVM_REG , and advanced debugging techniques Experience reading specifications and developing comprehensive test plans Expertise in building monitors, scoreboards, sequencers, and sequences Skilled in using scripts and verification methodologies to enhance bug detection Strong understanding of functional verification , including test planning, testbench development, stimulus generation, checking, and functional coverage Comfortable with build checks , working with large testbenches , coverage analysis , and adding/enabling debug mechanisms Proactive approach to analyzing failures and identifying root causes Apply Now or send your resume to swarnamanjari@mirafra.com

Key Responsibilities Lead and manage all engineering functions across front-end and back-end VLSI design and verification. Define and execute engineering strategy aligned with company objectives and customer requirements. Drive excellence in RTL design, functional verification, DFT, physical design, STA, and sign-off processes. Build and mentor high-performing teams; attract, retain, and develop top VLSI engineering talent. Ensure timely delivery of high-quality project outcomes across multiple client engagements. Establish and enforce best practices, methodologies, and quality standards. Collaborate with business development and sales teams to support proposals and client interactions. Evaluate and introduce tools, technologies, and methodologies to enhance engineering productivity. Manage engineering budgets, resource planning, and project allocation. Foster a culture of innovation, ownership, and continuous improvement. Qualifications B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related field. 15+ years of hands-on experience in VLSI design and verification, including at least 5 years in senior leadership roles. Proven track record of managing large engineering teams and delivering complex SoC or ASIC projects. Deep expertise in design (RTL, synthesis) and verification (UVM, SystemVerilog, functional coverage). Familiarity with industry-standard EDA tools (Synopsys, Cadence, Mentor, etc.). Strong leadership, communication, and organizational skills. Experience working with global clients or in multinational environments is a plus.