Posted:3 weeks ago|
Platform:
On-site
Full Time
Participate in development of verification test plan, verification environment documentation, and test environment usage documentation. Evaluate and exercise various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics (functional coverage and code coverage). Collaborate with architects, designers, VIP team, and peers to accomplish all verification goals. Identify design problems, possible corrective actions, and/or inconsistencies on documented functionality. Adhere to quality standards and good test and verification practices. May work to coach junior engineers and help them in debugging complex problems. Key Qualifications: Proven desire to learn and explore new state-of-the-art technologies. Demonstrate good written and spoken English communication skills. Demonstrate good review and problem-solving skills. Knowledgeable with Verilog, VHDL, and/or SystemVerilog. Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus. Understanding of verification methodology such as UVM. Good organization and communication skills. 5+ years of relevant experience.
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