Senior Design Verification Engineer

Job Description

Position #1: Lead/Senior Design Verification Engineer - CPU / RISC-V Location : Bangalore Experience : 612 Years Domain : Semiconductors | SoC | RISC-V | CPU Subsystems Role Overview: We are seeking an experienced Design Verification (DV) Engineer to join our core CPU verification team focused on RISC-V based processors and subsystems . This is a hands-on role requiring strong technical knowledge in processor architecture , microarchitecture verification , and end-to-end validation of complex SoCs. Key Responsibilities: Develop and execute test plans and environments for CPU and RISC-V based subsystems. Build UVM-based verification environments for simulation and regression. Create testbenches, assertions, checkers, and functional coverage models. Debug failures using waveform viewers, logs, and deep architectural understanding. Collaborate with architects, designers, and firmware teams across all verification phases. Required Skills: 612 years of hands-on DV experience, primarily on CPU cores or RISC-V . Strong understanding of RISC-V or ARM microarchitectures . Proficient in SystemVerilog, UVM , and scripting (Python/Perl/Tcl). Experience with cache coherency, MMUs, branch prediction, or pipeline logic is a plus. Exposure to verification tools like VCS, Questa, or Xcelium . Position #2: Lead/Senior Design Verification Engineer - High-Speed PCIe Location : Bangalore Experience : 612 Years Domain : Semiconductors | SoC | High-Speed Interfaces | PCIe Gen4/Gen5 Role Overview: We are looking for a skilled Design Verification Engineer with expertise in high-speed interface protocols , particularly PCI Express (PCIe) . The role will focus on validating complex SerDes-based subsystems and ensuring full compliance and performance coverage. Key Responsibilities: Define and implement UVM-based testbenches for PCIe-based subsystems. Verify protocol-level compliance (PCIe Gen4/Gen5/Gen6). Generate, run, and debug simulations across various protocol scenarios and stress conditions. Ensure full coverage functional, code, and assertion-based . Collaborate with silicon validation and firmware teams for end-to-end test alignment. Required Skills: 612 years of DV experience with PCIe (mandatory) and high-speed interface protocols. Strong command of UVM, SystemVerilog , and assertion-based verification. Deep understanding of PCIe layers , packet formats, credit flow, and link training. Experience with VIPs (Synopsys/Cadence/Mentor) and waveform debugging tools. Knowledge of AXI/AMBA , DDR, or USB is a strong plus. Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com