Staff MSDV Engineer

Job Description

We're looking for a highly experienced and self-motivated Lead Analog/Mixed-Signal Verification Engineer to join our team. In this pivotal role, you'll be responsible for the comprehensive verification of complex mixed-signal designs, from block to full-chip levels. You'll drive verification methodologies, mentor junior engineers, and play a crucial part in ensuring the quality of our cutting-edge products. Responsibilities: Lead the verification of complex mixed-signal designs and sub-systems , ensuring robust functionality and performance. Develop and utilize Analog Behavioral Models (SystemVerilog, Verilog-AMS, wreal, UDNs, EEnet) for efficient verification. Validate real number models against SPICE models , ensuring accuracy and correlation. Gain hands-on experience with SPICE simulations using industry-standard simulators such as SPECTRE. Define comprehensive test plans, tests, and verification methodologies for both block and chip-level verification of Mixed-Signal Designs. Continuously interact with the analog co-simulation team to enable seamless top-level chip verification. Contribute to and influence decisions on verification methodologies to be adopted across projects. Technically mentor and guide junior verification engineers on SoC Verification best practices. Support post-silicon verification activities of products, working closely with design, product evaluation, and applications engineering teams. Required Qualifications: B.Tech/M.Tech with 8-12 years of industry experience in analog/mixed-signal verification. Demonstrated experience in verification plan development, verification environment creation, and verification/debug of complex mixed-signal products at block and chip-top levels. Proven experience in co-simulations with analog model/transistor level and digital RTL/Gate+SDFs , as well as circuit simulations with Spice/Fast Spice simulators. Proven experience in leading full-chip level design verification of mixed-signal devices. Must have experience in modeling and validation of analog blocks (RNM, Verilog-AMS, etc.). Familiarity with latest digital verification methodologies , including Digital Mixed-Signal (DMS) verification using UVM. Strong communication skills and the ability to collaborate effectively with a global team. Self-motivated and enthusiastic. Excellent debugging and analytical skills. Additional Qualifications & Experience: Proficiency with Verification Planning tools (e.g., ePlanner, vManager). Experience with SystemVerilog Assertions (SVA) . Skilled in scripting languages (Shell, TCL, Perl, Python) for testbench automation. Hands-on UVM experience at the user level, including pseudo and constrained random techniques, and assertion-based verification with SystemVerilog. Experience in building and leading small verification teams . Strong interpersonal, teamwork, and communication skills are essential.