83 Mixed Signal Jobs

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs ( PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support. Responsibilities Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation. Minimum Qualifications Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field. 12+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications Experience with Low power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc., Experience in scripting languages (Python, or Perl). Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors.

Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). Qualcomm is a company of inventors seeking to revolutionize the CPU market in an age of new possibilities. Are you interested in joining Qualcomm’s high performance CPU team as an SRAM Mask Layout DesignerYou will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. As a Mask Layout Designer, you will develop block or macro level layouts and floorplans for high performance custom memories according to project requirements, specifications, and design schematics. Minimum qualifications 5+ years of experience and a high school diploma or equivalent OR 5+ years experience and BS in Electrical Engineering OR 3+ years experience and MS in Electrical Engineering Direct experience with custom SRAM layout Experience in industry standard custom design tools and flows. Knowledge of leading-edge FinFET and/or nanosheet processes (5nm or newer). Experience in Layout design of library cells, datapaths, memories in deep sub-micron technologies. Knowledge of all aspects of Layout floorplanning and hierarchical assembly. Knowledge of Cadence Virtuoso and Calibre LVS/DRC. Preferred qualifications Good understanding of device parasitics and reliability considerations during layout. Good understanding of critical circuits and layout styles. Ability to write Skill code for layout automation. Knowledge of improving EMIR in layout. Good communication skills to work with different teams to accurately describe issues and follow them through for completion. Roles and Responsibilities Design layout for custom memories and other digital circuits based on provided schematics. Read and interpret design rule manuals to create optimal and correct layout. Own the entire layout process from initial floorplanning to memory construction to physical verification. Use industry standard verification tools to validate LVS, DRC, ERC etc. Interpret the results from the verification suite and perform layout fixes as needed. Provide layout fixes as directed by the circuit design engineers. Work independently and execute memory layout with little supervision. Provide realistic schedules for layout completion. Provide insight into strategic decisions regarding memory layout and

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas: Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: AMS Verification Location : Bangalore Work Type: Onsite Job Type: Full time Job Description: Lead the verification of analog and mixed-signal IPs such as bandgaps, LDOs, multi-phase buck regulators, comparators, and functional safety (FuSa) monitoring circuits. Own and execute comprehensive verification plans for assigned blocks or features, ensuring complete coverage and robust test quality. Develop or enhance analog behavioral models using System Verilog Real Number Modelling (SV-RNM). Validate digital functionalities including CRC checks, clock monitors, register maps, OTPs, and communication interfaces. Apply strong SystemVerilog skills, including the use of assertions and cover groups. Utilize advanced debugging techniques across RTL and schematic views at the top level. Manage and maintain VSIF files to support verification regression workflows. Conduct coverage analysis using tools such as IMC or vManager. Write or maintain automation scripts (Make files preferred) to streamline verification processe TekWissen Group is an equal opportunity employer supporting workforce diversity.

Bring substantial experience in effective team management to help mentor, coach and grow the Physical Design and Implementation team with an emphasis on positive influence on team morale and culture Will be responsible for delivering silicon for a wide range of applications Primarily a management position, however, the candidate is required to have significant RTL to GDSII knowledge to probe into technical details Candidate will be required to collaborate and foster good relationship with all parts of engineering: Architecture team, Front End Design teams and Program management Qualifications Minimum 15 years of ASIC physical design experience Minimum 5 years of management experience with leading a physical design and implementation teams from RTL-to-GDSII Should have excellent collaboration and teamwork capabilities across various chip development disciplines. Will be responsible to hire talent and mentor, build expertise, and grow each team member Ability to define and drive flows and methodologies to optimize physical design work, define guidelines and checklists, drive execution, and track progress Ability to resolve design and flow issues related to physical design through the identification of potential solutions and drive resolution Experience in working with the front-end teams to understand chip architecture and drive physical aspects early in the definition cycle Experience working relationships with EDA Vendors Multiple successful tape out Excellent communication (oral and written) skills Ability to present to and interface with internal customers Ability to handle a dynamic environment and to coordinate team action Bachelor s Degree in Electrical Engineering or closely related discipline is required Masters Degree in Electrical Engineering or closely related discipline is preferred Company Overview MaxLinear is a global, NASDAQ-traded company (MXL) where the entrepreneurial spirit is alive and well. We are a fabless system-on-chip product company, striving to improve the world s communication networks for everyone through our highly integrated radio-frequency (RF), analog, digital, and mixed-signal semiconductor solutions for access and connectivity, wired and wireless infrastructure, and industrial and multi-market applications. We hire the best people in the industry and engage them in some of the most exciting opportunities that connect the world we live in today. Our growth has come from innovative, bold approaches to solving some of the world s most challenging communication technology problems in the most efficient and effective manner. MaxLinear began by developing the world s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn t achieve the extremely high-performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we ve developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments. Over the years, we ve expanded through organic growth and through several acquisitions that have perfectly complemented our existing portfolio and enabled us to deliver complete end-to-end solutions in our target markets. One such example was the acquisition of Intel s Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers needs. Our headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Waltham, Massachusetts; Vancouver, Canada; Valencia, Spain; Bangalore and Chennai, India; Villach, Austria; Munich, Germany; Israel; and Singapore. We have approximately 1,500 employees, a substantial majority of whom have engineering degrees and include masters and Ph.D. graduates from many of the premiere universities around the world. Our employees thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building the best and most innovative products on the market.

We are seeking a Principal Analog Design Engineer to lead the architecture, design, and development of Power Management ICs (PMICs). This is a high-impact technical leadership role, focused on designing complex, high-performance analog and mixed-signal circuits with emphasis on quality, reliability, and innovation. Key Responsibilities Define architecture and lead transistor-level design of analog and mixed-signal blocks for PMICs, including: LDOs, DC-DC converters (Buck/Boost), Voltage supervisors, Power sequencing, Load switches, Bandgap references, Oscillators, and Bias circuits Drive system-level specification and partitioning in collaboration with Systems and Application teams Perform pre- and post-layout simulations and analysis across PVT corners using industry-standard EDA tools Work closely with layout engineers to optimize performance, area, and noise/EMI sensitivity Collaborate with cross-functional teams across design, verification, test, validation, and reliability Ensure designs meet functional safety, reliability, and regulatory compliance standards Support silicon bring-up, characterization, and debug Mentor junior designers and lead design reviews Promote IP reuse, documentation best practices, and patent/IP generation initiatives Qualifications Bachelor s, Master s, or PhD in Electrical Engineering or related field 15+ years of hands-on experience in analog/mixed-signal IC design, with a focus on PMICs Deep expertise in analog circuit design, power management, and system-level integration Familiarity with ISO 26262, AEC-Q100, and other quality/reliability standards Strong experience with Cadence tools and analog simulation methodologies Demonstrated leadership in delivering complex designs from concept to production Excellent problem-solving, communication, and collaboration skills Experience with high-voltage BCD processes (e.g., 40V/60V) Proven track record of successful silicon tape-outs and production ramp Knowledge of industry design standards and practices for reliability and safety Understanding of layout impact on analog performance and EMC/EMI mitigation We recognize and appreciate the value and contributions of individuals with diverse backgrounds and experiences and welcome all qualified individuals to apply. Equal Opportunity Employer: Disability/Veteran Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership qualities in planning, area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environment. Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items. Contribute to effective project-management. Effectively communicating with Global engineering teams to assure the success of layout project. Qualification/Requirements 6 to 9 years experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET ) Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc, Good understanding of Analog Layout fundamentals (e.cg., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive static device parasitics etc) Understanding layout effects on the circuit such as speed, capacitance, power and area etc Ability to understand design constraints and implement high-quality layouts Ability to understand design hierarchy and different architectures for Memory designs. Excellent problem-solving skills in physical verification of custom layout. Multiple Tape out support experience will be an added advantage. Excellent verbal and written communication skills.

Physical verification engineer for SOC/blocks Key Responsibilities Physical verification for SOCs, cores, and blocks, including DRC, LVS, ERC, ESD, DFM, and tapeout processes. Address critical design and execution challenges associated with physical verification and sign-off. Have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Partner with PNR engineers to achieve sign-off at various stages of the design process. Qualifications Proficient in physical verification for SoC/full-chip and block-level processes, including DRC, LVS, ERC/PERC, DFM, OPC, and tape out. Experience: 7-15Y Comprehensive experience and understanding of all stages of the IC design process from RTL to GDS2. Skilled in troubleshooting LVS issues at the chip level, particularly with complex analog-mixed signal IPs. Familiar with low-power design techniques, including level shifters, isolation cells, power domains/islands, and substrate isolation. Experienced in physical verification of I/O rings, corner cells, seal rings, RDL routing, bumps, and other full-chip components. Capable of developing sign-off methodologies/flows and providing support to larger teams. Knowledge of ERC rules, PERC rules, and ESD rules is a valuable asset. Experience in floor planning is a plus Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies, with a particular focus on achieving high-efficiency power conversion for applications using GaN devices. Job Description Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies , with a particular focus on achieving high-efficiency powerconversion for applications using GaN devices. D esign and verify pre-silicon analog/mixed-signal integrated circuitblocks , including incorporating features for testing and quality assurance, and providing support for top-level integration. Assist in defining the requirements for analog and mixed-signalblocks , aligning them with IP Module architecture, and ensuring compliance with requirements through documentation. Estimate effort and planning design work packages to meet project milestones. Provide essential support to physical design engineers, post-silicon verification, production testing , and other critical activities extending beyond the design phase. You are best equipped for this task if you have: A masters degree in electrical/Electronic Engineering, Physics or equivalent field of studies. Experience in analog and mixed-signal circuit design, particularly in CMOS and Smart Power Technologies. Good Analytical skills and very good understanding of Analog Design. Familiarity with high-efficiency power conversion, such as DC-DC converters, is highly desirable. Experience in pre-silicon verification and with System Verilog would be a plus. Proficiency in computer-aided design tools and methodologies. Excellent problem-solving and communication skills. Ability to work effectively in a collaborative team environment. Detail-oriented with a commitment to quality and precision. Fluency in English

Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies, with a particular focus on achieving high-efficiency power conversion for applications using GaN devices. Job Description In your new role you will: Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies , with a particular focus on achieving high-efficiency power conversion for applications using GaN devices. Design and verify pre-silicon analog/mixed-signal integrated circuit blocks , including incorporating features for testing and quality assurance, and providing support for top-level integration. Assist in defining the requirements for analog andmixed-signal blocks , aligning them with IP Module architecture, and ensuring compliance with requirements through documentation. Estimate effort and planning design work packages to meet project milestones. Provide essential support to physical design engineers,post-silicon verification, production testing , and other critical activities extending beyond the design phase; Your Profile You are best equipped for this task if you have: A masters Degree in Electrical/Electronic Engineering, Physics or equivalent field of studies. Experience in analog and mixed-signal circuit design, particularly in CMOS and Smart Power Technologies. Good Analytical skills and very good understanding of Analog Design. Familiarity with high-efficiency power conversion, such as DC DCconverters, is highly desirable. Experience in pre-silicon verification and with System Verilog wouldbea plus. Proficiency in computer-aided design tools and methodologies. Excellent problem-solving and communication skills. Ability to work effectively in a collaborative team environment. Detail-oriented with a commitment to quality and precision. Fluency in English

Job Title: Analog Design Engineer / Lead Location: Location: Bengaluru/Bhubaneswar/Ranchi Experience: 5 - 10 Years Technical Requirements: Analog Circuit Design: Strong expertise in designing and simulating analog circuits such as amplifiers, ADCs/DACs, voltage regulators, PLLs, and other mixed-signal Tools & Methodologies: Proficient in using EDA tools for schematic capture, circuit simulation (e.g., SPICE), layout, and post-layout verification. Layout Techniques: Deep understanding of analog layout techniques, including matching, noise reduction, and parasitic minimization. Design for Performance: Experience in optimizing designs for low power, high speed, and area efficiency. Process Knowledge: Familiarity with CMOS process technology, including the impact of process variations on analog performance. Verification & Validation: Skilled in analog/mixed-signal verification methodologies, including behavioral modeling and corner case analysis. Tape-Out Experience: Experience with silicon validation and characterization, including working through tape-out processes. Expectations from the Role: Problem-Solving: Strong analytical and problem-solving skills, with the ability to troubleshoot complex circuit issues. Collaboration: Effective communication and teamwork skills, with the ability to collaborate with digital and layout teams. Attention to Detail: High attention to detail to ensure design accuracy and Innovation: Ability to innovate and optimize designs within the constraints of the Project Management: Ability to manage multiple tasks and projects, ensuring timely

Job Description: Job Title: Electronics Engineer Medical Devices Location: IIT Kanpur, UP / Delhi NCR Company Name: Lenek Technologies Pvt Ltd Company Website: https://www.lenektech.com/#/ LinkedIn Website: http://www.lenektech.com/ Experience: 2+ years preferred (Exceptional freshers may also apply) Job Role: Design of Mixed Signal PCB ranging from 2 to 20 layers Circuit simulations using Matlab or LTSpice PCB simulations for thermal management, signal integrity and power integrity Circuit design and component selection Firmware programming Board level testing, system integration and product level testing Portfolio we are looking for: Bachelor's or master’s degree in Electronics, Electrical, or related disciplines Experience in PCB design and circuit simulation tools (LTSpice, PSpice, etc.) Strong foundation in embedded systems and firmware development (C/C++) Familiarity with analogue signal processing, data converters (ADC/DAC), op-amps Understanding of EMI/EMC, grounding, and safety in medical electronics (preferred) Excellent debugging and documentation skills Experience in design, development, and deployment of analogue and digital hardware electronics systems working with engineers, technicians, vendors and management stakeholders. Hands-on experience and working knowledge of ECAD packages like KiCAD/Altium Designer/PADS/OrCAD/ Hyper Lynx/ Cadence/Eagle, etc. and simulation tools like Matlab/ LTSpice/Ansys, etc. Knowledge and understanding of laboratory instruments like Oscilloscope, Spectrum Analyzer, Function Generator, etc Active participation in electronics technical communities.

Participate in the development and testing of Field-Programmable Gate Arrays (FPGAs) for various projects. In your new role you will: Experience with FPGA design and development Proficiency in Vivado and other design software Providing Simulation of digital designs and design FPGA board Design emulation circuits for analog parts with discrete device Experience with lab equipment and testing procedures Validating on lab testing of FPGA Strong understanding of digital and analog circuit design Strong analytical and problem-solving skills You are best equipped for this task if you have: Master s or Bachelor s Degree in Electrical/Electronic Engineering, Physics or equivalent field of studies. Experience in FPGA design, preferred with Xilinx/Vivado. Experience in digital and mixed-signal design, particularly with System Verilog. Good Analytical skills and good understanding of digital and mixed signal designs. Familiarity with power conversion topologies, such as DC/DC and AC/DC converters, is highly desirable. Experience in pre-silicon verification would be a plus. Proficiency in computer-aided design tools and methodologies. Excellent problem-solving and communication skills. Ability to work effectively in a collaborative team environment. Contact: Garima Chauhan - garima,chauhan@infineon.com We are on a journey to create the best Infineon for everyone.

: 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is necessary. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc. Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience and collaborating with cross functional teams will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Multiple foundries experience is an added plus. Minimum Educational Qualification : Educational Bachelor's, Electrical or Electronics Engineering or equivalent Role And Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, EM, quality check and documentation. Responsible for on-time delivery of block-level/top-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work Should have good experience in working with cross-functional team. Ensure standard processes and procedures are followed to resolve all client queries. Handle technical escalations through effective diagnosis and troubleshooting of client queries Manage and resolve technical roadblocks/ escalations to timely deliverable with high quality. Troubleshoot all client queries in a user-friendly, courteous, and professional manner. Offer alternative solutions to clients (where appropriate) with the objective of retaining customers' and clients' business. Build people capability to ensure operational excellence and maintain superior customer service levels of the existing account/client. Contribute to effective project-management. Effectively communicating with engineering teams in different Geographical locations to assure the success of the layout project. Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders.

MS or Ph D with a major in EE or Physics related field Solid background in analog CMOS circuit design Proficient with Cadence design environment and mixed-signal simulation Able to assume responsibility for a variety of technical tasks and to work independently (recommended) Digital communication system, digital signal processing, digital system design, RF system, MATLAB Architecture study and evaluation of advanced SerDes topologies SerDes design and verification of different high speed analog and mixed signal blocks including, but not limited to: drivers, front end circuits, samplers, comparators, ADCs, DACs, PLLs, clock distribution, etc Evaluate, measure, and debug silicon until it reaches high volume production Work with cross functional teams to optimize the designs

About Analog Devices . Job Description As part of the Engineering Enablement organization based in Bangalore, this senior mixed signal design engineer develops and maintains CAD tools/methods used in Analog, RF, and Mixed-Signal product development across all of ADI. As a Senior Mixed Signal Design Engineer, you will also be expected to possess necessary programming skills and circuit design knowledge to allow you to develop, QA, support, and enhance EDA tools/methods used by IC product development teams. Requirements: Masters or Bachelors in Electrical/Electronics Engineers with 3+ years of experience Experienced in design and/or layout of Analog and mixed signal circuits Experienced in circuit simulation with Cadence ADE/Spectre, ideally with experience of RF simulations and debugging simulation issues Proficient at programming, like Cadence SKILL/Perl/Python/Shell etc. Formal training in software development is preferred. Good to have PDK or physical verification rules development experience. Strong interpersonal and communication skills are critical for working, influencing and collaborating with product development groups in India and worldwide. Proficiency in English language

Bachelor or master Degree with 3-10 years of Analog Layout experience. Good understanding of advanced semiconductor technology process and device physics. Full-custom circuit layout/verification and RC extraction experience. Experience in one or more of the following areas is preferable: Mixed signal/analog/high speed layout, e. g. PLL, IO, RF, PMIC, OSC, DC-DC convertor, Temperature sensor, SRAM, TCAM, ROM, MRAM, ESD Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC, LVS, DFM, etc). Experiences in advanced technology node under 16nm/14nm/7nm. 5nm/3nm will be an added advantage. Must have expertise on Totem EMIR Self-heating effects, Star RC extraction, and Calibre PV checks (DRC, LVS, Antenna, ERC, PERC etc. ). Good Understanding of layout fundamentals (Matching, EM, ESD, Latch up, coupling, crosstalk etc. ). Experience in top-level floorplan, hierarchical layout methodologies Programming skills in SKILL automation and circuit Design background is a plus. Good communication skills and willingness to work with global team. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment Work Experience Must have expertise on Totem EMIR Self-heating effects, Star RC extraction, and Calibre PV checks (DRC, LVS, Antenna, ERC, PERC etc. ). Good Understanding of layout fundamentals (Matching, EM, ESD, Latch up, coupling, crosstalk etc. ). Experience in top-level floorplan, hierarchical layout methodologies Programming skills in SKILL automation and circuit Design background is a plus

Bachelor or master Degree with 3-10 years of Analog Layout experience. Good understanding of advanced semiconductor technology process and device physics. Full-custom circuit layout/verification and RC extraction experience. Experience in one or more of the following areas is preferable: Mixed signal/analog/high speed layout, e. g. PLL, IO, RF, PMIC, OSC, DC-DC convertor, Temperature sensor, SRAM, TCAM, ROM, MRAM, ESD Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC, LVS, DFM, etc). Experiences in advanced technology node under 16nm/14nm/7nm. 5nm/3nm will be an added advantage. Must have expertise on Totem EMIR Self-heating effects, Star RC extraction, and Calibre PV checks (DRC, LVS, Antenna, ERC, PERC etc. ). Good Understanding of layout fundamentals (Matching, EM, ESD, Latch up, coupling, crosstalk etc. ). Experience in top-level floorplan, hierarchical layout methodologies Programming skills in SKILL automation and circuit Design background is a plus. Good communication skills and willingness to work with global team. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment Work Experience Must have expertise on Totem EMIR Self-heating effects, Star RC extraction, and Calibre PV checks (DRC, LVS, Antenna, ERC, PERC etc. ). Good Understanding of layout fundamentals (Matching, EM, ESD, Latch up, coupling, crosstalk etc. ). Experience in top-level floorplan, hierarchical layout methodologies Programming skills in SKILL automation and circuit Design background is a plus.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL, AMS system modelling and PD teams. Lead technical alignment on verification strategies. Define and architect verification environments and methodologies. Take initiative to drive overall execution efficiency and quality improvements. Improve and evolve existing verification methodologies : Co-Simulation (Co-SIM), UPF Power Aware Simulations (UPF PA Sim), VIP/DIP integration and Verification, increase Formal Verification usage especially FPV, Safety Verification Analyze execution and quality issues to define, develop, and deploy new functional verification methodologies for continuous improvement. Required Qualifications: Solid background in functional verification fundamentals. Experience in: Verification environment development Test plan creation Verification closure RTL and GLS debug skills, formal verification, PA simulation Strong SystemVerilog and UVM methodology expertise. Prior digital verification experience in serial bus multiprotocol PHY IPs (UCIE or SerDes IPs is preferred) B. E/B. Tech/M. E/M. Tech with 10+ years of experience Good to Have (Not Mandatory): Exposure to analog modeling and AMS (Analog/Mixed-Signal)-digital co-simulations. Experience with automotive IP verification (e. g. , fault injection). Emulation exposure. We re doing work that matters. Help us solve what others can t.

> If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 73553 Job Description We are a passionate and dedicated team of world-class analog, mixed-signal and digital design and verification engineers committed to building the next generation of SOCs. This position is for an experienced and equally passionate analog and mixed-signal engineer interested in excellent personal and professional growth opportunities. Your role: You will: Bring state of the art Analog and Mixed Signal IP and products to market. Provide guidance and oversee design and verification, systems, algorithms, etc. to meet product requirements . Interface with Analog and Digital, RF, DV engineers and module design teams to create the detailed specification, report design progress, and to collect, track, and resolve any performance and circuit design issues. Job Segment: Electrical Engineering, Engineer, Telecom, Telecommunications, Electrical, Engineering, Technology

The Role We are looking to expand our team with a Senior Digital IC Design Engineer with experience in the development of mixed-signal components, and behavioral modelling of Power & CLK modules like LDO/DCDC, RC-OSCs, and PLL You will participate in the development of Power & Clock management digital system controller design in close collaboration with analog designers Additionally, you will support the product integration teams on the integration of these components into the semiconductor products What You ll Do Participate in feasibility studies and architecture definitions of new mixed-signal components Participate in detailed specifications and test plans for these components Implement and verify the digital part of the mixed-signal components and participate in the mixed-signal verification Participate in prototyping integration by performing logic synthesis, and digital backend of smaller systems Participate in the development of a silicon evaluation infrastructure, and support the evaluation in the lab What You ll Need Minimum BS/MS in Electrical Engineering or related technical field At least 10 years of relevant work experience in semiconductor product or IP development RTL design of digital IP blocks and systems in Verilog/SystemVerilog Good understanding of mixed-signal semiconductor circuits Experience in logic synthesis, place-and-route, STA

Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). Solid experience of 8 to 12 years in developing high speed IO/ESD/Analog layout design. Expertise in working on FinFet layouts in lower nodes, preference to TSMCN 7nm and below. Expertise in using the best and latest features of Cadence VXL and Calibre DRC/LVS. Basic understanding of IO/ESD designs. Knowledge on Basic /PERL. Capable of working independently and with team and getting work done with contract work force. The ability to work & communicate effectively with global engineering teams.

Job Area: Interns Group, Interns Group > Interim Engineering Intern - HW Qualcomm Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. General Summary: We know our employees ideas change the world. For more than three decades, weve been a global leader in mobile technology, continually pushing the boundaries of whats possible. Working with customers across industries "” from automotive to health care, from smart cities to robotics"” we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU Design Must have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skill Educational Background:Masters, BachelorsElectrical Engineering , VLSI , Embedded and VLSI , ECE

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Solid understanding of Electronics engineering fundamentals, PCB manufacturing process, Mixed-signal and RF circuit analysis techniques. Knowledge of RF & Mixed Signal PCB design, test board debug and using CAD software such as Mentor Graphics DA or Cadence Allegro is mandatory Good understanding of Si-Pi for board designs and ability to use simulation tools like HFSS, ADS, Power SI is mandatory Good knowledge of RF & Digital measurement techniques like S-parameters, TDRs, Eye analysis, jitter, isolation etc. Good ASIC device level characterization skills. System level knowledge is a plus. Able to work comfortably with lab equipment like Oscilloscopes, Network Analyzer, Spectrum Analyzer, Signal Generator, Digitizer etc is a plus Good software skills for writing codes for automation using Python is a plus. Able to communicate clearly, organize effectively and document work thoroughly while working with local and global teams.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualcomm PMIC team is a global organization responsible for delivering power and cost efficient solutions to mobile, compute, AR/VR, Auto and IOT products. Selected candidate will be part a new PMIC analog design team in Qualcomm Bangalore and be part of Qualcomms global PMIC design community. Job function includes but not limited to Oversees definition, design, verification, and documentation of mixed signal circuits and/or products in the field of Power Management. Executes the design and verification strategies of PMICs, for own specific assigned part of a block with supervision from technical lead. Runs functionality checks on a single block to ensure it meets specifications provided by team lead with minimal guidance. Seeks essential knowledge of industry trends, competitor products, and advances in the Power Management field from publicly available information Is actively involved in all aspects of the design from system definition/specification to circuit design and simulation, post silicon debug. Communicate information that may be somewhat complex to others through written documents and orally in meetings. Will require basic skills of negotiation, influence, diplomacy, and tact. Heavy involvement in overseeing layout and silicon evaluation is also expected. Requires expertise in one or more of the following engineering disciplinespower electronics (switch mode and linear), control theory, high accuracy data converters and analog front ends, high bandwidth linear amplifiers, very low power references, electro-migration and transistor reliability, behavioral modeling and UVI techniques. Uses design tools such as Cadence ADE, MathWorks MATLAB, Verilog/VerilogAMS, System Verilog and others. Actively participates in next generation initiatives and innovation.