RTL Engineer

About Eridu AI

Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is looking to hire highly motivated and talented professionals for its RD center in Bengaluru to join our world-class team.

Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI s solution and value proposition have been widely validated with several hyperscalers.

The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World s leading micro-LED display company and developer of the first augmented reality contact lens) .

Visit our website to learn more about our impressive list of investors, advisors and leadership team.

We are seeking an RTL Packet Processing Engineer to help define and implement our industry-leading Networking IC. If youre a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices.

• Packet Processing Design: Design and architect solutions for high-speed networking device, focusing on latency optimization, and quality of service (QoS) support. Prior experience with CAMs, and routing tables.
• Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks. Conduct thorough testing and validation to ensure functionality and reliability.
• Performance Optimization: Analyze and optimize pipelining architectures to improve performance metrics.
• Protocol Support: Provide support for various networking protocols and standards related to input and output queues, including Ethernet.
• Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing, working closely with cross-functional teams, including hardware engineers, firmware developers, and system architects.

• ME/BE with a minimum of 8-15 years of experience.
• Working knowledge of system Verilog, and Verilog is Mandatory

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  Prior experience with ownership of memory subsystems.
• Proven expertise in designing and optimizing packet pipelining and QoS mechanisms, for high-speed networking devices.
• Solid understanding of ASIC design methodologies, including simulation, and verification tools (e.g. Synopsys, Cadence).
• Experience with Ethernet/PCIe networking protocols.
• Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues.
• Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences.