2715 Verilog Jobs - Page 6

The ideal candidate will be required to work on both IP development and integration into SoCs catering to various markets and tech nodes. Job will involve RTL design, front end tools flow and SoC integration/ porting related tasks. Desired Skills And Experience- 8 years of Experience Engineering experience with exposure to front end ASIC tool flows Should be self-driven and independent in tracking and closing tasks with respective owners In depth knowledge of AHB and bus infrastructures like matrix and fabrics Good understanding of ARM based SoC Architecture Exposure to ARM Cortex A/M integration or support Good understanding of SoC DV methodology Good experience in Low-Power design methodology Hands-on experience with ASIC tools Lint, CDC etc System Verilog/Verilog RTL coding Power aware RTL coding/design knowledge Understanding of Clock-Structures/Scheme Good Communication Skills

Wafer Space is looking for smart and enterprising SOC Verification experts to come and work on complex SOC Verification projects. This role will include- Technical execution of SOC Verification projects of complex ARM based SOCs Test Planning, Environment Architecture, SV-UVM environments Desired Skills And Experience- 3 - 7 years experience in Design Verification Excellent Communication and Presentation Skills Expert Knowledge in SOC Verification Expert at Verification - Coverage Driven Test Planning, Architecting Environments, Verification Flow Strong knowledge in System Verilog Knowledge in at least one methodology, OVM, UVM, VMM or RVM Very Good knowledge of protocols, at least one protocol of SATA, USB, Ethernet, PCIE Ability and desire to learn new methodologies, languages, protocols etc. is required

Wafer Space is looking for a smart and enterprising leader with expert knowledge in IP Verification to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking as your role will involve leading 7 to 8 projects at one time. You will be responsible for leading and managing a team, client communication, and project execution. This role will include- Lead an internal IP Verification team, executing projects for an offshore client Be responsible for Test Planning, Environment Architecture and Project Management of Multiple Projects Guide team members in verifying IP's and delivering zero bug IP's Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills And Experience- 8 - 12 years experience in Design Verification Expert Knowledge in IP Verification Very strong knowledge in multiple protocols is highly desired, AMBA protocols and at least one high speed interface Must have expert knowledge in coverage driven test planning Must have expert knowledge in architecting configurable environments Must have very strong System Verilog and UVM background Must be able to lead the team technically in all aspects, must be able to drive multiple projects Past experience leading and managing teams highly desired Excellent Communication and Presentation Skills Ability and desire to learn new methodologies, languages, protocols etc. is required

Wafer Space is looking for some expert RTL Front End Design Engineers, having good knowledge of ASIC design flow. This will be a very challenging and exciting role and will involve very complex designs. Job Responsibilities- Chip integration of high complexity SOCs. Coordinating with various IP owners on receivables and DV, synthesis and Emulation for deliverables Spyglass/CDC for the full chip and will evaluate the incoming bugs and take appropriate action Formal Verification between RTL to Netlist and Netlist to Netlist Manual and Conformal ECO Running Lint (Spyglass) at SoC level. Chip level integration and connectivity. Debugging FV failures ECO implementation. Desired Skills And Experience- 2 - 10 years of experience Sound knowledge in Micro Architecture design and RTL implementatio Understanding of ARM SoCs with AXI/AHB buses, peripherals, CPUs and mobile SOCs is desirable Experience in Synthesis and pre-layout timing analysis Understanding of DFT flow is desirable Experiencing using clear case a must Experienced with VHDL/Verilog/coding and tools like VCS/Verdi/Spyglass/Mentor Zero-in Proficiency in LEC and formal flows. Experience in Perl, TCL and shell scripting Excellent interpersonal & analytical skills with ability to work independently

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SOFTWARE DEVELOPMENT ENGINEER The Role AMD is looking for a senior software engineer to join our growing team. As a key contributor you will be part of a leading team to drive and enhance AMD’s abilities to deliver the highest quality, industry-leading technologies to market. The Person Looking for experienced candidates who want to make an impact on AMD (Xilinx)’s future FPGA Architectures. An ideal candidate for this position should be good with one or more of the below areas: EDA algorithm development, mathematical modeling of hardware architectural aspects, familiarity with FPGA design flows, qualitative and quantitative comparison of hardware Architectures. This role requires candidates to be able to independently come up with analytical / mathematical or otherwise methods to compare and contrast various aspects (related to power, performance and area) of one generation of FPGA PL architecture to future FPGA architectures. Preferred skills: Algorithms, C++, Python, Matlab, Linear programming, ML, FPGA design flows, Verilog, HLS Academic Credentials Master’s degree in computer/software /Electronics Engineering, Computer Science, or related technical discipline Experience with 4+yrs and above experience across levels Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SOFTWARE DEVELOPMENT ENGINEER The Role AMD is seeking a talented, self-driven and motivated software engineer to join its RTL Synthesis software development team in Hyderabad. The candidate will be responsible for design and development of synthesis features and optimizations in AMD’s current and next generation software tools. We are looking for smart, creative people who have a passion for solving complex problems. The Person The ideal candidate has a strong background in algorithms, data structures and SW engineering, with strong foundations in C++, boost / STL and strong coding practices. Experience in logic synthesis, high-level synthesis, or RTL front-end development is preferred. The candidate should have a solid understanding of SW quality and processes. Key Responsibilities Develop and drive execution of comprehensive, highly effective software for sophisticated new technology and new product introduction projects Validate new SW features before releasing them to customers Contribute to a high-functioning feature team Collaborate closely with multiple teams to deliver key planning solutions and the technology to support them Help contribute to the design and implementation of future architecture for a highly scalable, durable, and innovative system Work very closely with dev teams and Project Managers to drive results Required Experience BS or MS in CS, EE or CE with 3+ years of software development experience Background in EDA tools development preferred Strong background in computer algorithms and data structures. Strong background in C++ programming including boost and STL Familiarity with parts of the VLSI Implementation or Verification flow. Familiarity with Verilog or VHDL. Excellent problem solving skills and willingness to think outside the box Experience with production software quality assurance practices, methodologies and procedures Excellent communication skills and experience working with global teams Preferred Experience Compilers, RTL front-end development RTL Synthesis algorithms, datapath or high-level synthesis Timing/area/power optimizations Technology mapping Static timing analysis Simulation, Formal Verification or Design For Test Exposure to FPGAs and FPGA software tool chain. Academic Credentials Bachelor’s or Master’s degree in Computer/Software Engineering, Computer Science, or related technical discipline Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SOFTWARE DEVELOPMENT ENGINEER The Role AMD is seeking a talented, self-driven and motivated software engineer to join its RTL Synthesis software development team in Hyderabad. The candidate will be responsible for design and development of synthesis features and optimizations in AMD’s current and next generation software tools. We are looking for smart, creative people who have a passion for solving complex problems. The Person The ideal candidate has a strong background in algorithms, data structures and SW engineering, with strong foundations in C++, boost / STL and strong coding practices. Experience in logic synthesis, high-level synthesis, or RTL front-end development is preferred. The candidate should have a solid understanding of SW quality and processes. Key Responsibilities Develop and drive execution of comprehensive, highly effective software for sophisticated new technology and new product introduction projects Validate new SW features before releasing them to customers Contribute to a high-functioning feature team Collaborate closely with multiple teams to deliver key planning solutions and the technology to support them Help contribute to the design and implementation of future architecture for a highly scalable, durable, and innovative system Work very closely with dev teams and Project Managers to drive results Required Experience BS or MS in CS, EE or CE with 3+ years of software development experience Background in EDA tools development preferred Strong background in computer algorithms and data structures. Strong background in C++ programming including boost and STL Familiarity with parts of the VLSI Implementation or Verification flow. Familiarity with Verilog or VHDL. Excellent problem solving skills and willingness to think outside the box Experience with production software quality assurance practices, methodologies and procedures Excellent communication skills and experience working with global teams Preferred Experience Compilers, RTL front-end development RTL Synthesis algorithms, datapath or high-level synthesis Timing/area/power optimizations Technology mapping Static timing analysis Simulation, Formal Verification or Design For Test Exposure to FPGAs and FPGA software tool chain. Academic Credentials Bachelor’s or Master’s degree in Computer/Software Engineering, Computer Science, or related technical discipline Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a motivated graduate in Electronics Engineering, ready to launch your career in the semiconductor industry. With internship or project experience in digital design or verification, you bring a strong academic foundation and a passion for technology. You thrive in collaborative, multicultural teams, value open communication, and are committed to continuous learning. You pay attention to detail, enjoy solving problems, and adapt quickly to new tools and methodologies. Proactive and eager, you are excited to make a real impact while growing in a supportive, inclusive environment where your ideas are valued. What You’ll Be Doing: Collaborating with experienced engineers to develop and deliver high-quality verification solutions for advanced semiconductor projects. Applying your knowledge in Verilog, SystemVerilog, and UVM to support verification and design validation tasks. Assisting in the development and maintenance of testbenches, scripts, and automation flows to improve verification efficiency and coverage. Participating in technical reviews and supporting the creation of test plans and testcases for key protocols such as PCIe. Analyzing, debugging, and resolving design issues in partnership with global teams. Engaging in team knowledge-sharing sessions and ongoing training to stay current with evolving verification methodologies and Synopsys technologies. The Impact You Will Have: Enable Synopsys’ customers to achieve first-time silicon success through robust verification and support. Enhance the quality, reliability, and performance of next-generation semiconductor products. Contribute to the development of scalable and reusable verification environments. Drive customer satisfaction by assisting in timely and effective technical solutions. What You’ll Need: Bachelor’s or Master’s degree in Electronics Engineering or a related field. Internship or project experience in digital design or verification. Proficiency in Verilog and SystemVerilog; exposure to UVM is a plus. Familiarity with scripting languages (Python, TCL, Shell) is beneficial. Strong analytical and debugging skills to resolve technical issues efficiently. Who You Are: Clear and confident communicator, able to convey complex ideas effectively. Collaborative team player with a positive attitude and a willingness to learn. Detail-oriented and organized, able to manage multiple priorities. Proactive, adaptable, and open to feedback and challenges. The Team You’ll Be A Part Of: You will be a valued member of a dynamic Verification IP (VIP) team focused on delivering state-of-the-art solutions for Synopsys’ semiconductor customers. The team works closely with R&D, product management, and customer support to ensure seamless integration and customer success. Together, you’ll innovate, share knowledge, and advance industry-leading technologies. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Alternate Job Titles: Senior R&D Memory Design Engineer Memory Circuit Design Specialist SRAM/ROM Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and detail-oriented engineering professional, eager to push the boundaries of memory technology and create a measurable impact in the semiconductor industry. With a solid foundation in CMOS fundamentals, you are fascinated by the intricacies of memory architectures, and you thrive on solving complex technical challenges. Your expertise in transistor-level circuit design is complemented by a deep understanding of SRAM and ROM, and you are adept at optimizing designs for power, performance, and area. You bring a collaborative spirit, valuing the diverse perspectives of cross-functional teams to deliver innovative solutions. Your analytical mindset drives you to conduct thorough simulations and validation, ensuring the highest standards of reliability and efficiency. You embrace continuous learning, staying updated with the latest advancements in memory design and verification. Your programming skills, especially in Linux scripting and PERL, empower you to automate and streamline design processes. You are an excellent communicator, able to articulate technical concepts clearly and work effectively with colleagues from diverse backgrounds. Above all, you are committed to excellence, integrity, and fostering a culture of innovation and inclusion. What You’ll Be Doing: Designing and simulating transistor-level circuits for advanced SRAM and ROM memory arrays, including peripheral circuits and sense amplifiers. Conducting detailed timing, reliability, and variation analyses—such as Monte Carlo simulations—to ensure robust memory performance under diverse scenarios. Optimizing memory designs for power, performance, and area (PPA) to meet or exceed product requirements and industry standards. Running comprehensive design verification and validation, including margin analysis, Verilog simulation, and liberty checks, to guarantee functional accuracy and manufacturability. Collaborating closely with cross-functional teams—including layout, verification, and product engineering—to deliver state-of-the-art memory solutions. Utilizing Linux scripting and programming skills to automate design processes, improve workflow efficiency, and support continuous integration initiatives. Documenting design methodologies, contributing to technical reviews, and supporting knowledge sharing across the organization. The Impact You Will Have: Drive innovation in memory design, directly influencing the performance and efficiency of next-generation semiconductor products. Enhance Synopsys’ competitive advantage by delivering highly optimized, reliable, and scalable memory solutions for global customers. Contribute to the development of cutting-edge products that power applications from mobile devices to AI and automotive systems. Promote rigorous quality standards through meticulous validation and verification, minimizing risks and ensuring successful silicon implementation. Strengthen cross-functional collaboration, fostering a culture of knowledge sharing and continuous improvement within the team. Mentor and inspire junior engineers, supporting their growth and helping to build a diverse, high-performing engineering community. What You’ll Need: Solid understanding of CMOS fundamentals and transistor-level circuit design principles. Deep knowledge of SRAM and ROM memory architectures, including array and peripheral circuit design. Hands-on experience with simulation tools for timing, reliability, and variation analysis (e.g., Monte Carlo simulations). Proficiency in design verification and validation techniques, such as margin analysis, Verilog, and liberty checks Strong Linux scripting skills; programming capability in PERL is a plus. Experience with Verilog RTL coding for memory component modeling and verification. Who You Are: Analytical thinker with strong problem-solving abilities and attention to detail. Excellent communicator, able to clearly articulate technical concepts and collaborate across diverse teams. Proactive, self-motivated, and adaptable to fast-paced, dynamic environments. Team player who values inclusion, open feedback, and continuous learning Organized and methodical, with a strong commitment to quality and innovation. The Team You’ll Be A Part Of: You will join a dynamic, collaborative team of expert engineers dedicated to developing state-of-the-art memory solutions for a wide range of applications. Our team embraces diversity, fosters continuous learning, and leverages collective expertise to tackle some of the most challenging problems in semiconductor design. You’ll be empowered to share your ideas, drive innovation, and contribute to a culture that values excellence and mutual respect. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Hyderabad /Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A US based well-funded product-based startup looking for Highly talented Senior Physical Principal / Staff IP/RTL Design Engineer (AI Accelerator) – Multiple positions - Hyderabad /Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Well-funded product startup is looking for RTL Design Engineers to contribute to the development of novel high performance AI accelerators from scratch. In this role you will collaborate with cross-functional teams, including architect, software, verification, physical design, systems engineers, to define and implement next generation AI architectures. We are seeking highly experienced individuals who have a passion for innovation and are excited about the opportunity to create world class products from India. The key responsibilities for this role include, but are not limited to: Key Responsibilities Design and implement high-performance TPUs/MPUs and other related AI blocks using RTL. Own IP/block-level RTL from spec to GDS, including design, synthesis, and timing closure. Optimize design for power, performance, and area (PPA). Interface with physical design and DFT (Design for Test) engineers for seamless integration. Drive design reviews, write design documentation, and support post silicon bring-up/debug. Minimum Qualifications B.S./M.S./Ph.D. in ECE/CS from top engineering college with 5-15 years of related experience. Previous experience in either high performance processor design or AI accelerator design is plus. Clear understanding of floating-point arithmetic, vector processing, SIMD, MIMD, VLIW, EPIC concepts. Strong grasp of digital design fundamentals, computer architecture, virtual memory and high-speed data-path design. Proficiency in Verilog/SystemVerilog and simulation tools. Experience with EDA tools (e.g., Synopsys, Cadence) for synthesis, lint, CDC, and timing analysis. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

www.omnidesigntech.com SoC Director / Senior Principal Engineer Bangalore / Hyderabad About Omni Design Technologies Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated system-on-chip (SoC), in applications ranging from 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the internet-of-things (IoT). Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few MSPS to more than 100 GSPS sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins-Colorado, Bangalore-India, Hyderabad-India, Dublin-Ireland, Boston-Massachusetts. Bangalore Engineering – Digital Circuit Design / Hyderabad / Bangalore SOC Development – Engineering / Full-time / Hybrid Omni Design is working on exciting solutions and chips for next generation automotive and space applications and looking for talented and capable engineers. The Director of digital and mixed-signal engineering will be responsible for development of mixed-signal SOC being developed at ODT and build the digital engineering team and will work Analog/RF engineering, FW engineering, verification, Systems Validation team, Operations, SOC Architects, and report to the VP / SVP of ASIC Engineering. Nice to have experience in UCIE PCIE Gen5/Gen6/Gen7 Roles and Responsibilities Manage digital team, hire, and retain best talent Lead SOC integration design team to develop and productize next generation mixed-signal RF/communication SOCs Work with cross-functional project teams to define product specifications, system architecture, HW/SW partitioning, and execution plan Implement best SoC development practices and improve design methodology to maximize efficiency and predictability Deliver chip architecture, design, integration, programming model, verification, and manage hand-off to backend Support Silicon and System Validation, support system integration, and production testing Drive innovation and provides leadership to the organization to ensure world-class system solutions and flawless execution Qualifications BSEE Required, MSEE Preferred Proven track record of success in high-performance/high-volume semiconductor industry SoC, embedded CPU and bus architectures, networking, and control interfaces Communications / DSP algorithms and power / area efficient implementations Digital IC design, design for low power and high speed, design for test (DFT) System modeling, RTL coding, Lint / CDC checking, simulation, synthesis, power analysis, timing analysis in Cadence / Synopsys design environments Directed and constrained random verification, UVM methodology Embedded systems FPGA emulation, lab debug and chip validation Project planning and execution, and performing design tradeoffs to achieve performance, power, die size, and schedule targets Self-motivated, excellent communication skills, and ability to excel and to provide leadership in a fast-paced environment Senior Management experience preferred Work with architecture, physical design, and design teams to lead the implementation of the digital architecture. Develop and refine specification of the micro-architecture for the digital architecture. Is in tune with industry trends and contributes to consistent roadmap decisions. Experience 12-20+ years of experience in the area of RTL design and verification of silicon At Least 3+ years experience in leading low-power mixed-Signal SOC design 10+ years of experience with FPGA architecture specification and design (Altera or Xilinx) for high-speed serial protocols, including USB-SS, PCIe, SATA/SAS, DisplayPort Experience in leading, specifying, and work with Analog/RF team in developing, verifying, and productizing SERDES, CDR, and PLL/DLL designs Experience with USB 3.0, DisplayPort, PCIe, or SATA based silicon designs preferred Strong background in analog/mixed-signal integrated SOC Development Strong Hardware design knowledge and familiarity with signal integrity Strong foundation in SoC architecture, design, verification and physical implementation Strong analytical problem solving, and attention to details Knowledge of wireless, mobile, and storage domains Expertise in Verilog/System Verilog, C/C++/SystemC, UVM, Scripting languages like Perl/Python, etc. Excellent technical documentation skills Excellent written and verbal communication skills Excellent interpersonal skills, self-motivated, self-starter Experience in startup environment Expectations Put the RTL for the Full chip together. Evaluate the IP we have to license – like PCIe, LPDDR4, JESD 204C PHY Help develop any BIST Work with Verification Team to develop the FC Simulation test suites Develop the RTL for the various state machines and interfaces Run a few of the simulations Help with the FC simulations debug Help close the timing issues if any come up and work with the PD person to resolve any SI issues. Be a mentor and lead a team of Digital design engineers Work with Systems and Test engineering team to help validate the parts and release them to production We are looking for trailblazers ... We strongly believe that the pace of the ongoing hardware revolution will be greatly accelerated by Design’s IP cores and the rapidly emerging semiconductor embedded design business ecosystem. we have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring our vision to fruition. If you are interested in making an impact as part of a young, fast growing, cutting edge technology company, please reach out to us. We are a equal opportunity employer. We offer excellent compensation. We seek individuals that share our high standards and commitment to excellence. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com 'Mining The Knowledge Community'

Principal IP/RTL Design Engineer for TPU Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore IP/RTL Design Engineer for TPU Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a motivated graduate in Electronics Engineering, ready to launch your career in the semiconductor industry. With internship or project experience in digital design or verification, you bring a strong academic foundation and a passion for technology. You thrive in collaborative, multicultural teams, value open communication, and are committed to continuous learning. You pay attention to detail, enjoy solving problems, and adapt quickly to new tools and methodologies. Proactive and eager, you are excited to make a real impact while growing in a supportive, inclusive environment where your ideas are valued. What You’ll Be Doing: Collaborating with experienced engineers to develop and deliver high-quality verification solutions for advanced semiconductor projects. Applying your knowledge in Verilog, SystemVerilog, and UVM to support verification and design validation tasks. Assisting in the development and maintenance of testbenches, scripts, and automation flows to improve verification efficiency and coverage. Participating in technical reviews and supporting the creation of test plans and testcases for key protocols such as PCIe. Analyzing, debugging, and resolving design issues in partnership with global teams. Engaging in team knowledge-sharing sessions and ongoing training to stay current with evolving verification methodologies and Synopsys technologies. The Impact You Will Have: Enable Synopsys’ customers to achieve first-time silicon success through robust verification and support. Enhance the quality, reliability, and performance of next-generation semiconductor products. Contribute to the development of scalable and reusable verification environments. Drive customer satisfaction by assisting in timely and effective technical solutions. What You’ll Need: Bachelor’s or Master’s degree in Electronics Engineering or a related field. Internship or project experience in digital design or verification. Proficiency in Verilog and SystemVerilog; exposure to UVM is a plus. Familiarity with scripting languages (Python, TCL, Shell) is beneficial. Strong analytical and debugging skills to resolve technical issues efficiently. Who You Are: Clear and confident communicator, able to convey complex ideas effectively. Collaborative team player with a positive attitude and a willingness to learn. Detail-oriented and organized, able to manage multiple priorities. Proactive, adaptable, and open to feedback and challenges. The Team You’ll Be A Part Of: You will be a valued member of a dynamic Verification IP (VIP) team focused on delivering state-of-the-art solutions for Synopsys’ semiconductor customers. The team works closely with R&D, product management, and customer support to ensure seamless integration and customer success. Together, you’ll innovate, share knowledge, and advance industry-leading technologies. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

This role has been designed as ‘Hybrid’ with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: Job Family Definition: Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and system simulation, and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits. Analyzes designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions. May direct support personnel in the preparation of detailed design, design testing and prototype fabrication. Management Level Definition: Contributes to assignments of limited scope by applying technical concepts and theoretical knowledge acquired through specialized training, education, or previous experience. Acts as team member by providing information, analysis and recommendations in support of team efforts. Exercises independent judgment within defined parameters. What you'll do: We are looking to hire sharp ASIC Design Engineer with excellent communication and leadership skills. You will be part of a fast paced team responsible for delivering high-speed ASICs for large, complex systems. You will have a significant opportunity to interact with system design teams across geographies. Responsibilities: Define and architect high-performance blocks for the latest, most advanced networking ASICs Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power Collaborate with the verification team in the development of the test plan and assist in debugging test failures Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes What you need to bring: 3+ years of ASIC design experience Strong Verilog RTL coding skills Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus Knowledge of high performance memory subsystems Knowledge of multi-domain clock synchronization and high-speed serial interfaces Strong problem solving and ASIC debugging skills Excellent written and verbal communications skills MSEE or BSEE is required Additional Skills: Accountability, Accountability, Action Planning, Active Learning (Inactive), Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more} What We Can Offer You: Health & Wellbeing We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing. Personal & Professional Development We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division. Unconditional Inclusion We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. Let's Stay Connected: Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE. #india #networking Job: Engineering Job Level: TCP_01 HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity. Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities. HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories. Job Id: F1kTU0mF/5mdL0kUZ8/iOE0nRcDTT13a82g522bHW7qRZMUX+0oO3LrOpholEmZDNCDyz89hVOm9RtIKDW8H/qE/idttekvZZm0BwJQK5S9WWgbLGwlsFbXxrQIG3LeTzMRT4ouPGHraWbHTnpxoQpe+wpsX/CiTfAaj6wGeoTdW+C3yKKt/QVvteHoCFvg=

Principal RTL Design Engineer & Architect Bangalore We are seeking a seasoned RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in leading state of the RTL designs involving solutions for automotive camera and display systems. Responsibilities • Design and develop microarchitectures for a set of chips involving MIPI CSI,DSI and SerDes protocols • Microarchitecture and RTL coding ensuring optimal performance, power, area • Collaborate with software teams to define configuration requirements, verification collaterals etc. • Work with verification teams on assertions, test plans, debug, coverage etc. Qualifications and Preferred Skills • BTech, MTech in ECE/EE • 10+ years hands-on experience in microarchitecture and RTL development • Proficiency in developing micro-architecture from the design requirements, defining the H/W- S/W interface • In-depth understanding of MIPI CSI and DSI protocols • Experience designing IP blocks for video and audio design Proficiency in Verilog, System Verilog • Familiarity with industry-standard EDA tools and methodologies • Experience with large high-speed, pipelined, and low power designs • Excellent problem-solving skills and attention to detail • Strong communication and collaboration skills • Experience with modern programming languages like Python is a plus

About the job Job Location: Bangalore/ Hyderabad Notice Period: 15 days to 30 Days Minimum: 4 Years Key Responsibilities: Developing test plans Coding and bring up of asm, c++ tests UVM test bench components coding and maintaining Debugging regression fails Protocol: DDR,PCIE,USB,MIPI, PCIE Preferred Experience: Should have worked on Processor based System or Sub-system level verification Hands on experience with assembly, UVM, SV, C++ Experience in developing complex test bench/model in UVM, Verilog, System Verilog Hands on experience in developing test plans, coverage closure Ability to code readable, maintainable and verifiable code using UVM, SV, Strong digital design concepts Experience in developing asm/C++ tests will be an added advantage Experience in Power Management, Clock, Reset will be an added advantage Experience/Knowledge DPI Interface, Ruby/Perl script programming skills will be an added advantage Kindly Share/Refer himabindu.jeevarathnam@acldigital.com

Job description Job Location: Hyderabad Experience Level 5+ years The position involves designing, developing and deploying UVM based reusable testbenches for RTL unit blocks, sub-system level and top-level systems with emphasis on verifying the functionality and generating the code/functional coverage reports. The candidate should come up with test plans and test cases in order to achieve 100% code coverage and functional coverage. Educational Qualification: · Bachelor major in electronics, embedded programming, ECE, EEE. Key Requirements: · Experience in ASIC/FPGA verification using System Verilog. · Develop and sign off on test plans and test cases. · Strong knowledge of digital design, Verilog, System Verilog, UVM, C/C++. · Experience in AMBA AHB/AXI/APB based IPs design/verification. · Experience in usage of assertions, constrained random generation, functional and code · Coverages. · Experience in FPGA design and FPGA EDA tools will be a plus. · Experience in scripting, such as TCL, Perl, Bash and python to automate the verification · Methodologies and flows. · Able to build and set up scalable simulation / verification environments. · Ability to focus on finding the design issues and corner cases. · Knowledge of version control systems (GIT is preferable).

Overview Lead Verification engineer Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Requirements Bachelor’s/ Master’s degree or higher in EEE/ECE 7+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or DRAM. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Responsibilities Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

You will be responsible for designing and developing FPGA and FPGA-based SoCs for new electronic products, ranging from simple hardware solutions to highly complex embedded processing systems. Your tasks will include developing detailed specifications based on requirements, implementing FPGA designs, collaborating with the design team to evaluate alternatives, performing implementation activities like timing analysis and simulations, preparing validation plans, and working on Xilinx Cores such as DDR4/LPDDR4/PCIE/USB/Ethernet IP cores. Additionally, you will debug using Chip scope/Protocol aware Logic Analyser/high-speed probes, collaborate with the verification team, participate in hardware bring-up, support hardware development through schematic design and PCB layout, and document ideas, designs, and specifications to Enercons standards. Mentoring junior members of the engineering staff will also be part of your responsibilities to promote design team abilities and establish good working practices. You should possess demonstrated skill in developing original designs with Verilog for FPGAs and/or FPGA-based SoCs, a strong understanding of FPGA design and architectural concepts, specific experience with common FPGA platforms such as Xilinx, and a working knowledge of tools and methodologies used in FPGA development. Experience with Xilinx family of SoCs and associated interfaces (AXI4 bus, High-speed transceivers, PCIe, DDR, etc.) is preferred. Additionally, you should have experience in hardware development including schematic and PCB layout tools, troubleshooting hardware issues using electronics lab equipment, and the ability to work with minimum supervision while following established design procedures. Good interpersonal skills and the ability to work between multiple departments are essential for this position. For this role, you are required to have a 4-year degree or equivalent experience in ECE Engineering or a related engineering discipline, along with a minimum of 5 years of FPGA development or equivalent experience. You should be able to demonstrate a sound understanding of the principles involved, possess a good academic background, and have the ability and enthusiasm to explore and work in new areas.,

Lekha Wireless is a leading provider of wireless communication technology products and solutions, with its headquarters located in Bengaluru, India. We specialize in developing world-class products utilizing 4G, 5G, and proprietary technologies to meet various Radio Access Network requirements. As a member of our dynamic team, you will be involved in tackling both current and next-generation challenges within the field of wireless communication. Your responsibilities will include working on signal chain implementation for a variety of wireless communication products, designing cores and interfaces to facilitate high-speed data paths, and offering technical leadership in complex design processes. Ideally, you should hold a graduate or post-graduate degree in Electronics, Electrical, Instrumentation, or a related discipline, with 2 to 7 years of experience in the design and development of complex FPGA designs. Key Requirements: - Proficiency in Verilog/VHDL - Strong understanding of FPGA architectures such as RFSoC, Ultrascale, Zynq, and familiarity with STA and electrical interfaces/constraints of FPGAs - Expertise in signal processing, networking, and connectivity IP Cores (e.g., 1G/10G Ethernet, JESD, PCIe, SRIO, Memory cores) - Hands-on experience with Xilinx Vivado tool flow - Sound knowledge of general processor, memory architectures, and embedded peripherals - Understanding of hardware and embedded interfaces for system bring-up - Ability to effectively collaborate with hardware and embedded functions - Strong communication skills in design and debug processes Preferred Skills: - Familiarity with communication signal chains - Previous experience in Wireless communication system and Radio integration - Proficiency in DSP fundamentals Join us at Lekha Wireless to be a part of an innovative team dedicated to pushing the boundaries of wireless communication technology and creating impactful solutions for the future.,

Hughes Systique Corporation (HSC) is a leading global digital solutions and service provider, currently expanding its team in Dehradun, Uttarakhand. This presents an excellent opportunity for FPGA Design Engineers to engage in cutting-edge projects with a multinational company situated in Dehradun. IKSANA is actively supporting HSC in this recruitment drive. About Hughes Systique Corporation (HSC): HSC is a multinational company specializing in delivering innovative solutions in Networking, AI & ML, Retail, Automotive, IoT, Blockchain, and Security. The team at HSC comprises world-class domain experts, system architects, and engineers collaborating with global clients on challenging, innovative, and impactful projects. Role: FPGA Design Engineer Location: Dehradun (Full-Time, On-Site) Experience: 3-6 Years Type: Permanent Openings: 2 Note: This position is based in Dehradun and welcomes candidates currently located in Dehradun or professionals originating from Dehradun who are seeking to relocate back. Required Skills: - FPGA Design and Development - Proficiency in Verilog and/or VHDL - Experience with Xilinx Vivado tools - Familiarity with ModelSim and UVM Educational Background: Candidates should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Role Overview: HSC is in search of experienced FPGA developers to join their Dehradun team, focusing on the design, development, and optimization of complex FPGA-based systems for various applications. The ideal candidate will possess a robust background in FPGA design, verification, and implementation, along with experience in collaborating with hardware and software engineers to integrate FPGA designs into larger systems. Exposure to the latest FPGA technologies and techniques is highly desirable. If you possess significant expertise in FPGA design and aspire to be a part of a company that prioritizes learning, innovation, and career growth, we are eager to connect with you. To Apply: Please submit your CV to aayushi@outlookwork.com Contact Person: Aayushi Sharma Contact Number: +91 80063 07272,

As an Electronics Design Engineer, you will play a crucial role in the development and implementation of cutting-edge electronic systems. Your responsibilities will include working with digital logic technologies like FPGAs and ASICs, designing and verifying integrated circuits (ICs) and printed circuit boards (PCBs), and finding innovative solutions for efficient power usage and electronic equipment design. To excel in this role, you should possess a solid understanding of electronic engineering principles and hands-on experience with hardware design tools and simulation environments. Your key responsibilities will involve designing, simulating, and implementing digital logic using FPGA and ASIC technologies. You will be tasked with developing and verifying layouts for ICs and PCBs using industry-standard tools. Collaboration with cross-functional teams to seamlessly integrate electronic systems into larger platforms will be a critical aspect of your role. Additionally, you will conduct testing, debugging, and validation of electronic components and systems while focusing on optimizing power usage and performance of electronic equipment. It will also be essential for you to document design processes, test results, and technical specifications accurately. In terms of skills, you should be proficient in VHDL/Verilog for FPGA/ASIC development and have experience with PCB design tools such as Altium Designer, Cadence, or Mentor Graphics. A good knowledge of IC design and verification methodologies, along with a strong understanding of electronic circuits and power systems, will be beneficial. Secondary skills that would be advantageous include familiarity with embedded systems and microcontroller programming (e.g., ARM, PIC), experience with simulation tools like SPICE or ModelSim, and a basic understanding of signal integrity and thermal analysis. Effective communication and teamwork skills will also be essential for successful collaboration within the team. To qualify for this role, you should hold a Bachelors or Masters degree in Electronics Engineering, Electrical Engineering, or a related field. This position offers a challenging yet rewarding opportunity to contribute to the advancement of electronic systems and technologies.,

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Engineer Analog Design to join our memory interface chip design team in Bangalore. You will be working alongside some of the brightest inventors and engineers in the world to develop products that make data processing faster and more secure. In this role, you will report to the Director of Engineering and take ownership of the analog mixed signal circuit design activities for high-performance mixed signal chip products. The Rambus memory interface chips team is known for delivering advanced chipset solutions for server memory sub-systems. As a Principal Engineer Analog Design, you will have the opportunity to invent solutions that enhance the performance of next-generation high-performance mixed signal products. You will also gain valuable experience working through all phases of chip product design, from concept to volume production. Your responsibilities will include defining optimal architectures to meet competitive product specifications, designing, simulating, and characterizing high-performance and high-speed circuits such as transmitters, receivers, LDOs, PLLs, DLLs, and PI circuits. You will create high-level models for design tradeoff analysis, develop behavior models for verification simulations, and collaborate with the layout team on floor planning to demonstrate post-extraction performance. Additionally, you will mentor and manage junior team members, fostering a growth mindset and promoting collaboration and inclusion. To qualify for this position, you should have a Master's degree with 8+ years of experience (or a PhD with 6+ years) in CMOS analog/mixed-signal circuit design. Prior experience in circuits like transmitters, receivers with CTLE and DFE, PLLs, DLLs, PIs, and LDO regulators is essential. Knowledge of design principles for practical tradeoffs, high-speed chip-to-chip interfaces, and experience in modeling and scripting are advantageous. Strong written and verbal communication skills, along with the ability to work effectively in cross-functional and globally dispersed teams, are also required. About Rambus: With 30 years of innovation and semiconductor expertise, Rambus leads the industry in products and solutions that enhance speed performance, expand capacity, and improve security for various applications. Rambus" interface and security IP, as well as memory interface chips, enable SoC and system designers to realize their future visions. Rambus offers a competitive compensation package, including base salary, bonus, equity, and employee benefits. We are committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during the job application process. If you require assistance or accommodations due to a disability, please inform us during the application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. To learn more about Rambus, visit rambus.com, and explore current career opportunities at rambus.com/careers/.,

You should have a Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science, focusing on computer architecture, or equivalent practical experience. With 4 years of experience in RTL coding and experience with RTL quality checks methodologies such as Lint, CDC, RDC. A Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with a specialization in computer architecture is preferred. Experience in implementing Camera ISP image processing blocks, Video processing blocks, Machine Learning IPs, or other multimedia IPs like Display or Video Codecs would be advantageous. Also, familiarity with ASIC design methodologies for clock domain checks and reset checks is preferred. Join a team that pioneers innovation, crafting custom silicon solutions to drive the future of Google's direct-to-consumer products. Contribute to developing products that are adored by millions worldwide, shaping the next generation of hardware experiences for unparalleled performance, efficiency, and integration. The gChips team focuses on custom silicon solutions that enhance user experiences in Google Hardware products, optimizing performance and power for specific use cases. This includes SoCs and other integrated circuits for the product portfolio. Collaborating with various teams across Google, gChips identifies silicon requirements for the future and stays informed about the latest chip technologies and standards. As part of the team designing interconnect IP for Pixel SoCs, you will work with architecture, software, verification, power, timing, and synthesis teams to deliver quality RTL. Your responsibilities will include developing microarchitecture, Verilog/SystemVerilog RTL coding, simulation debugging, and RTL implementations meeting power, performance, and area goals. You will also be involved in synthesis, timing/power closure, pre-silicon, and post-silicon bring-up, along with collaborating with global teams at different sites. Google's mission is to make the world's information universally accessible and useful, combining AI, Software, and Hardware expertise to create innovative experiences. By researching, designing, and developing new technologies, we aim to enhance computing speed, seamlessness, and power, ultimately improving people's lives through technology. Your responsibilities will involve collaborating with architects to develop microarchitecture, RTL coding, and performing simulation, debug, and quality checks. You will work on RTL implementations meeting power, performance, and area goals, participate in synthesis and timing/power closure, and support pre-silicon and post-silicon activities. Additionally, you will travel to collaborate with global teams at different sites worldwide.,