2715 Verilog Jobs - Page 3

Skills/Experience: Proficient in STA timing fixes, ECO and Synthesis of complex SOCs at Sub system level, Block level and Chip level. Tools: Design compiler, Prime time, Tempus Experience (years) : 3+ Year Education Qualification: B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Work Profile : - Work on development of custom Analog circuit boards for applications related to RF, interfaces etc. - Implement new features and bug fixes - Verify analog/mixed-signal integrated circuits - Develop test cases to verify new features and bug fixes - Review and update the user manuals for software tools. - Supporting digital modelling of analog circuits for mixed-signal verification - Creating design specifications and circuit schematics - Work both independently and in a team environment, with the opportunity to provide technical leadership to other members of the engineering team - Create and/or modify specification documents detailing system design and enhancements to meet marketing requirements - Collaborate with others in the creation of technical reports, whitepapers, and user documentation Requisites : - EE/EEE/ECE graduate, undergraduate degree from reputed Tier 1 or Tier 2 colleges . - Strong knowledge of analog integrated circuit design fundamentals - Proven experience taking designs from concept to production - Experience in analog/mixed-signal IC design & verification - Understanding of BJT, CMOS and Op-Amp technologies. - Good understanding of analog/mixed-signal design flows (Cadence, Synopsys) - Transistor and system level simulation skills - Discrete time and continuous time signal processing skills - Strong lab and silicon validation skills - Verilog based digital design and test bench development, is a plus - Strong communication skills, both written and verbal.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: FPGA Design. Experience: 3-5 Years.

Over 3 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flow Proficient with Verilog, System Verilog and UVM. · Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard) · Good in defining and developing UVM based verification frameworks, testbenches, processes and flows. · Good in working in Linux and Windows environments. · Familiarity with power aware simulation and firmware/hardware co-verification is a plus. · Familiarity with industry standard high-speed protocols such as USB, PCIE, UFS, SATA, Ethernet is a plus. · Familiarity with industry standard interconnects such as AMBA (AXI, APB, AHB) is a plus.

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Could you be the full-time Talent Acquisition Specialist in Bengaluru were looking for? Your future role Take on a new challenge and apply your recruitment expertise in a dynamic and collaborative environment. Youll work alongside passionate and highly skilled teammates. You'll play a pivotal role in shaping our workforce by driving recruitment efforts aligned with our business objectives. Day-to-day, youll work closely with teams across the business (including HR Business Partners, Hiring Managers, and Support Teams), manage candidate databases, and ensure seamless recruitment processes, and much more. Youll specifically take care of preparing and publishing recruitment dashboards, as well as organizing and tracking e-recruitment activities, but also contribute to improving administrative processes. Well look to you for: Preparing and publishing monthly recruitment dashboards of open positions vs. budget vs. offered positions Consolidating and managing HAF data Maintaining and administering CV databases and candidate records Organizing and publishing job advertisements on various platforms Coordinating candidate interviews and preparing associated documentation Tracking and reporting on recruitment activity and progress Proposing and implementing process improvements in recruitment administration All about you We value passion and attitude over experience. Thats why we dont expect you to have every single skill. Instead, weve listed some that we think will help you succeed and grow in this role: MBA or graduate degree 7+ years of experience in recruitment, with exposure to the industry Experience in recruitment administration and familiarity with e-recruitment tools Proficiency in IT software such as Excel, Word, and PowerPoint Knowledge of ALPS database/systems (preferred) Strong communication and interpersonal skills High collaboration and stakeholder management abilities.

Skills/Experience: Independent layout development of High Speed blocks like SerDes, Rx, Tx, , PLL, ADC, LDO, Bandgap etc Strong debug skills and good communication Education Qualification: BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IJTAG. and MBIST/LBIST. Experience in Tessent based ATPG flow, GLS and Post-silicon-debug. Hands-on in Perl/Tcl/Python scripting. Excellent analytical, and problem-solving skills. Perform Core and SOC level ATPG to meet Automotive grade quality. Hierarchical ATPG retargeting and Pattern release for application on ATE. Perform SOC and Core level Timing/Non-timing GLS. Silicon bring-up, diagnosis and support for physical failure analysis. Enable Emulation of Gate level SCAN patterns. Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s chip design team. As a member of DFT team you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug. You will play a key role in silicon bring-up, workload execution and validation. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Proficiency in C and Python for validation and automation Hands on experiencec in Writing/ maintaining test programs and automation scripts using C and Python Experience in chip bring-up /debug Experience in chip-level throttling issues including power, thermal, and frequency-related behavior Knowledge on Analyzing trace data/logs and on-chip debug outputs for failure root cause Should be able to Interpret Verilog RTL to support functional and performance debug Collaborate with RTL, firmware, validation, and DFT teams for end-to-end issue resolution Strong understanding of chip boot flows and bring-up sequences Familiarity with assembly-level debugging on RISC/V, ARM, or other architectures Ability to read and debug Verilog RTL code In depth understanding of chip internals, including resets, clocking, and register programming Preferred technical and professional experience Experience in post-silicon validation, emulation or pre-silicon environments Exposure to firmware-hardware interactions Knowledge of debug infrastructure and on-chip monitoring tools Familiarity with version control tools like Git

Lead the Architecture, Design and development of processor MMU (Memory management unit) for high- performance IBM Systems. - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the MMU feature enhancements. - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 to 15 years of relevant experience - At least 1 generation of experience in the memory management/ memory controller delivery leadership. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. Good understanding of industry trends & advances in - 8 to 15 years of relevant experience - At least 1 generation of experience in the memory management/ memory controller delivery leadership. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. Good understanding of industry trends & advances in architecting high bandwidth memory solutions.

End-to-end design and development of features for IBM high performance Mainframe and POWER processors and ASICs. Develop the feature, present the proposed architecture in the High level design discussions Estimate the overall effort to develop the feature Develop micro-architecture, Design RTL, Collaborate with the Verification, Physical design, FW teams to develop the feature Pre Silicon: Signoff the Design that meets all the functional, area and timing goals Post Silicon: Bringup and Validate the hardware functionality Required education Bachelor's Degree Required technical and professional expertise 1 to 3 years of professional experience Experience with HDLs- VHDL/ Verilog Understand and Design Power efficient logic. Drive design closure including test plan reviews and verification coverage Understand of logic synthesis, Physical Design concepts, Timing, and constraints Prior experience in and knowledge in one or more areas : I2C, I3C, SPI, AXI, AHB, APB, boot, security, debug and trace, OTP ROM, clocks and resets, silicon bringup

Job Title Electrical Architect- Firmware & Control Job Description Job Description You have the opportunity to be part of an exciting team and contribute to the design, development and maintenance of Imaging Components. In this role of Electrical Architect- Firmware & Control , you are responsible for the development and maintenance of X-ray generators. Together with a multidisciplinary team of engineers, you play a crucial role in getting the X-ray generators to the required performance, by owning the design, development, testing, and maintenance of embedded systems and safety/mission critical embedded software and firmware, that control various functions of X-ray generators. You are a part of Image Chain R&D under CT/AMI Business, located at Philips Healthcare Innovation Centre (HIC) Pune. You are responsible for : Requirements, design, implementation, test and integration of module/sub-system in accordance with the higher-level architectural requirements and design specifications Ensuring that the design is consistent with the higher-level architecture and requirements Ensuring that the proposed design would have the safety, reliability and quality features built-in Responsible for ensuring that the design meets the performance, quality and cost criteria Conduct concept and feasibility studies. Leads the introduction of new technologies Ensuring that there is proper documentation per standards for the developed design Ensuring the mutual consistency and efficient integration of the separate components in modular design that meets the product specification Ensuring that his design modules meet the product certification requirements Drawing up personal schedule and reports on progress Defining and assessing the Work Breakdown Structure/planning/costs of his/her area Being abreast of technical developments in own field through study of literature and technical contacts Mentoring/guiding/hand-holding young engineers in the team and helping them ramp-up well Maintaining product and company reputation by complying with country specific regulations To succeed in this role, you should have the following skills and experience: Completed engineering studies at University level; BE/BTech/ME/M-Tech in Electronics or Electrical Engineering, with 12 to 15 years of experience Experience in complete life-cycle management of embedded software, preferably for medical products Expert in C, C++ and other embedded programming languages Proficient in hardware description languages like VHDL, Verilog etc. Knowledge of Software Design Life Cycle (SDLC) Good knowledge of modern OS coding techniques, IP protocols and hardware interfaces Experience in 16/32-bit microcontroller-based design and programmable devices (FPGA/CPLD/SoC etc.) and their interface Knowledge of communication interfaces like RS232, RS485, CAN, EtherCAT, Ethernet and USB Hands-on experience in developing control software for close-loop systems. Hands-on experience in using simulation and implementation tools such as MATLAB and SIMULINK Excellent debugging skills - ability to understand and debug problems across hardware/software boundaries Experience in printed circuit board bring up and testing Knowledge of software tests and static code analyses Knowledge of firmware development environments such as IAR or Eclipse as well as version control systems like GIT Should have experience in DFMEA and design of Fail-Safe Systems and Sub Systems Knowledge of IEC 60601 standards will be an added advantage Knowledge of Global Medical Quality and Regulatory Standards e.g. IEC, FDA, UL, CE, CSA etc. Hands-on experience with tools like Agile, Clear-quest, Windchill or equivalent Disciplined team worker, ability to work independently Result oriented team player Ability to present and articulate ideas to key stakeholders and leadership team Excellent communication skills and Positive ‘can do’ attitude Quality mindset in design and documentation Global and Cross-functional Experience/Skills in a Matrix Organization will be an added advantage. How We Work Together We believe that we are better together than apart. For our office-based teams, this means working in-person at least 3 days per week. Onsite roles require full-time presence in the company’s facilities. Field roles are most effectively done outside of the company’s main facilities, generally at the customers’ or suppliers’ locations. Indicate if this role is an office/field/onsite role. About Philips We are a health technology company. We built our entire company around the belief that every human matters, and we won't stop until everybody everywhere has access to the quality healthcare that we all deserve. Do the work of your life to help the lives of others. Learn more about our business. Discover our rich and exciting history. Learn more about our purpose. If you’re interested in this role and have many, but not all, of the experiences needed, we encourage you to apply. You may still be the right candidate for this or other opportunities at Philips. Learn more about our culture of impact with care here.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SMTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD SOCs THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP/Sub-System/SOC level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Processor Micro-Architecture concepts – Reset/Boot-flow/Cache Coherency/Interrupt flows knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electronics/Electrical Engineering #LI-SR5 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Job Information Job Opening ID ZR_162_JOB Industry Semiconductor Date Opened 08/20/2025 Job Type Full time Work Experience 2-4 Years City Hyderabad State/Province Telangana Country India Zip/Postal Code 500081 Job Description FPGA Engineer | 2–4 yrs – TWO positions - Key Skills: ✅ Vivado /FPGA design flow hands-on ✅ Verilog proficiency ✅ Aptitude for FPGA IP development

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performan ce silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled engineer with 6-10 years of experience, passionate about developing cutting-edge emulation solutions for industry-stand ard protocols such as PCIe, CXL, and UCIe. You possess a strong background in software development using C/C++ and synthesizable RTL development with Verilog. Your deep understanding of digital design concepts, HDL languages, and scripting languages like Python or Perl will be invaluable in this role. You thrive in collaborative environments, have excellent communication skills, and are adept at solving complex problems. Your ability to interact with customers during deployment and debug processes will ensure successful implementation and satisfaction. A B.E/B.Tech/M.T ech in Electronic & Communication or Computer Science Engineering is essential. Knowledge of ARM architecture, UVM, and functional verification, along with experience in emulation, will be a significant advantage. What You’ll Be Doing: Developing emulation solutions for PCIe, CXL, and UCIe protocols for semiconductor customers. Engaging in software development using C/C++ and synthesizable RTL development with Verilog. Verifying solutions to ensure high performance and reliability. Interacting with customers during the deployment and debug phases to ensure smooth i mplementation. Collaborating with cross-function al teams to integrate emulation solutions. Maintaining and enhancing existing emulation solutions to meet evolving industry standards. The Impact You Will Have: Driving the development of advanced emulation solutions that meet industry standards. Enhancing the performance and reliability of semiconductor products through innovative solutions. Ensuring customer satisfaction by providing robust and efficient deployment support. Contributing to the continuous improvement of Synopsys' emulation technologies. Supporting the adoption of new protocols and standards in the semiconductor industry. Strengthening Synopsys' position as a leader in chip design and verification solutions. What You’ll Need: 5+ years of relevant experience In-depth knowledge of PCIe, CXL, and UCIe protocols. Proficiency in C/C++ programming and object-oriente d programming concepts. Strong understanding of digital design principles and HDL languages such as System Verilog and Verilog. Experience with scripting languages like Python, Perl, or TCL. Familiarity with ARM architecture and UVM/functional verification is a plus. Who You Are: A collaborative team player with excellent communication skills. A problem-solver with a keen eye for detail and a passion for innovation. Adaptable and able to work effectively in a fast-paced, dynamic environment. Customer-focus ed, with the ability to handle deployment and debugging challenges efficiently. Committed to continuous learning and staying updated with industry advancements. The Team You’ll Be A Part Of: You will be part of a dynamic team focused on developing and enhancing emulation solutions for cutting-edge semiconductor technologies. Our team collaborates closely with various departments to ensure the highest quality and performance of our products, driving innovation and excellence in the industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Industry: Electronics, Telecom & IT Skills: Coding and Debugging in C language FPGA RTL coding and Simulation using Verilog/VHDL Knowledge on ARM based architectures of 8/16/32 Microcontrollers , UART,ADC , DAC , Ethernet ,SPI,CAN,I2C and I2S 4 Yrs of Full Stack Development is required Development Life Cycle processes for embedded systems Preferable: Realization of Real Time Digital Signal Processing Realization of real time Digital Communications Desired profile of the candidate: Good communication and technical presentation skills, leadership abilities Experience Level: 3 to 5 years Qualification: BE/B.Tech (ECE), M.Sc (Electronics)

AI Centre Ethernet Switching Architect India-remote. person could be based anywhere in India - Remote work will be considered for exceptional profiles Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore AI Centre Ethernet Switching Architect Position Overview We are seeking a top-notch specialist Architect with over 15 years of experience to join our team in designing and developing Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet/TCP/IP protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, UALink, Ultra Ethernet with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Define and develop the architecture of AI Datacentre Switch Fabric from ground up Performance Modelling and optimization of latency, throughput and power efficiency of switch fabric Decompose the architecture into sub blocks for implementation by design team Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G/1600G), ECMP, and congestion control, packet spraying Apply knowledge of InfiniBand/Ultra Ethernet, NVLink/UALink, or similar protocols for feature implementation. Understanding/experience of IOS/Junos or equivalent software platform Use P4 or related languages for programmable packet processing. Working with design, software, verification team for complete product solutions Documentation of architecture and stay updated on AI networking trends. Required Qualifications Education: MS/PhD in Electrical/Electronic Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G/1600G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Soft Skills: Strong problem-solving, communication, and teamwork skills. Position Overview Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Role Overview As a Senior/Lead Design Verification Engineer , you will own verification strategy and execution for high-complexity IP and SoC designs. You will be responsible for planning, leading teams, defining testbench architecture, and ensuring coverage-driven closure. Key Responsibilities Define and drive the verification plan based on design specifications and functional requirements. Architect and develop reusable UVM/SystemVerilog-based testbenches. Own IP/SoC-level functional verification from test planning to coverage closure. Work closely with RTL, DFT, and firmware teams for seamless integration and debug. Guide and mentor junior engineers; conduct reviews and knowledge sessions. Contribute to verification methodology improvements and best practices. Perform regression setup, coverage analysis, and issue tracking. Deliver high-quality, first-time-right silicon. Required Skills Strong experience in SoC verification using SystemVerilog/UVM . Solid understanding of verification methodologies and simulation flows. Hands-on with tools like VCS, Questa, Verdi, SimVision, etc. Experience with standard bus protocols like MAC (Preferred), AXI, AHB, PCIe, USB, etc. Good debugging skills using waveform viewers and log analysis. Experience in writing assertions and functional coverage models. Knowledge of scripting (Python, Perl, TCL) is a plus. Strong communication and leadership abilities. Preferred Qualifications Experience with formal verification, assertion-based verification (SVA). Exposure to low-power verification and UPF flows. Familiarity with safety/security standards (e.g., ISO 26262, DO-254). Experience working with emulation platforms and FPGA prototyping. Location: Bangalore / Hyderabad / Pune Experience: 6-12 Years Notice Period: Immediate to 30 Days Company: ADV Logics Empowering Next-Gen VLSI Innovation

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled engineer with 6-10 years of experience, passionate about developing cutting-edge emulation solutions for industry-standard protocols such as PCIe, CXL, and UCIe. You possess a strong background in software development using C/C++ and synthesizable RTL development with Verilog. Your deep understanding of digital design concepts, HDL languages, and scripting languages like Python or Perl will be invaluable in this role. You thrive in collaborative environments, have excellent communication skills, and are adept at solving complex problems. Your ability to interact with customers during deployment and debug processes will ensure successful implementation and satisfaction. A B.E/B.Tech/M.Tech in Electronic & Communication or Computer Science Engineering is essential. Knowledge of ARM architecture, UVM, and functional verification, along with experience in emulation, will be a significant advantage. What You’ll Be Doing: Developing emulation solutions for PCIe, CXL, and UCIe protocols for semiconductor customers. Engaging in software development using C/C++ and synthesizable RTL development with Verilog. Verifying solutions to ensure high performance and reliability. Interacting with customers during the deployment and debug phases to ensure smooth implementation. Collaborating with cross-functional teams to integrate emulation solutions. Maintaining and enhancing existing emulation solutions to meet evolving industry standards. The Impact You Will Have: Driving the development of advanced emulation solutions that meet industry standards. Enhancing the performance and reliability of semiconductor products through innovative solutions. Ensuring customer satisfaction by providing robust and efficient deployment support. Contributing to the continuous improvement of Synopsys' emulation technologies. Supporting the adoption of new protocols and standards in the semiconductor industry. Strengthening Synopsys' position as a leader in chip design and verification solutions. What You’ll Need: 5+ years of relevant experience In-depth knowledge of PCIe, CXL, and UCIe protocols. Proficiency in C/C++ programming and object-oriented programming concepts. Strong understanding of digital design principles and HDL languages such as System Verilog and Verilog. Experience with scripting languages like Python, Perl, or TCL. Familiarity with ARM architecture and UVM/functional verification is a plus. Who You Are: A collaborative team player with excellent communication skills. A problem-solver with a keen eye for detail and a passion for innovation. Adaptable and able to work effectively in a fast-paced, dynamic environment. Customer-focused, with the ability to handle deployment and debugging challenges efficiently. Committed to continuous learning and staying updated with industry advancements. The Team You’ll Be A Part Of: You will be part of a dynamic team focused on developing and enhancing emulation solutions for cutting-edge semiconductor technologies. Our team collaborates closely with various departments to ensure the highest quality and performance of our products, driving innovation and excellence in the industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

www.omnidesigntech.com Senior SoC Director / Senior Principal Engineer Bangalore / Hyderabad About Omni Design Technologies Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated system-on-chip (SoC), in applications ranging from 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the internet-of-things (IoT). Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few MSPS to more than 100 GSPS sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins-Colorado, Bangalore-India, Hyderabad-India, Dublin-Ireland, Boston-Massachusetts. Bangalore Engineering – Digital Circuit Design / Hyderabad / Bangalore SOC Development – Engineering / Full-time / Hybrid Omni Design is working on exciting solutions and chips for next generation automotive and space applications and looking for talented and capable engineers. The Director of digital and mixed-signal engineering will be responsible for development of mixed-signal SOC being developed at ODT and build the digital engineering team and will work Analog/RF engineering, FW engineering, verification, Systems Validation team, Operations, SOC Architects, and report to the VP / SVP of ASIC Engineering. Nice to have experience in UCIE PCIE Gen5/Gen6/Gen7 Roles and Responsibilities Manage digital team, hire, and retain best talent Lead SOC integration design team to develop and productize next generation mixed-signal RF/communication SOCs Work with cross-functional project teams to define product specifications, system architecture, HW/SW partitioning, and execution plan Implement best SoC development practices and improve design methodology to maximize efficiency and predictability Deliver chip architecture, design, integration, programming model, verification, and manage hand-off to backend Support Silicon and System Validation, support system integration, and production testing Drive innovation and provides leadership to the organization to ensure world-class system solutions and flawless execution Qualifications BSEE Required, MSEE Preferred Proven track record of success in high-performance/high-volume semiconductor industry SoC, embedded CPU and bus architectures, networking, and control interfaces Communications / DSP algorithms and power / area efficient implementations Digital IC design, design for low power and high speed, design for test (DFT) System modeling, RTL coding, Lint / CDC checking, simulation, synthesis, power analysis, timing analysis in Cadence / Synopsys design environments Directed and constrained random verification, UVM methodology Embedded systems FPGA emulation, lab debug and chip validation Project planning and execution, and performing design tradeoffs to achieve performance, power, die size, and schedule targets Self-motivated, excellent communication skills, and ability to excel and to provide leadership in a fast-paced environment Senior Management experience preferred Work with architecture, physical design, and design teams to lead the implementation of the digital architecture. Develop and refine specification of the micro-architecture for the digital architecture. Is in tune with industry trends and contributes to consistent roadmap decisions. Experience 12-25+ years of experience in the area of RTL design and verification of silicon At Least 3+ years experience in leading low-power mixed-Signal SOC design 10+ years of experience with FPGA architecture specification and design (Altera or Xilinx) for high-speed serial protocols, including USB-SS, PCIe, SATA/SAS, DisplayPort Experience in leading, specifying, and work with Analog/RF team in developing, verifying, and productizing SERDES, CDR, and PLL/DLL designs Experience with USB 3.0, DisplayPort, PCIe, or SATA based silicon designs preferred Strong background in analog/mixed-signal integrated SOC Development Strong Hardware design knowledge and familiarity with signal integrity Strong foundation in SoC architecture, design, verification and physical implementation Strong analytical problem solving, and attention to details Knowledge of wireless, mobile, and storage domains Expertise in Verilog/System Verilog, C/C++/SystemC, UVM, Scripting languages like Perl/Python, etc. Excellent technical documentation skills Excellent written and verbal communication skills Excellent interpersonal skills, self-motivated, self-starter Experience in startup environment Expectations Put the RTL for the Full chip together. Evaluate the IP we have to license – like PCIe, LPDDR4, JESD 204C PHY Help develop any BIST Work with Verification Team to develop the FC Simulation test suites Develop the RTL for the various state machines and interfaces Run a few of the simulations Help with the FC simulations debug Help close the timing issues if any come up and work with the PD person to resolve any SI issues. Be a mentor and lead a team of Digital design engineers Work with Systems and Test engineering team to help validate the parts and release them to production We are looking for trailblazers ... We strongly believe that the pace of the ongoing hardware revolution will be greatly accelerated by Design’s IP cores and the rapidly emerging semiconductor embedded design business ecosystem. we have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring our vision to fruition. If you are interested in making an impact as part of a young, fast growing, cutting edge technology company, please reach out to us. We are a equal opportunity employer. We offer excellent compensation. We seek individuals that share our high standards and commitment to excellence. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com 'Mining The Knowledge Community'

Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams. Analyze and implement System Verilog assertions and coverage (code, toggle, functional). Provide mentorship and technical guidance to junior verification engineers.Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment. Ensure verification signoff criteria are met and documentation is comprehensive.Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines. Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies. Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence. Qualifications Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. ORMasters degree in computer science, Electrical/Electronics Engineering, or related field. ORPhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design Verification. Expertise in UVM (Universal Verification Methodology) and System Verilog. Prior experience working on IP level and SOC level verification projects. Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs). Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols. Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF. Proficiency in scripting languages such as shell, Makefile, and Perl. Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment. C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.

Role Description: A highly skilled VLSI Frontend Design Engineer with hands-on experience in architecting and developing complex SoCs from scratch. Exp: 8+ years Location: Trivandrum. Experience: 8–10 years in VLSI Frontend & RTL Design, with at least one complete end-to-end SoC development ownership. Strong RTL Design Expertise: Verilog, SystemVerilog, VHDL. Micro-architecture Design: Experience defining and implementing high-performance compute or control-intensive SoC subsystems. Interface & Protocol Knowledge: AMBA (AXI/AHB/APB), PCIe, DDR, USB, MIPI, I2C/SPI, Ethernet, etc. EDA Tools: Synopsys/Cadence/Siemens front-end tools (Design Compiler, Spyglass, VCS, Incisive, etc.). Power-aware Design Techniques: Clock gating, multi-Vt, UPF/CPF based design. Good understanding of DFT, CDC, Linting, Synthesis constraints , timing closure. Exposure to RISC-V/ARM architecture , cache design, coherency protocols, and IO subsystems. Strong documentation skills, design reviews, and collaboration in cross-functional teams. Experience with AI/ML accelerators , Automotive/ADAS SoCs, or high-speed SerDes. (Good to have) Knowledge of High-Level Synthesis (HLS) flows and SystemC modeling. Familiarity with firmware/embedded software and driver bring-up. Educational Qualification: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, VLSI, or equivalent from a reputed institute.

Job Information Job Opening ID ZR_162_JOB Industry Semiconductor Date Opened 08/20/2025 Job Type Full time Work Experience 2-4 Years City Hyderabad State/Province Telangana Country India Zip/Postal Code 500081 Job Description FPGA Engineer | 2–4 yrs – TWO positions - Key Skills: ✅ Vivado /FPGA design flow hands-on ✅ Verilog proficiency ✅ Aptitude for FPGA IP development

Job Description Develop and execute AMS verification plans for mixed-signal IP and SoCs. Create and validate behavioral models using Verilog-A for analog and mixed-signal blocks. Implement and optimize AMS testbenches in the Xcelium simulation environment. Collaborate with analog and digital designers to verify top-level integration and system performance. Debug and resolve complex AMS simulation and modeling issues. Drive and contribute to the development of AMS verification methodologies and best practices. Perform regression testing and coverage analysis to ensure design robustness. Document verification plans, results, and technical reports. (ref:hirist.tech)

Emulation Engineer with Zebu experience- digital systems RTL code for IP, sub-systems, and SoCs. hardware description languages (HDLs) such as Verilog or system Verilog Experience in building emulation model builds Email id - ta6@nippondata.com