2736 Verilog Jobs - Page 10

As a Senior Director of Digital Design for New Product Development in Power Management at OnSemi in Bengaluru, India, you will be responsible for working on the development of power management products such as DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches, and efuses for consumer, industrial, and automotive applications. Your role will involve collaborating with various product lines for RTL implementation of power converter controller design, digital design architecture, low power design, synthesis, timing analysis, and physical design interface for power management chips. You will work as part of a large team of engineers and collaborate with design architects, digital verification, project management, and digital/analog design teams globally. Your responsibilities will include implementing micro-architecture to RTL implementation, supporting the bring-up of features in pre-silicon platforms, owning the technical outcome of design, verification, and implementation of Power Management ICs, understanding project goals, leading and supporting customer issues, production issues, FW and system development, and supporting post-silicon validation activities. To qualify for this position, you should have a BS/MS in Electrical Engineering or a related field with 18/20 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. The ideal candidate should have a thorough understanding of the end-to-end digital design flow, RTL design, CDC, ASIC synthesis, timing analysis, P&R, UPF, system Verilog, Verilog, TCL, and Perl/Python/XML programming languages. OnSemi, a company focused on automotive and industrial end-markets, is committed to driving disruptive innovations in megatrends such as vehicle electrification, safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a portfolio of intelligent power and sensing technologies, OnSemi aims to create a safer, cleaner, and smarter world. If you are a high-performance innovator looking to join a dynamic team in a forward-thinking company, OnSemi offers a positive recruitment experience and attractive company benefits. More details about the benefits can be found here: [OnSemi Career Benefits](https://www.onsemi.com/careers/career-benefits).,

Qualcomm India Private Limited is seeking a talented individual to join their Wireless IP team for the role of designing and developing cutting-edge RTL for next-generation cellular and Wi-Fi modem IPs used in mobile, wearable, and IoT platforms. In this role, you will be responsible for working on high-performance, low-power digital designs throughout the full VLSI development cycle, from architecture and micro-architecture to RTL implementation and SoC integration. You will have the opportunity to collaborate with global teams and contribute to market-leading wireless solutions. Your key responsibilities will include designing and implementing RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog, developing micro-architecture specifications, integrating complex subsystems into SoC environments, collaborating with various teams such as system architects, verification, SoC, software, DFT, and physical design teams, applying low-power design techniques, analyzing and optimizing for performance, area, and power, ensuring protocol compliance and performance of interconnects, conducting CDC and lint checks, and participating in post-silicon debug and bring-up activities. Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering experience, or - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 1+ year of Hardware Engineering experience, or - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. - Minimum qualification of a Bachelors or Masters degree in Electronics, VLSI, Communications, or related field with proven experience in RTL design and SoC development. Preferred Skills & Experience: - 2-5 years of experience in digital front-end ASIC/RTL design. - Strong expertise in Verilog/SystemVerilog RTL coding and micro-architecture development. - Familiarity with wireless protocols such as IEEE 802.11, LTE, or 5G NR is highly desirable. - Solid understanding of bus protocols and bridge logic. - Experience with wireless modem IPs or similar high-performance digital blocks is a plus. - Familiarity with low-power design methodologies and CDC handling. - Hands-on experience with tools like Spyglass, 0-in, Design Compiler, PrimeTime, and simulation environments. - Exposure to post-silicon debug and SoC integration challenges. - Strong documentation and communication skills. - Self-motivated with a collaborative mindset and ability to work with minimal supervision. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations to individuals with disabilities during the application/hiring process. For more information about this role, please contact Qualcomm Careers.,

Boltchip is a Talent Transformation company based in Singapore. One of our global client is building their Design teams in India. We are building their entire capability for ASIA. Role : Senior Design Engineer Location : Ahmedabad Qualification (s) – BE / BTech / MTech / MS / PhD Domain - Electronics, Electrical, Computer Engineering or Computer Science Engineering Experience – 7+ years We are looking for a highly skilled and experienced Design Verification Engineer to join our team. This role is ideal for someone who brings deep technical expertise in verification along with a strong grasp of industry protocols and low-power design techniques. You'll work on advanced IP and SoC subsystems involving both RISC-V and ARM-based architecture, and collaborate closely with our architecture, design, and validation teams. What You'll Do: · Own and drive the full verification cycle for IP blocks and subsystems · Create detailed verification plans, identify test items, and track coverage · Build UVM-based test benches from scratch, including drivers, monitors, and scoreboards · Perform low power verification using both UPF and Native Low Power (NLP) methods · Develop and run UVM-based test environments for Ethernet and other protocol interfaces · Integrate and work with third-party Verification IPs (VIPs) · Write and debug assertions and functional coverage models · Collaborate with design and architecture teams to close verification cycles efficiently · Support silicon bring-up and post-silicon debug when required · Mentor junior team members on verification techniques and best practices Key Skills We Are Looking For: · UPF / Low Power Verification (UVM expert) · Strong understanding of low-power concepts in ASIC design (UPF/NLP) from a verification perspective · UVM with Ethernet protocol expertise · NLP Test bench Verification with Native Low Power (UVM expert) · Strong command over System Verilog , Verilog , and UVM methodology · Solid understanding of ASIC design flows and power-aware design concepts · Experience with protocols like PCIe, AXI, CHI, Ethernet, USB, NVMe, DDR, and CXL · Good working knowledge of System Verilog Assertions (SVA) and formal verification techniques · Hands-on experience with scripting ( Python, Perl, Shell, TCL ) · Comfortable working in Linux development environments · Excellent debugging, problem-solving, and analytical thinking · Strong communication and collaboration skills Qualifications: · Bachelor’s degree in Electrical Engineering, Electronics and Communications Engineering, Computer Engineering, Computer Science, or related fields · Fluent in both written and spoken English · Excellent collaborative skills · Highly motivated and self-driven individual · Strong coding and object-oriented programming skills · Excellent debugging, problem solving, and analytical skills · Knowledgeable in digital design · Minimum 7 years of industry experience in Design Verification roles. · A track record of successfully verifying complex IP blocks or subsystems from spec to silicon. Please forward your resume to jasmine.h@boltchip.com

Introduction IBM Infrastructure division builds Servers, Storage, Systems and Cloud Software which are the building blocks for next-generation IT infrastructure of enterprise customers and data centers. IBM Servers provide best-in-class reliability, scalability, performance, and end-to-end security to handle mission-critical workloads and provide seamless extension to hybrid multicloud environments. India Systems Development Lab (ISDL) is part of word-wide IBM Infrastructure division. Established in 1996, the ISDL Lab is headquartered in Bengaluru, with presence in Pune and Hyderabad as well. ISDL teams work across the IBM Systems stack including Processor development (Power and IBM Z), ASCIs, Firmware, Operating Systems, Systems Software, Storage Software, Cloud Software, Performance & Security Engineering, System Test etc. The lab also focuses on innovations, thanks to the creative energies of the teams. The lab has contributed over 400+ patents in cutting edge technologies and inventions so far. ISDL teams also ushered in new development models such as Agile, Design Thinking and DevOps. Your Role And Responsibilities As a Software Engineer at IBM India Systems Development Lab (IBM ISDL), you will get an opportunity to work on all the phases of product development (Design/Development, Test and Support) across core Systems technologies including Operating Systems, Firmware, Systems Software, Storage Software & Cloud Software. As a Software Developer At ISDL: You will be focused on development of IBM Systems products interfacing with development & product management teams and end users, cutting across geos. You would analyze product requirements, determine the best course of design, implement/code the solution and test across the entire product development life cycle. One could also work on Validation and Support of IBM Systems products. You get to work with a vibrant, culture driven and technically accomplished teams working to create world-class products and deployment environments, delivering an industry leading user experience for our customers. You will be valued for your contributions in a growing organization with broader opportunities. At ISDL, work is more than a job - it's a calling: To build. To design. To code. To invent. To collaborate. To think along with clients. To make new products/markets. Not just to do something better, but to attempt things you've never thought was possible. Are you ready to lead in this new era of technology and solve some of the most challenging problems in Systems Software technologies? If so, let’s talk. Required Technical And Professional Expertise Required Technical Expertise: Knowledge of Operating Systems, OpenStack, Kubernetes, Container technologies, Cloud concepts, Security, Virtualization Management, REST API, DevOps (Continuous Integration) and Microservice Architecture. Strong programming skills in C, C++, Go Lang, Python, Ansible, Shell Scripting. Comfortable in working with Github and leveraging Open source tools. AI Software Engineer: As a Software Engineer with IBM AI on Z Solutions teams, you will get the opportunity to get involved in delivering best-in class Enterprise AI Solutions on IBM Z and support IBM Customers while adopting AI technologies / Solutions into their businesses by building ethical, secure, trustworthy and sustainable AI solutions on IBM Z. You will be part of end to end solutions working along with technically accomplished teams. You will be working as a Full stack developer starting from understanding client challenges to providing solutions using AI. Required Technical Expertise: Knowledge of AI/ML/DL, Jupyter Notebooks, Linux Systems, Kubernetes, Container technologies, REST API, UI skills, Strong programming skills like – C, C++, R, Python, Go Lang and well versed with Linux platform. Strong understanding of Data Science, modern tools and techniques to derive meaningful insights Understanding of Machine learning (ML) frameworks like scikit- learn, XGBoost etc. Understanding of Deep Learning (DL) Frameworks like Tensorflow, PyTorch Understanding of Deep Learning Compilers (DLC) Natural Language Processing (NLP) skills Understanding of different CPU architectures (little endian, big endian). Familiar with open source databases PostGreSQL, MongoDB, CouchDB, CockroachDB, Redis, data sources, connectors, data preparations, data flows, Integrate, cleanse and shape data. IBM Storage Engineer: As a Storage Engineer Intern in a Storage Development Lab you would support the design, testing, and validation of storage solutions used in enterprise or consumer products. This role involves working closely with hardware and software development teams to evaluate storage performance, ensure data integrity, and assist in building prototypes and test environments. The engineer contributes to the development lifecycle by configuring storage systems, automating test setups, and analyzing system behavior under various workloads. This position is ideal for individuals with a foundational understanding of storage technologies and a passion for hands-on experimentation and product innovation. Preferred Technical Expertise: Practical working experience with Java, Python, GoLang, ReactJS, Knowledge of AI/ML/DL, Jupyter Notebooks, Storage Systems, Kubernetes, Container technologies, REST API, UI skills, Exposure to cloud computing technologies such as Red Hat OpenShift, Microservices Architecture, Kubernetes/Docker Deployment. Basic understanding of storage technologies: SAN, NAS, DAS Familiarity with RAID levels and disk configurations Knowledge of file systems (e.g., NTFS, ext4, ZFS) Experience with operating systems: Windows Server, Linux/Unix Basic networking concepts: TCP/IP, DNS, DHCP Scripting skills: Bash, PowerShell, or Python (for automation) Understanding of backup and recovery tools (e.g., Veeam, Commvault) Exposure to cloud storage: AWS S3, Azure Blob, or Google Cloud Storage Linux Developer: As a Linux developer, you would be involved in design and development of advanced features in the Linux OS for the next generation server platforms from IBM by collaboration with the Linux community. You collaborate with teams across the hardware, firmware, and upstream Linux kernel community to deliver these capabilities. Preferred Technical Expertise Excellent knowledge of the C programming language Knowledge of Linux Kernel internals and implementation principles. In-depth understanding of operating systems concepts, data structures, processor architecture, and virtualization Experience with working on open-source software using tools such git and associated community participation processes. Hardware Management Console (HMC) / Novalink Software Developer: As a Software Developer in HMC / Novalink team, you will work on design, development, and test of the Management Console for IBM Power Servers. You will be involved in user centric Graphical User Interface development and Backend for server and virtualization management solution development in Agile environment. Preferred Technical Expertise Strong Programming skills in in Core Java 8, C/C++ Web development skills in JavaScript (Frameworks such as Angular.js, React.js etc),, HTML, CSS and related technologies Experience in developing rich HTML applications Web UI Frameworks: Vaadin, React JS and UI styling libraries like Bootstrap/Material Knowledge of J2EE, JSP, RESTful web services and GraphQL API AIX Developer: AIX is a proprietary Unix operating system which runs on IBM Power Servers. It’s a secure, scalable, and robust open standards-based UNIX operating system which is designed to meet the needs of Enterprises class infrastructure. As an AIX developer, you would be involved in development, test or support of AIX OS features development or open source software porting/development for AIX OS Preferred Technical Expertise Strong Expertise in Systems Programming Skills (C, C++) Strong knowledge of operating systems concepts, data structures, algorithms Strong knowledge of Unix/Linux internals (Signals, IPC, Shared Memory,..etc) Expertise in developing/handling multi-threaded Applications. Good knowledge in any of the following areas User Space Applications File Systems, Volume Management Device Drivers Unix Networking, Security Container Technologies Linkers/Loaders Virtualization High Availability & clustering products Strong debugging and Problem-Solving skills Performance Engineer: As a performance Engineer , you will get an opportunity to conduct experiments and analysis to identify performance aspects for operating systems and Enterprise Servers. where you will be responsible for advancing the product roadmap by using your expertise in Linux operating system, building kernel , applying patches, performance characterization, optimization and hardware architecture to analyse performance of software/hardware combinations. You will be involved in conducting experiments and analysis to identify performance challenges and uncover optimization opportunities for IBM Power virtualization and cloud management software built on Open stack. The areas of work will be on characterization, analysis and fine-tune application software to help deliver optimal performance on IBM Power. Preferred Technical Expertise Experience in C/C++ programming Knowledge of Hypervisor, Virtualization concepts Good understanding of system HW , Operating System , Systems Architecture Strong skills in scripting Good problem solving, strong analytical and logical reasoning skills Familiar with server performance management and capacity planning Familiar with performance diagnostic methods and techniques Firmware Engineer: As a Firmware developer you will be responsible for designing and developing components and features independently in IBM India Systems Development Lab. ISDL works on end-to-end design, development across Power, Z and Storage portfolio. You would be a part of WW Firmware development organization and would be involved in designing & developing cutting edge features on the open source OpenBMC stack (https://github.com/openbmc/) and developing the open source embedded firmware code for bringing up the next generation enterprise Power, Z and LinuxONE Servers. You will get an opportunity work alongside with some of the best minds in the industry, forum and communities in the process of contributing to the portfolio. Preferred Technical Expertise Strong System Architecture knowledge Hands on programming skills with C, C++ , C on Linux Distros. Experience/exposure in Firmware/Embedded software design & development, Strong knowledge of Linux OS and Open Source development Experience with Open Source tools & scripting languages: Git, Gerrit, Jenkins, perl/python Other Skills (Common For All The Positions): Strong Communication, analytical, interpersonal & problem solving skills Ability to deliver on agreed goals and the ability to coordinate activities in the team/collaborate with others to deliver on the team vision. Ability to work effectively in a global team environment Enterprise System Design Software Engineer: The Enterprise Systems Design team is keen on hiring passionate Computer science and engineering graduates / Masters students, who can blend their architectural knowledge and programming skills to build the complex infrastructure geared to work for the Hybrid cloud and AI workloads. We have several opportunities in following areas of System & chip development team : Processor verification engineer Needs to develop the test infrastructure to verify the architecture and functionality of the IBM server processors/SOC or ASICs. Will be responsible to creatively think of all the scenarios to test and report the coverage. Work with design as well as other key stakeholders in identifying /debugging & Resolving logic design issues and deliver a quality design Processor Pre / Post silicon validation engineer As a validation engineer you would design and develop algorithms for Post Silicon Validation of next generation IBM server processors, SOCs and ASICs. Electronic design automation – Front & BE tool development. EDA tools development team is responsible for developing state of the art Front End verification , simulation , Formal verification tools , Place & Route, synthesis tools and Flows critical for designing & verifying high performance hardware design for IBM's next generation Systems (IBM P and Z Systems) which is used in Cognitive, ML, DL, and Data Center applications. Required Professional And Technical Skills: Functional Verification / Validation of Processors or ASICs. Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Strong C/C++programming skills in a Unix/Linux environment required Great scripting skills – Perl / Python/Shell Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow. Understand Verilog / VHDL , verification coverage closure Proven problem-solving skills and the ability to work in a team environment are a must

Introduction IBM Infrastructure division builds Servers, Storage, Systems and Cloud Software which are the building blocks for next-generation IT infrastructure of enterprise customers and data centers. IBM Servers provide best-in-class reliability, scalability, performance, and end-to-end security to handle mission-critical workloads and provide seamless extension to hybrid multicloud environments. India Systems Development Lab (ISDL) is part of word-wide IBM Infrastructure division. Established in 1996, the ISDL Lab is headquartered in Bengaluru, with presence in Pune and Hyderabad as well. ISDL teams work across the IBM Systems stack including Processor development (Power and IBM Z), ASCIs, Firmware, Operating Systems, Systems Software, Storage Software, Cloud Software, Performance & Security Engineering, System Test etc. The lab also focuses on innovations, thanks to the creative energies of the teams. The lab has contributed over 400+ patents in cutting edge technologies and inventions so far. ISDL teams also ushered in new development models such as Agile, Design Thinking and DevOps. Your Role And Responsibilities As a Software Engineer at IBM India Systems Development Lab (IBM ISDL), you will get an opportunity to work on all the phases of product development (Design/Development, Test and Support) across core Systems technologies including Operating Systems, Firmware, Systems Software, Storage Software & Cloud Software. As a Software Developer At ISDL: You will be focused on development of IBM Systems products interfacing with development & product management teams and end users, cutting across geos. You would analyze product requirements, determine the best course of design, implement/code the solution and test across the entire product development life cycle. One could also work on Validation and Support of IBM Systems products. You get to work with a vibrant, culture driven and technically accomplished teams working to create world-class products and deployment environments, delivering an industry leading user experience for our customers. You will be valued for your contributions in a growing organization with broader opportunities. At ISDL, work is more than a job - it's a calling: To build. To design. To code. To invent. To collaborate. To think along with clients. To make new products/markets. Not just to do something better, but to attempt things you've never thought was possible. Are you ready to lead in this new era of technology and solve some of the most challenging problems in Systems Software technologies? If so, let’s talk. Required Technical And Professional Expertise Required Technical Expertise: Knowledge of Operating Systems, OpenStack, Kubernetes, Container technologies, Cloud concepts, Security, Virtualization Management, REST API, DevOps (Continuous Integration) and Microservice Architecture. Strong programming skills in C, C++, Go Lang, Python, Ansible, Shell Scripting. Comfortable in working with Github and leveraging Open source tools. AI Software Engineer: As a Software Engineer with IBM AI on Z Solutions teams, you will get the opportunity to get involved in delivering best-in class Enterprise AI Solutions on IBM Z and support IBM Customers while adopting AI technologies / Solutions into their businesses by building ethical, secure, trustworthy and sustainable AI solutions on IBM Z. You will be part of end to end solutions working along with technically accomplished teams. You will be working as a Full stack developer starting from understanding client challenges to providing solutions using AI. Required Technical Expertise: Knowledge of AI/ML/DL, Jupyter Notebooks, Linux Systems, Kubernetes, Container technologies, REST API, UI skills, Strong programming skills like – C, C++, R, Python, Go Lang and well versed with Linux platform. Strong understanding of Data Science, modern tools and techniques to derive meaningful insights Understanding of Machine learning (ML) frameworks like scikit- learn, XGBoost etc. Understanding of Deep Learning (DL) Frameworks like Tensorflow, PyTorch Understanding of Deep Learning Compilers (DLC) Natural Language Processing (NLP) skills Understanding of different CPU architectures (little endian, big endian). Familiar with open source databases PostGreSQL, MongoDB, CouchDB, CockroachDB, Redis, data sources, connectors, data preparations, data flows, Integrate, cleanse and shape data. IBM Storage Engineer: As a Storage Engineer Intern in a Storage Development Lab you would support the design, testing, and validation of storage solutions used in enterprise or consumer products. This role involves working closely with hardware and software development teams to evaluate storage performance, ensure data integrity, and assist in building prototypes and test environments. The engineer contributes to the development lifecycle by configuring storage systems, automating test setups, and analyzing system behavior under various workloads. This position is ideal for individuals with a foundational understanding of storage technologies and a passion for hands-on experimentation and product innovation. Preferred Technical Expertise: Practical working experience with Java, Python, GoLang, ReactJS, Knowledge of AI/ML/DL, Jupyter Notebooks, Storage Systems, Kubernetes, Container technologies, REST API, UI skills, Exposure to cloud computing technologies such as Red Hat OpenShift, Microservices Architecture, Kubernetes/Docker Deployment. Basic understanding of storage technologies: SAN, NAS, DAS Familiarity with RAID levels and disk configurations Knowledge of file systems (e.g., NTFS, ext4, ZFS) Experience with operating systems: Windows Server, Linux/Unix Basic networking concepts: TCP/IP, DNS, DHCP Scripting skills: Bash, PowerShell, or Python (for automation) Understanding of backup and recovery tools (e.g., Veeam, Commvault) Exposure to cloud storage: AWS S3, Azure Blob, or Google Cloud Storage Linux Developer: As a Linux developer, you would be involved in design and development of advanced features in the Linux OS for the next generation server platforms from IBM by collaboration with the Linux community. You collaborate with teams across the hardware, firmware, and upstream Linux kernel community to deliver these capabilities. Preferred Technical Expertise Excellent knowledge of the C programming language Knowledge of Linux Kernel internals and implementation principles. In-depth understanding of operating systems concepts, data structures, processor architecture, and virtualization Experience with working on open-source software using tools such git and associated community participation processes. Hardware Management Console (HMC) / Novalink Software Developer: As a Software Developer in HMC / Novalink team, you will work on design, development, and test of the Management Console for IBM Power Servers. You will be involved in user centric Graphical User Interface development and Backend for server and virtualization management solution development in Agile environment. Preferred Technical Expertise Strong Programming skills in in Core Java 8, C/C++ Web development skills in JavaScript (Frameworks such as Angular.js, React.js etc),, HTML, CSS and related technologies Experience in developing rich HTML applications Web UI Frameworks: Vaadin, React JS and UI styling libraries like Bootstrap/Material Knowledge of J2EE, JSP, RESTful web services and GraphQL API AIX Developer: AIX is a proprietary Unix operating system which runs on IBM Power Servers. It’s a secure, scalable, and robust open standards-based UNIX operating system which is designed to meet the needs of Enterprises class infrastructure. As an AIX developer, you would be involved in development, test or support of AIX OS features development or open source software porting/development for AIX OS Preferred Technical Expertise Strong Expertise in Systems Programming Skills (C, C++) Strong knowledge of operating systems concepts, data structures, algorithms Strong knowledge of Unix/Linux internals (Signals, IPC, Shared Memory,..etc) Expertise in developing/handling multi-threaded Applications. Good knowledge in any of the following areas User Space Applications File Systems, Volume Management Device Drivers Unix Networking, Security Container Technologies Linkers/Loaders Virtualization High Availability & clustering products Strong debugging and Problem-Solving skills Performance Engineer: As a performance Engineer , you will get an opportunity to conduct experiments and analysis to identify performance aspects for operating systems and Enterprise Servers. where you will be responsible for advancing the product roadmap by using your expertise in Linux operating system, building kernel , applying patches, performance characterization, optimization and hardware architecture to analyse performance of software/hardware combinations. You will be involved in conducting experiments and analysis to identify performance challenges and uncover optimization opportunities for IBM Power virtualization and cloud management software built on Open stack. The areas of work will be on characterization, analysis and fine-tune application software to help deliver optimal performance on IBM Power. Preferred Technical Expertise Experience in C/C++ programming Knowledge of Hypervisor, Virtualization concepts Good understanding of system HW , Operating System , Systems Architecture Strong skills in scripting Good problem solving, strong analytical and logical reasoning skills Familiar with server performance management and capacity planning Familiar with performance diagnostic methods and techniques Firmware Engineer: As a Firmware developer you will be responsible for designing and developing components and features independently in IBM India Systems Development Lab. ISDL works on end-to-end design, development across Power, Z and Storage portfolio. You would be a part of WW Firmware development organization and would be involved in designing & developing cutting edge features on the open source OpenBMC stack (https://github.com/openbmc/) and developing the open source embedded firmware code for bringing up the next generation enterprise Power, Z and LinuxONE Servers. You will get an opportunity work alongside with some of the best minds in the industry, forum and communities in the process of contributing to the portfolio. Preferred Technical Expertise Strong System Architecture knowledge Hands on programming skills with C, C++ , C on Linux Distros. Experience/exposure in Firmware/Embedded software design & development, Strong knowledge of Linux OS and Open Source development Experience with Open Source tools & scripting languages: Git, Gerrit, Jenkins, perl/python Other Skills (Common For All The Positions): Strong Communication, analytical, interpersonal & problem solving skills Ability to deliver on agreed goals and the ability to coordinate activities in the team/collaborate with others to deliver on the team vision. Ability to work effectively in a global team environment Enterprise System Design Software Engineer: The Enterprise Systems Design team is keen on hiring passionate Computer science and engineering graduates / Masters students, who can blend their architectural knowledge and programming skills to build the complex infrastructure geared to work for the Hybrid cloud and AI workloads. We have several opportunities in following areas of System & chip development team : Processor verification engineer Needs to develop the test infrastructure to verify the architecture and functionality of the IBM server processors/SOC or ASICs. Will be responsible to creatively think of all the scenarios to test and report the coverage. Work with design as well as other key stakeholders in identifying /debugging & Resolving logic design issues and deliver a quality design Processor Pre / Post silicon validation engineer As a validation engineer you would design and develop algorithms for Post Silicon Validation of next generation IBM server processors, SOCs and ASICs. Electronic design automation – Front & BE tool development. EDA tools development team is responsible for developing state of the art Front End verification , simulation , Formal verification tools , Place & Route, synthesis tools and Flows critical for designing & verifying high performance hardware design for IBM's next generation Systems (IBM P and Z Systems) which is used in Cognitive, ML, DL, and Data Center applications. Required Professional And Technical Skills: Functional Verification / Validation of Processors or ASICs. Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Strong C/C++programming skills in a Unix/Linux environment required Great scripting skills – Perl / Python/Shell Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow. Understand Verilog / VHDL , verification coverage closure Proven problem-solving skills and the ability to work in a team environment are a must

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills Lattice is seeking candidates for the position of Sr EDA SW Dev Engineer. This is a full-time position located in Pune, India. Accountabilities Develop and deliver state-of-art Lattice FPGA software tool for small, mid-range and large FPGA products. Develop software capabilities for next generation of Lattice FPGA products. Support and maintain existing Lattice FPGA design and debug tools. Learn and contribute to Spec and Plan process - review marketing requirement documents, generate functional specifications and developer unit test plans to ensure quality software. Improve development methodologies and processes. Qualifications BS/MS/PhD Electrical Engineering or Computer Science 5+ years of experience in large-scale software development for engineering application domains, preferably in FPGA/ASIC Design Automation Must be proficient with C++. Modern C++ proficiency is a plus Familiarity with Verilog/VHDL Strong background in Software Architecture, object-oriented programming, data structures and algorithms, Design Patterns Experience of working on multiple platforms – at least Linux and Windows – is required. Knowledge of shell, Tcl or Python scripting is a plus. Familiarity with commercial FPGA software tools and design flow is a plus. Knowledge in FPGA logic design is a plus. Must be detail oriented and possess independent problem-solving skills. Must be able to drive projects and lead a discussion. Strong written and verbal communication skills, and collaboration skill with the ability to work with multiple groups.

Employment Type: Full-time Job Profile: We are looking for a skilled and experienced Digital Circuit Design Engineer to lead the design, development, and validation of high-performance digital systems. The ideal candidate will have expertise in digital logic design, proficiency with HDL languages and FPGA tools , and a strong grasp of embedded systems integration. Key Responsibilities: Design and implement complex digital circuits including logic gates, finite state machines, and both synchronous and asynchronous architectures. Use industry-standard tools (e.g., Verilog, VHDL, FPGA development environments) for simulation, synthesis, and verification. Integrate digital designs with communication and memory protocols such as PCIe, DDR, UART, USB, and SPI. Conduct thorough testing, debugging, and optimization of digital systems. Collaborate with firmware and embedded software teams using C/C++ or Python for system-level integration. Education: B.Tech/M.Tech in ECE/Embedded Systems/Digital Electronics. Minimum 3 years of experience.

Mandate - Required Skillset RTL Verification Experience: 4–10 years of hands-on experience verifying RTL designs for digital systems or SoCs. Simulation Tools Proficiency: Expertise in using industry-standard verification tools such as ModelSim, Cadence Incisive, and Synopsys VCS. Testbench Development: Proficient at developing and maintaining verification environments and testbenches using SystemVerilog, UVM, Verilog, or VHDL. Functional Verification: Strong background in functional verification, writing test plans, creating test cases, debugging failures, and ensuring design quality. Scripting for Automation: Experience scripting with Python, Perl, or TCL to automate verification workflows and enhance productivity. Coverage Analysis: Familiar with coverage-driven verification methodologies (functional and code coverage). Team Collaboration: Excellent communication and teamwork skills for efficient interaction with design and architecture teams. Problem Solving: Strong analytical skills to identify, debug, and resolve complex design and verification issues. Nice To Have Experience with formal verification tools. Exposure to FPGA prototyping and hardware emulation. Knowledge of industry standard protocols (e.g., AXI, PCIe, USB). Skills: systemverilog,uvm,functional verification,coverage analysis,synopsys vcs,fpga prototyping (nice to have),scripting (python, perl, tcl),verilog,simulation tools (modelsim, cadence incisive, synopsys vcs),testbench development (systemverilog, uvm, verilog, vhdl),python,formal verification tools (nice to have),vhdl,team collaboration,rtl verification,protocol knowledge (axi, pcie, usb - nice to have),modelsim,problem solving,cadence incisive,perl,tcl

About Company Espressif Systems (688018) is a public multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power IoT solutions. We have created the popular ESP8266 and ESP32 series of chips, modules and development boards. By leveraging wireless computing, we provide green, versatile and cost-effective chipsets. We have always been committed to offering IoT solutions that are secure, robust and power-efficient. By open-sourcing our technology, we aim to enable developers to use Espressif’s technology globally and build smart connected devices. In July 2019, Espressif made its Initial Public Offering on the Sci-Tech Innovation Board (STAR) of the Shanghai Stock Exchange (SSE). Espressif’s Technology Center in Pune (Baner), India focuses on Digital IP development, embedded software engineering and IoT solutions development for our growing customers. About Role Job Responsibilities Digital IP design Perform Lint/CDC/LEC/DFT/Low-Power analysis Module level synthesis and timing constraints Must have worked on ARM/RISC-V CPU based designs Familiarity with FPGA/Silicon validation using C based tests and usage of standard debugging tools Qualifications M.Tech/ B.Tech in the field of VLSI/Electronics engineering with 4 to 8 years of experience. Proficiency in System Verilog for RTL logic design and verification. Strong understanding of CPU pipeline and computer architecture is a must. EDA tool knowledge of Design Compiler, PrimeTime is preferred. Automation skills in PERL and/or TCL and/or Shell* is an added plus. Team player, with good problem solving and communication skills.

Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 10+ years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement

We are seeking an experienced and motivated FPGA Verification Team Lead to join our hardware engineering team. In this role, you will plan and build a UVM SV environment and lead a team of verification engineers responsible for ensuring the functional verification of a full FPGA design. Duties and Responsibilities: Lead and mentor FPGA verification engineers Plan and implement verification plans, strategies, and methodologies Work closely with FPGA designers and system architects Develop and maintain verification environments and agents using System Verilog UVM methodologies Monitor and report verification progress, coverage metrics, and quality indicators. Support regression testing, bug tracking, and issue resolution during the development cycle. Track verification progress using Agile tools (e.g., Jira, Azure DevOps) and provide regular status updates and metrics. Technical Requirements: Bachelor’s degree in electrical engineering, Computer Engineering or Computer Science 10+ years of experience in FPGA or ASIC verification, with at least 2 years in a leadership or team lead role Strong hands-on experience in writing System-verilog UVM agents and full UVM environments from scratch Strong hands-on experience in writing verification plans and coverage plans Solid understanding of FPGA architecture and RTL design Familiarity with version control systems (e.g., Git) and issue tracking tools (e.g., Jira). Excellent leadership, communication, and organizational skills Strong experience with simulation tools such as Xcelium, Questasim or VCS Strong debug capabilities • Strong hands-on experience in writing System-Verilog UVM agents and full UVM environments from scratch • Strong hands-on experience in writing verification plans and coverage plans Preferred technical Requirements: Graduated with honors or equivalent distinctions Academic honors, scholarships, or recognition demonstrating intellectual capability Knowledge of automation frameworks and CI/CD tools: Azure DevOps, Atlassian, GIT Experience in programming and scripting languages: Bash, Python Experience in using MATLAB models and generators as part of the verification flow Experience in DevOps tools like Azure DevOps Good knowledge of signal processing · No of years of experience: 10 - 15 years · Managerial experience: 3 - 4 years · Technical Lead experience: 4 - 5 years

Job Description We are seeking a highly skilled and motivated Firmware Development Engineer with hands-on experience in embedded systems development and testing. The ideal candidate will be proficient in C programming, device driver development, and debugging complex firmware issues across pre-silicon and post-silicon platforms. Experience range 6+ Yrs. 1 Mid-Level Firmware Engineer capable of writing C test cases on A78 core with device driver for low/high speed interfaces. Zephyr OS or ARM experience which we are looking for Expert C programming experience & debugging skills for embedded systems. Working experience and/or exposure to firmware testing platforms including: Emulation and post Si. Prior involvement in board, processor, or ASIC bring-up. Proven ability to methodically root-cause complex failure mechanisms at the IP, subsystem and/or system level. Knowledge of firmware algorithms used in any Host protocols such as: SCSI, SATA, eMMC, USB, PCIe, SPI, DDR, NVMe is an added advantage. Knowledge on security protocols is an added advantage. Experience in hardware/software interfaces and debuging sophisticated issues in CPU and firmware using JTAG, source code debuggers and other tools. Experience with source control systems including git/gerrit Working experience with Python, C++, UVM, System Verilog and Verilog is highly preferred Solid understanding of firmware development cycle, integration and verification/validation for pre-si and post-si for SoC designs. Job Responsibilities 6+ years of software development and testing. Experience in designing complex multithreaded Performant SW. Experience in designing SW API interfaces. Experience in C/C++ programming. Experience with Multi-threaded software development in Linux environment. Experience with Embedded IP subsystems e.g. Ethernet/PCIe/SPI/I2C/USB/GPIO/Memory architectures /DDR/SDRAM/DMA. Experience with development of software targeted for x86; standalone and RTOS platforms Experience in low level driver development; register interface programming; general algorithms and data structures; bootloaders/Uboot. Experience working with and integrating open-source software. Strong debugging skills at device and board level using JTAG debuggers. Experience in Software programming for FPGAs is an advantage. Scripting language experience like Perl; Python or TCL. Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field Skills (competencies) Verbal Communication

Job Description About ASM Auto: We are seeking talented and motivated individuals to join our team in developing cutting-edge solutions with Application-Specific Microcontrollers (MCUs) for the rapidly evolving automotive industry. Our MCUs power a wide range of critical vehicle functions, including traction control, onboard charging (OBC) and DC-DC converters, advanced lighting systems, body control modules, engine management, and braking systems. Additionally, we are at the forefront of innovation with zonal microcontrollers designed to enable software-defined vehicles, paving the way for greater functionality, scalability, and efficiency. Our products shape the future of automotive technology and create impactful solutions for modern mobility challenges. https://www.ti.com/applications/automotive/overview.html Role: Senior Design Engineer (RTL) We are looking for an experienced Senior RTL Design Engineer to join our team in developing cutting-edge automotive microcontroller solutions. The ideal candidate will have deep understanding of RTL design and SoC integration, particularly in the context of ARM-based architectures, and a proven ability to collaborate across multiple engineering disciplines to deliver high-quality solutions for complex systems. Key Responsibilities Define and develop microarchitecture for various subsystems, including CPU subsystems, low-power subsystems, and Reset & Clock Management modules. Own SoC integration for automotive MCUs, ensuring efficient, scalable designs. Collaborate with IP teams, Systems, and Architecture teams to derive requirements, co-develop microarchitecture, and align on design goals for IPs, subsystems, and SoC. Work closely with cross-functional teams such as Design Verification (DV), Design for Testability (DFT), Emulation, and Physical Implementation to ensure quality deliverables. Participate in debug sessions, design reviews, and ensure design robustness and compliance with industry standards. Qualifications Qualifications and Skills Required: Education: Bachelor’s or Master’s degree in Electrical Engineering (EE), Electronics & Communication Engineering (ECE), Computer Science (CS), or a related specialization. Experience: 2-5 years of hands-on experience in RTL development for IPs and SoCs. Technical Expertise Experience in SoC integration with ARM processors and ARM bus architectures. Good understanding of SoC reset and clocking architectures. Experience with standard interfaces like SPI/QSPI, I2C, Debug/Trace, CAN, and others. Expertise in industry-standard front-end (FE) tools and flows, including Lint, CDC, LEC, and power estimation tools such as Jasper Gold, Conformal, Joules, etc. Knowledge of DFT concepts and ability to design for testability. Good understanding of constraints, timing analysis, and optimization techniques. Proficiency in system verilog and verilog. Experience with industry-standard simulators (e.g., Incisive) and formal verification tools. Soft Skills Exceptional problem-solving and debugging skills. Strong written and verbal communication skills for effective collaboration and reporting. Ability to work in a team-oriented environment and guide junior engineers when needed. Preferred Qualifications Experience in automotive-grade SoC designs and compliance with ISO 26262 (Functional Safety) standards. Familiarity with power management techniques and low-power design principles. Knowledge of scripting languages such as Python, Perl, or TCL for automation. About Us Why TI? Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. About Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com . Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. If you are interested in this position, please apply to this requisition. About The Team TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ The Role The person will be part of AMD's DCGPU Performance Verification team. This team is part of AMD's global Data Center Performance teams and plays a critical role in next generation AMD Data Center GPU SoC design. Involves having deep understanding of existing AMD X86 SoC architecture/microarchitecture including CPU/ Cache Hier, Memory Subsystem and IO subsystem; debugging performance issues of RTL, giving feedback to design team for latest gen SoC in pre-silicon and emulation environment. We highly encourage people with a creative bent of mind and with a natural ability to dive into the details. This team is a perfect place for people who can understand the present and envision the future. If you find yourself to be a person who wants to go that extra mile to refine an existing process and also understands the opportunities to make it better, if you are the one who has innovative ideas in your brain waiting to find a proper stage to come out, we can offer you the perfect ground for that. The Person Should have excellent inter-personal, communication skills and ability to work in a fast-paced exciting environment. Continuous learning has always been the moto in this ever changing industry. An ideal person for this role should be a self-learner and always ready to upgrade his/her skills to stay abreast with the technology. The person need to drive and enable team to execute on the projects with respect to timelines and ensure quality of execution. The person should closely interact with all cross functional teams on dependencies closure and alignment for achieving overall SOC performance bounding box targets. Key Responsibilities Lead the team for performance verification and verify performance of complex SoC Project schedule and detailed resource planning with respect to SOC test plans Performance verification at full chip env involves Graphic/MultiMedia Subsystem , CPU, Memory Subsystem and IO Subsystem perf verification. Enabling team to write specific targeted tests to measure the performance of the SoC In coordination with Perf architects, driving tuning of performance results to meet product bounding box Involves having a deep understanding of SoC micro-architecture and triaging performance issues in RTL and simulator Skillset Enabling team to debug triage of failures from simulation and emulation environment for SoC or sub level regressions. Automation using Perl/Ruby and creating tools using perl/ruby or AMD verification methodology (primarily in C++) to enhance the functional debug and triage process. On a need basis, work on Post-Si bug recreation Preferred Experience Experience: 15+ years' experience in processor/ASIC performance verification and correlation and managing experienced team Experience in building team to accomplish SOC performance goals by closely working with cross functional teams Experience in micro-architecture testing for modern high-performance processors. Experience in writing tests and building infrastructure that tests performance of modern processors. Experience in application performance analysis Programming/Scripting Skills C, C++, Perl, Python. Solid background and understanding of Digital Design, RTL design , improving model performance and Processor Architecture Strong troubleshooting, analytical and debug skills. Prior experience in performance correlation of Processor subsystems is a plus. Excellent knowledge of computer architecture with relevant research and project work or industry experience Strong programming skills (C/C++ and assembly) and System verilog Academic Credentials Bachelors/Masters in Computer Science/Electrical/Electronics Engineering with relevant course and research work LOCATION: Hyderabad/Bangalore Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Job role: At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. We're looking for ASIC Digital Verification Engineers with different experience levels to join the team! Does this sound like a good role for you? You will be working on VLSI IP verification of controllers related to complex protocols. You will be part of the Solutions Group at our Bangalore Design Center, India. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Verification domain. Job Responsibilities - Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design for some of the components of the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as Ethernet/DSC/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/DDR/PCIe/ USB/ MIPI Be an individual contributor in the Verification Tasks – Architect testbenches, coding of TE, debug, verification coverage improvement, etc. Will contribute to technical review of TE Code of medium complexity. Will contribute to technical process and quality improvement to achieve high quality deliveries Will be expected to Solve complex/ abstract problems The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in CRV environment. The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide. May need to take the role of technical lead for a few of the components of the Test Environment and achieve high quality verification with a small team of verification engineers. The role offers ample scope to mentor junior engineers and interns and to enhance ones’ leadership skills. Key Qualifications And Experience Must have BSEE/ MSEE in EE with 6 to 12 years of relevant experience in the following areas: Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc. Knowledge of one or more of protocols: Ethernet/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/USB/ DDR/PCIe MIPI/DSC. Knowledge of Ethernet protocol will be plus. Hands on experience with creating detailed design of components of Test Environment from Functional Specifications/ Test Environment Specifications. The TE must have used methodologies such as UVM, OVM Test Planning, Coverage Planning, Assertion Planning Hands on experience with System Verilog coding and Simulation tools; Deep Knowledge of OOPs Concepts Experience with Perforce or similar revision control environment Knowledge of Perl/Shell scripts. Exposure to quality processes in the context of IP design and verification is an added advantage In addition, the candidate should have good communication skills, will be a team player, and will have good problem-solving skills. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Principal IP/RTL Design Engineer for TPU Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore IP/RTL Design Engineer for TPU Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Hyderabad /Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore A US based well-funded product-based startup looking for Highly talented Senior Physical Fri, Mar 28 at 9:39 AM Principal / Staff IP/RTL Design Engineer (AI Accelerator) – Multiple positions - Hyderabad /Bangalore Well-funded product startup is looking for RTL Design Engineers to contribute to the development of novel high performance AI accelerators from scratch. In this role you will collaborate with cross-functional teams, including architect, software, verification, physical design, systems engineers, to define and implement next generation AI architectures. We are seeking highly experienced individuals who have a passion for innovation and are excited about the opportunity to create world class products from India. The key responsibilities for this role include, but are not limited to: Key Responsibilities Design and implement high-performance TPUs/MPUs and other related AI blocks using RTL. Own IP/block-level RTL from spec to GDS, including design, synthesis, and timing closure. Optimize design for power, performance, and area (PPA). Interface with physical design and DFT (Design for Test) engineers for seamless integration. Drive design reviews, write design documentation, and support post silicon bring-up/debug. Minimum Qualifications B.S./M.S./Ph.D. in ECE/CS from top engineering college with 5-15 years of related experience. Previous experience in either high performance processor design or AI accelerator design is plus. Clear understanding of floating-point arithmetic, vector processing, SIMD, MIMD, VLIW, EPIC concepts. Strong grasp of digital design fundamentals, computer architecture, virtual memory and high-speed data-path design. Proficiency in Verilog/SystemVerilog and simulation tools. Experience with EDA tools (e.g., Synopsys, Cadence) for synthesis, lint, CDC, and timing analysis. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

We are looking for a highly skilled and motivated Firmware Development Engineer with over 6 years of experience in embedded systems development and testing. As a Mid-Level Firmware Engineer, your responsibilities will include writing C test cases on A78 core with device driver for low/high-speed interfaces. You should have expertise in Zephyr OS or ARM, along with proficient C programming skills and the ability to debug complex firmware issues. Your role will involve working with firmware testing platforms such as emulation and post Si, as well as participating in board, processor, or ASIC bring-up. You should have a proven track record of methodically identifying and resolving complex failure mechanisms at the IP, subsystem, and system levels. Knowledge of firmware algorithms related to Host protocols like SCSI, SATA, eMMC, USB, PCIe, SPI, DDR, NVMe will be advantageous. Additionally, familiarity with security protocols is a plus. Experience in hardware/software interfaces and debugging advanced issues in CPU and firmware using JTAG, source code debuggers, and other tools is essential. Proficiency in source control systems like git/gerrit and working knowledge of Python, C++, UVM, System Verilog, and Verilog is highly desirable. You should have a solid understanding of the firmware development cycle, integration, and verification/validation for both pre-si and post-si SoC designs. Your responsibilities will also include software development and testing, designing complex multithreaded Performant SW, creating SW API interfaces, and programming in C/C++. Experience with multi-threaded software development in a Linux environment, as well as familiarity with Embedded IP subsystems (e.g., Ethernet, PCIe, SPI, I2C, USB, GPIO, Memory architectures, DDR, SDRAM, DMA) is required. Knowledge of software development for x86 platforms, low-level driver development, register interface programming, algorithms, data structures, and bootloaders/Uboot is essential. Strong debugging skills using JTAG debuggers at the device and board level, along with experience in software programming for FPGAs, will be advantageous. Proficiency in scripting languages such as Perl, Python, or TCL is a plus. A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field is required for this position. If you possess excellent verbal communication skills and meet the above qualifications, we encourage you to apply for this exciting opportunity in Firmware Development Engineering.,

As a SOC Verification Engineer with 2-8 years of experience, you will be responsible for verifying complex System on Chip (SOC) designs. You should have a strong proficiency in System Verilog and hands-on experience in Verilog and System Verilog. It is essential to have a minimum of 2 years of experience specifically in SOC Verification. Expertise in C/Assembly languages is also required for this role. Your role will be based in Delhi/NCR, where you will collaborate with a team of professionals to ensure the successful verification of SOC designs. As a self-motivated individual, you will actively contribute to the verification process and work effectively within a team environment. Excellent communication skills are crucial for this position as you will be required to interact with team members and other stakeholders regularly. Being a good team player is another key requirement for this role, as you will be working closely with colleagues to achieve common verification goals. If you are passionate about SOC Verification and possess the necessary skills and experience, we encourage you to apply for this exciting opportunity. Join our team and be a part of cutting-edge SOC design verification projects.,

As an ASIC RTL Engineer at Google, you will be part of a team that is dedicated to developing custom silicon solutions for Google's direct-to-consumer products. Your role will involve pushing boundaries and contributing to the innovation that drives products loved by millions worldwide. Your expertise will play a crucial role in shaping the next generation of hardware experiences, focusing on delivering unparalleled performance, efficiency, and integration. In this role, you will lead a team of ASIC RTL engineers, overseeing sub-system and chip-level integration activities. Your responsibilities will include planning tasks, conducting code and design reviews, and developing complex features. You will collaborate closely with the architecture team to develop implementation strategies that meet quality, schedule, performance, power, and area requirements for sub-system/chip-level integration. Additionally, you will work with a cross-functional team comprising Verification, Design for Test, Physical Design, and Software teams. Your role will involve making design decisions and representing project status throughout the development process. Your contributions will be essential in ensuring the successful execution of projects and meeting the goals set for each stage of development. If you have a Bachelor's degree in Electrical Engineering or Computer Science, along with 8 years of experience in high-performance design and multi-power domains with clocking, and have worked on multiple SoCs with silicon success, this role could be an exciting opportunity for you. Experience with Verilog or System Verilog language is essential, and familiarity with ASIC design methodologies for front quality checks and chip design flow will be advantageous. Join us at Google, where we combine the best of Google AI, Software, and Hardware to create radically helpful experiences. Our mission is to make the world's information universally accessible and useful, and your contributions as an ASIC RTL Engineer will play a significant role in achieving this goal.,

As an ASIC Design Engineer specializing in UPF and Low Power Design, you will be responsible for owning and driving RTL design for complex digital blocks with multiple power domains. Your role will involve defining, implementing, and validating power intent using UPF 2.0/3.0 for ASIC and SoC designs. Collaboration with verification and physical design teams will be crucial to ensure correct propagation and verification of power intent across the flow. You will work closely with architecture teams to define low power design strategies including power gating, clock gating, and multi-voltage domains. Additionally, analyzing and debugging power-related issues during RTL and gate-level simulations will be part of your responsibilities. It is essential to develop and maintain design documentation such as micro-architecture specs and power intent specifications. Supporting integration and implementation teams in handling low power design constraints and challenges will also be a key aspect of your role. To be successful in this position, you should hold a Bachelors or Masters degree in Electronics/Electrical Engineering or a related discipline. With a minimum of 7 years of ASIC front-end design experience, including at least 3 years focused on low power/UPF design, you should be proficient in RTL coding using Verilog/SystemVerilog with strong design fundamentals. A deep understanding of low power architecture techniques like power gating, retention, isolation, and voltage scaling is required. Hands-on experience with UPF-based flows and power-aware tools from Synopsys, Cadence, or Mentor is essential. Experience in running LINT, CDC, and synthesis with power intent, along with excellent debugging and problem-solving skills, are also necessary. Preferred skills include exposure to DFT constraints and the impact of power intent on scan/ATPG, familiarity with scripting languages like Python/Perl/TCL for automation, and experience in collaborating across global design and verification teams. A working knowledge of timing closure, clock domain crossing (CDC), and logic equivalence checks (LEC) would be beneficial in this role. Joining BOLTCHIP will offer you the opportunity to be part of a cutting-edge semiconductor design team focused on innovation and quality. You will collaborate with top-tier professionals in the low-power design domain and benefit from competitive compensation and opportunities for growth. If you meet the requirements and are excited about this opportunity, please apply by sending your resume to jasmine.h@boltchip.com.,

As a Verification Engineer at Marvell, you will play a crucial role in leading the verification efforts for blocks, subsystems, and top-level verification. You will be responsible for developing and maintaining UVM-based verification environments, defining and reviewing test plans with architecture and design teams, and verifying designs using directed and constrained random techniques. Your expertise will be utilized to maintain regression, debug failures, and analyze coverage, driving verification to meet coverage targets. You will also contribute to next-generation data processing and hardware accelerator verification, focusing on networking domain verification for future solutions, and ensuring design closure using innovative and automated techniques. To excel in this role, you should possess a Bachelors or Masters degree in Computer Science, Electrical Engineering, or a related field with 8+ years of professional experience. Your strong experience with Verilog, SystemVerilog, and UVM, along with expertise in unit and subsystem verification and modern verification concepts, will be essential. Proficiency in SystemVerilog, C, C++, and scripting (Perl, Tcl, Python preferred) is required, as well as strong debugging skills and verification flow optimization. You will collaborate with design teams on specs, test plans, and verification strategies, develop and maintain UVM-based testbenches for ASIC SoCs, execute verification, maintain regressions, and debug failures. Excellent verbal and written communication skills will also be important in this role. At Marvell, you will be part of a team that is empowering the global data economy. With competitive compensation and great benefits, you will enjoy a workstyle within an environment of shared collaboration, transparency, and inclusivity. Marvell is dedicated to providing its employees with the tools and resources they need to succeed in doing work that matters, and to grow and develop within the company. For more information on what it's like to work at Marvell, visit our Careers page.,

As a Sr. Principal Digital Design Engineer at OnSemi in Bengaluru, India, you will be an integral part of the Power Management product development team, focusing on designing innovative solutions for consumer, industrial, and automotive applications. Your responsibilities will include collaborating with various product lines for RTL implementation of power converter controller designs, digital design architecture, low power design, synthesis, timing analysis, and physical design interface using state-of-the-art RTL2GDS flows. You will work closely with a dynamic team of engineers, design architects, digital verification, project management, and analog design teams across different geographies. Your role will involve implementing micro-architecture to RTL, supporting pre-silicon platforms, owning the technical outcome of Power Management ICs, and leading customer support, production issues, system development, and failure analysis. To excel in this role, you should possess a Bachelor's degree in Electrical Engineering with 12 years of experience or a Master's degree with 10 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. A deep understanding of the digital design flow, RTL design, CDC, synthesis, timing analysis, system Verilog, Verilog, TCL, Perl/Python/XML programming languages, and various protocols is essential. Onsemi (Nasdaq: ON) is dedicated to driving disruptive innovations in automotive and industrial markets, aiming to accelerate change in megatrends such as vehicle electrification, sustainable energy grids, industrial automation, and 5G infrastructure. With a focus on intelligent power and sensing technologies, Onsemi is committed to creating a safer, cleaner, and smarter world. To learn more about our company benefits, visit: https://www.onsemi.com/careers/career-benefits Join us at Onsemi to be part of a high-performance team that fosters innovation and offers a positive recruitment experience, cultivating a strong brand as an exceptional workplace.,

www.omnidesigntech.com Senior SoC Director / SoC Director Bangalore / Hyderabad About Omni Design Technologies Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated system-on-chip (SoC), in applications ranging from 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the internet-of-things (IoT). Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few MSPS to more than 100 GSPS sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins-Colorado, Bangalore-India, Hyderabad-India, Dublin-Ireland, Boston-Massachusetts. Bangalore Engineering – Digital Circuit Design / Hyderabad / Bangalore SOC Development – Engineering / Full-time / Hybrid Omni Design is working on exciting solutions and chips for next generation automotive and space applications and looking for talented and capable engineers. The Manager of digital and mixed-signal engineering will be responsible for development of mixed-signal SOC being developed at ODT and build the digital engineering team and will work Analog/RF engineering, FW engineering, verification, Systems Validation team, Operations, SOC Architects, and report to the VP / SVP of ASIC Engineering. Roles and Responsibilities Manage digital team, hire, and retain best talent Lead SOC integration design team to develop and productize next generation mixed-signal RF/communication SOCs Work with cross-functional project teams to define product specifications, system architecture, HW/SW partitioning, and execution plan Implement best SoC development practices and improve design methodology to maximize efficiency and predictability Deliver chip architecture, design, integration, programming model, verification, and manage hand-off to backend Support Silicon and System Validation, support system integration, and production testing Drive innovation and provides leadership to the organization to ensure world-class system solutions and flawless execution Qualifications BSEE Required, MSEE Preferred Proven track record of success in high-performance/high-volume semiconductor industry SoC, embedded CPU and bus architectures, networking, and control interfaces Communications / DSP algorithms and power / area efficient implementations Digital IC design, design for low power and high speed, design for test (DFT) System modeling, RTL coding, Lint / CDC checking, simulation, synthesis, power analysis, timing analysis in Cadence / Synopsys design environments Directed and constrained random verification, UVM methodology Embedded systems FPGA emulation, lab debug and chip validation Project planning and execution, and performing design tradeoffs to achieve performance, power, die size, and schedule targets Self-motivated, excellent communication skills, and ability to excel and to provide leadership in a fast-paced environment Senior Management experience preferred Work with architecture, physical design, and design teams to lead the implementation of the digital architecture. Develop and refine specification of the micro-architecture for the digital architecture. Is in tune with industry trends and contributes to consistent roadmap decisions. Experience 15-30+ years of experience in the area of RTL design and verification of silicon At Least 3+ years experience in leading low-power mixed-Signal SOC design 10+ years of experience with FPGA architecture specification and design (Altera or Xilinx) for high-speed serial protocols, including USB-SS, PCIe, SATA/SAS, DisplayPort Experience in leading, specifying, and work with Analog/RF team in developing, verifying, and productizing SERDES, CDR, and PLL/DLL designs Experience with USB 3.0, DisplayPort, PCIe, or SATA based silicon designs preferred Strong background in analog/mixed-signal integrated SOC Development Strong Hardware design knowledge and familiarity with signal integrity Strong foundation in SoC architecture, design, verification and physical implementation Strong analytical problem solving, and attention to details Knowledge of wireless, mobile, and storage domains Expertise in Verilog/System Verilog, C/C++/SystemC, UVM, Scripting languages like Perl/Python, etc. Excellent technical documentation skills Excellent written and verbal communication skills Excellent interpersonal skills, self-motivated, self-starter Experience in startup environment Expectations Put the RTL for the Full chip together. Evaluate the IP we have to license – like PCIe, LPDDR4, JESD 204C PHY Help develop any BIST Work with Verification Team to develop the FC Simulation test suites Develop the RTL for the various state machines and interfaces Run a few of the simulations Help with the FC simulations debug Help close the timing issues if any come up and work with the PD person to resolve any SI issues. Be a mentor and lead a team of Digital design engineers Work with Systems and Test engineering team to help validate the parts and release them to production We are looking for trailblazers ... We strongly believe that the pace of the ongoing hardware revolution will be greatly accelerated by Design’s IP cores and the rapidly emerging semiconductor embedded design business ecosystem. we have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring our vision to fruition. If you are interested in making an impact as part of a young, fast growing, cutting edge technology company, please reach out to us. We are a equal opportunity employer. We offer excellent compensation. We seek individuals that share our high standards and commitment to excellence. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com 'Mining The Knowledge Community'

Principal /Senior Staff / Staff PCIe/CXL based memory expander Verification PCIe/CXL based memory expander - Verification Engineer: looking for experienced and talented professional for CXL based memory expander. Minimum Qualifications: BE/BTech in Electrical/Computer engineering with 8+ years of experience or ME/MTech in Electrical/Computer engineering with 6+ years of experience Should have hands on experience in System Verilog, UVM and Object-Oriented Programming Proven track record in USB/PCIe/CXL IP verification both on FPGA and ASIC, with ability to bring up testbenches from scratch to defining test plan and sign-off for tape out. Integration and verification of complex System IP features. Work closely with RTL designers and SOC team to scope out integration and verification requirements. Good understanding of any memory protocol like DDR, ONFI, NAND, Flash SPI/QSPI. Proficiency in bus protocols AXI/AHB Proficiency in scripting languages like Perl, Python etc. Strong communication, collaboration, and interpersonal skills Strong analytical and problem-solving skills Preferred Qualifications: Experience in verification of PCIe/CXL based sub-system/SoC/IP. Knowledge of SoC with processor boot-flow. Knowledge of FPGA setup and running FPGA simulations. Experience in GLS is added advantage. Verification expertise in Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols. Experience with compliance at the physical and transaction layers for PCIe/CXL endpoints or root ports. Analysing performance metrics of CXL/PCIe. System-level verification experience for PCIe/CXL. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"